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From: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
To: u-boot@lists.denx.de
Subject: [PATCH 18/22] x86: mtrr: Add support for writing to MTRRs on any CPU
Date: Wed, 10 Jun 2020 15:28:22 +0200	[thread overview]
Message-ID: <OF6E348790.9A47AA8E-ONC1258583.0046C3CF-C1258583.004A0277@br-automation.com> (raw)
In-Reply-To: <20200521202309.18.I79f1122b437ee390b87d4446bbcfc51dd581d908@changeid>

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH 18/22] x86: mtrr: Add support for writing to MTRRs on any CPU
> 
> To enable support for the 'mtrr' command, add a way to perform MTRR
> operations on selected CPUs.
> 
> This works by setting up a little 'operation' structure and sending it
> around the CPUs for action.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/cpu/mtrr.c         | 81 +++++++++++++++++++++++++++++++++++++
>  arch/x86/include/asm/mtrr.h | 21 ++++++++++
>  2 files changed, 102 insertions(+)
> 
> diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
> index a48c9d8232e..25f317d4298 100644
> --- a/arch/x86/cpu/mtrr.c
> +++ b/arch/x86/cpu/mtrr.c
> @@ -221,3 +221,84 @@ int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
>  
>  	return 0;
>  }
> +
> +/** enum mtrr_opcode - supported operations for mtrr_do_oper() */
> +enum mtrr_opcode {
> +	MTRR_OP_SET,
> +	MTRR_OP_SET_VALID,
> +};
> +
> +/**
> + * struct mtrr_oper - An MTRR operation to perform on a CPU
> + *
> + * @opcode: Indicates operation to perform
> + * @reg: MTRR reg number to select (0-7, -1 = all)
> + * @valid: Valid value to write for MTRR_OP_SET_VALID
> + * @base: Base value to write for MTRR_OP_SET
> + * @mask: Mask value to write for MTRR_OP_SET
> + */
> +struct mtrr_oper {
> +	enum mtrr_opcode opcode;
> +	int reg;
> +	bool valid;
> +	u64 base;
> +	u64 mask;
> +};
> +
> +static void mtrr_do_oper(void *arg)
> +{
> +	struct mtrr_oper *oper = arg;
> +	u64 mask;
> +
> +	switch (oper->opcode) {
> +	case MTRR_OP_SET_VALID:
> +		mask = native_read_msr(MTRR_PHYS_MASK_MSR(oper->reg));
> +		if (oper->valid)
> +			mask |= MTRR_PHYS_MASK_VALID;
> +		else
> +			mask &= ~MTRR_PHYS_MASK_VALID;
> +		wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), mask);
> +		break;
> +	case MTRR_OP_SET:
> +		wrmsrl(MTRR_PHYS_BASE_MSR(oper->reg), oper->base);
> +		wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), oper->mask);
> +		break;
> +	}
> +}
> +
> +static int mtrr_start_op(int cpu_select, struct mtrr_oper *oper)
> +{
> +	struct mtrr_state state;
> +	int ret;
> +
> +	mtrr_open(&state, true);
> +	ret = mp_run_on_cpus(cpu_select, mtrr_do_oper, oper);
> +	mtrr_close(&state, true);
> +	if (ret)
> +		return log_msg_ret("run", ret);
> +
> +	return 0;
> +}
> +
> +int mtrr_set_valid(int cpu_select, int reg, bool valid)

With the introduction of this function in this patch there are now two
conflicting implementations of mtrr_set_valid(), and this commit does not
compile.

The conflicting function is removed in the following patch. Could these
two patches be merged so we don't break bisectability?

> +{
> +	struct mtrr_oper oper;
> +
> +	oper.opcode = MTRR_OP_SET_VALID;
> +	oper.reg = reg;
> +	oper.valid = valid;
> +
> +	return mtrr_start_op(cpu_select, &oper);
> +}
> +
> +int mtrr_set(int cpu_select, int reg, u64 base, u64 mask)
> +{
> +	struct mtrr_oper oper;
> +
> +	oper.opcode = MTRR_OP_SET;
> +	oper.reg = reg;
> +	oper.base = base;
> +	oper.mask = mask;
> +
> +	return mtrr_start_op(cpu_select, &oper);
> +}
> diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
> index 476d6f8a9cf..6c50a67e1fe 100644
> --- a/arch/x86/include/asm/mtrr.h
> +++ b/arch/x86/include/asm/mtrr.h
> @@ -159,6 +159,27 @@ int mtrr_set_next_var(uint type, uint64_t base, uint64_t size);
>   */
>  void mtrr_save_all(struct mtrr_info *info);
>  
> +/**
> + * mtrr_set_valid() - Set the valid flag for a selected MTRR and CPU(s)
> + *
> + * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...)
> + * @reg: MTRR register to write (0-7)
> + * @valid: Valid flag to write
> + * @return 0 on success, -ve on error
> + */
> +int mtrr_set_valid(int cpu_select, int reg, bool valid);
> +
> +/**
> + * mtrr_set() - Set the valid flag for a selected MTRR and CPU(s)
> + *
> + * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...)
> + * @reg: MTRR register to write (0-7)
> + * @base: Base address and MTRR_BASE_TYPE_MASK
> + * @mask: Mask and MTRR_PHYS_MASK_VALID
> + * @return 0 on success, -ve on error
> + */
> +int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
> +
>  #endif
>  
>  #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
> -- 
> 2.27.0.rc0.183.gde8f92d652-goog

regards, Wolfgang

  reply	other threads:[~2020-06-10 13:28 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-22  2:23 [PATCH 00/22] x86: Enhance MTRR functionality to support multiple CPUs Simon Glass
2020-05-22  2:23 ` [PATCH 01/22] x86: mp_init: Switch to livetree Simon Glass
2020-06-10 13:25   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 02/22] x86: Move MP code into mp_init Simon Glass
2020-06-10 13:25   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 03/22] x86: mp_init: Avoid declarations in header files Simon Glass
2020-06-10 13:25   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 04/22] x86: mp_init: Switch parameter names in start_aps() Simon Glass
2020-06-10 13:25   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 05/22] x86: mp_init: Drop the num_cpus static variable Simon Glass
2020-06-10 13:25   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 06/22] x86: mtrr: Fix 'ensable' typo Simon Glass
2020-06-10 13:26   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 07/22] x86: mp_init: Set up the CPU numbers at the start Simon Glass
2020-06-10 13:26   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 08/22] x86: mp_init: Adjust bsp_init() to return more information Simon Glass
2020-06-10 13:26   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 09/22] x86: cpu: Remove unnecessary #ifdefs Simon Glass
2020-06-10 13:26   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 10/22] x86: mp: Support APs waiting for instructions Simon Glass
2020-06-10 13:27   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 11/22] global_data: Add a generic global_data flag for SMP state Simon Glass
2020-06-10 13:27   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 12/22] x86: Set the SMP flag when MP init is complete Simon Glass
2020-06-10 13:27   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 13/22] x86: mp: Allow running functions on multiple CPUs Simon Glass
2020-06-10 13:27   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 14/22] x86: mp: Park CPUs before running the OS Simon Glass
2020-06-10 13:27   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 15/22] x86: mp: Add iterators for CPUs Simon Glass
2020-06-10 13:27   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 16/22] x86: mtrr: Use MP calls to list the MTRRs Simon Glass
2020-06-10 13:28   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 17/22] x86: mtrr: Update MTRRs on all CPUs Simon Glass
2020-06-10 13:28   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 18/22] x86: mtrr: Add support for writing to MTRRs on any CPU Simon Glass
2020-06-10 13:28   ` Wolfgang Wallner [this message]
2020-05-22  2:23 ` [PATCH 19/22] x86: mtrr: Update the command to use the new mtrr calls Simon Glass
2020-06-10 13:28   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 20/22] x86: mtrr: Restructure so command execution is in one place Simon Glass
2020-06-10 13:28   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 21/22] x86: mtrr: Update 'mtrr' to allow setting MTRRs on any CPU Simon Glass
2020-06-10 13:29   ` Wolfgang Wallner
2020-05-22  2:23 ` [PATCH 22/22] x86: mtrr: Enhance 'mtrr' command to list " Simon Glass
2020-06-10 13:29   ` Wolfgang Wallner
2020-05-22 10:54 ` [PATCH 00/22] x86: Enhance MTRR functionality to support multiple CPUs Andy Shevchenko
2020-05-22 13:42   ` Simon Glass

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