Re: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER

From: "Pradeep Satyanarayana" <pradeep@us.ibm.com>
To: Shahaf Shuler <shahafs@mellanox.com>
Cc: "bruce.richardson@intel.com" <bruce.richardson@intel.com>,
	Chao Zhu <chaozhu@linux.vnet.ibm.com>,
	Dekel Peled <dekelp@mellanox.com>, "dev@dpdk.org" <dev@dpdk.org>,
	David Christensen <drc@ibm.com>,
	"honnappa.nagarahalli@arm.com" <honnappa.nagarahalli@arm.com>,
	"konstantin.ananyev@intel.com" <konstantin.ananyev@intel.com>,
	"ola.liljedahl@arm.com" <ola.liljedahl@arm.com>,
	Ori Kam <orika@mellanox.com>,
	Thomas Monjalon <thomas@monjalon.net>,
	David Wilder <wilder@us.ibm.com>,
	Yongseok Koh <yskoh@mellanox.com>
Subject: Re: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER
Date: Sun, 24 Mar 2019 09:37:34 -0800	[thread overview]
Message-ID: <OFB810109E.4E511E37-ON882583C7.0060A84E-882583C7.0060D2F5@notes.na.collabserv.com> (raw)
In-Reply-To: <AM0PR0502MB3795753A8C8FE1874DFD1175C35D0@AM0PR0502MB3795.eurprd05.prod.outlook.com>

Shahaf Shuler <shahafs@mellanox.com> wrote on 03/23/2019 11:37:42 PM:

> From: Shahaf Shuler <shahafs@mellanox.com>
> To: "pradeep@us.ibm.com" <pradeep@us.ibm.com>, Thomas Monjalon
> <thomas@monjalon.net>
> Cc: "bruce.richardson@intel.com" <bruce.richardson@intel.com>, Chao
> Zhu <chaozhu@linux.vnet.ibm.com>, Dekel Peled <dekelp@mellanox.com>,
> "dev@dpdk.org" <dev@dpdk.org>, David Christensen <drc@ibm.com>,
> "honnappa.nagarahalli@arm.com" <honnappa.nagarahalli@arm.com>,
> "konstantin.ananyev@intel.com" <konstantin.ananyev@intel.com>,
> "ola.liljedahl@arm.com" <ola.liljedahl@arm.com>, Ori Kam
> <orika@mellanox.com>, David Wilder <wilder@us.ibm.com>, Yongseok Koh
> <yskoh@mellanox.com>
> Date: 03/23/2019 11:37 PM
> Subject: RE: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER
>
> Pradeep,
>
> Pradeep Satyanarayana wrote on Saturday, March 23, 2019 12:58 AM
> >Thomas Monjalon <thomas@monjalon.net> wrote on 03/22/2019 10:51:17 AM:
> >> Date: 03/22/2019 10:51 AM
> >> Subject: Re: [PATCH] eal/ppc: remove fix of memory barrier for IBM
POWER
> >>
> >> 22/03/2019 16:30, Pradeep Satyanarayana:
> >> > Thomas Monjalon <thomas@monjalon.net> wrote on 03/22/2019 01:49:03
AM:
> >> > > 22/03/2019 02:40, Pradeep Satyanarayana:
> >> > > > - rte_[rw]mb (general memory barrier) --> should be lwsync
> >> > >
> >> > > This is what may be discussed.
> >> > > The assumption is that the general memory barrier should cover
> >> > > all cases (CPU caches, SMP and I/O).
> >> > > That's why we think it should "sync" for Power.
> >> >
> >> > In that case, at a minimum we must de-link rte_smp_[rw]mb from
rte_[rw]mb
> >> > and retain it as lwsync. Agreed?
> >>
> >> I have no clue about what is needed for SMP barrier in Power.
> >> As long as it works as expected, no problem.
> >>
> >
> >We will try that out and report back here, later next week
>
> Till then, i think there are 2 orthogonal issues:
> 1. ppc rte_wmb is incorrect
> 2. ppc rte_smp_[rw]mb may be improved.
>
> for #1 the current patch from Dekel seems to be OK. do you agree?
> for #2 i guess you will check and come back w/ patch/answer?

That has been the line of thinking. However, we need to do some extensive
testing
to confirm that it all holds up.

Thanks
Pradeep
pradeep@us.ibm.com