[PATCH v1 00/43] x86: Programmatic generation of ACPI tables (Part C)

[PATCH v1 00/43] x86: Programmatic generation of ACPI tables (Part C)

[Simon Glass]

This series is split off from the original ACPI series and renumbered to
version 1.

It includes functions for generating more ACPI constructs as well as I2C,
GPIO and sound support. There are also quite a few patches related to
getting coral to work correctly with ACPI.

Changes in v1:
- Add a way to set the binman ROM offset
- Add linux/err.h header
- Capitalise ACPI_OPS_PTR
- Use acpi,ddn instead of acpi,desc
- Add a check for invalid node
- Add NHLT support
- Capitalise ACPI_OPS_PTR
- Rebase to master
- Use acpi,ddn instead of acpi,desc
- Drop the unwanted acpi_device_write_gpio_desc()
- Rename max97357a to max98357a
- Add NHLT support
- Capitalise ACPI_OPS_PTR
- Rebase to master
- Add a new patch to support building up an NHLT structure
- Add new patch to add error checking for csrt table generation
- Use acpi_get_path() to get device path
- Add new patch to improve designware_i2c debugging
- Capitalise ACPI_OPS_PTR

Simon Glass (43):
  binman: Allow setting the ROM offset
  binman: Refactor binman_entry_find() to allow other nodes
  binman: Add way to locate an entry in memory
  acpi: Allow creating the GNVS to fail
  dtoc: Support ACPI paths in of-platdata
  dm: core: Add a way of overriding the ACPI device path
  dm: acpi: Add support for the NHLT table
  acpi: Export functions to write sized values
  acpi: Support generation of a scope
  acpi: Support generation of a generic register
  acpi: mmc: Generate ACPI info for the PCI SD Card
  x86: Add bindings for NHLT
  acpi: Support generation of a device
  acpi: Support writing named values
  sound: Add an ACPI driver for Dialog Semicondutor da7219
  sound: Add an ACPI driver for Maxim MAX98357ac
  x86: pinctrl: Add a way to get the pinctrl reg address
  x86: pinctrl: Update comment for intel_pinctrl_get_pad()
  x86: pinctrl: Add multi-ACPI control
  x86: pinctrl: Set up itss in the probe() method
  x86: pinctrl: Drop the acpi_name member
  x86: Add support for building up an NHLT structure
  x86: Add error checking for csrt table generation
  x86: apl: Use memory-mapped access for VBT
  x86: gpio: Add support for obtaining ACPI info for a GPIO
  i2c: designware_i2c: Add a little more debugging
  i2c: Add log_ret() on error
  i2c: designware_i2c: Support ACPI table generation
  p2sb: Add a method to hide the bus
  x86: apl: Support set_hide() in p2sb driver
  x86: apl: Hide the p2sb on exit from U-Boot
  pmc: Move common registers to the header file
  x86: irq: Support flags for acpi_gpe
  x86: apl: Fix save/restore of ITSS priorities
  x86: Add debugging to table writing
  x86: apl: Adjust FSP-M code to avoid hard-coded address
  x86: Store the coreboot table address in global_data
  x86: mp: Allow use of mp_run_on_cpus() without MP
  x86: Update the comment about booting for FSP2
  x86: Drop setup_pcat_compatibility()
  x86: acpi: Correct the version of the MADT
  x86: Rename board_final_cleanup() to board_final_init()
  acpi: Enable ACPI table generation by default on x86

 arch/Kconfig                                  |   1 +
 arch/x86/cpu/acpi_gpe.c                       |  26 +
 arch/x86/cpu/apollolake/fsp_m.c               |   6 +-
 arch/x86/cpu/apollolake/fsp_s.c               |  56 +-
 arch/x86/cpu/baytrail/acpi.c                  |   4 +-
 arch/x86/cpu/coreboot/coreboot.c              |   4 +-
 arch/x86/cpu/coreboot/tables.c                |   8 +-
 arch/x86/cpu/cpu.c                            |  21 +-
 arch/x86/cpu/efi/app.c                        |   2 +-
 arch/x86/cpu/i386/cpu.c                       |   7 +-
 arch/x86/cpu/intel_common/itss.c              |  25 +-
 arch/x86/cpu/intel_common/p2sb.c              |  44 ++
 arch/x86/cpu/mp_init.c                        |  12 +-
 arch/x86/cpu/quark/acpi.c                     |   4 +-
 arch/x86/cpu/quark/quark.c                    |   2 +-
 arch/x86/cpu/start.S                          |   1 +
 arch/x86/cpu/tangier/acpi.c                   |   4 +-
 arch/x86/include/asm/acpi_nhlt.h              | 314 ++++++++++++
 arch/x86/include/asm/acpi_table.h             |  10 +-
 arch/x86/include/asm/global_data.h            |   2 +
 arch/x86/include/asm/intel_pinctrl.h          |  19 +-
 arch/x86/include/asm/itss.h                   |   2 +-
 arch/x86/include/asm/u-boot-x86.h             |   2 -
 arch/x86/lib/Makefile                         |   1 +
 arch/x86/lib/acpi_nhlt.c                      | 482 ++++++++++++++++++
 arch/x86/lib/acpi_table.c                     |  32 +-
 arch/x86/lib/fsp/fsp_common.c                 |   2 +-
 arch/x86/lib/fsp2/fsp_silicon_init.c          |   1 +
 arch/x86/lib/tables.c                         |  38 +-
 configs/sandbox_defconfig                     |   4 +
 doc/device-tree-bindings/device.txt           |  23 +
 doc/device-tree-bindings/sound/da7219.txt     | 113 ++++
 doc/device-tree-bindings/sound/max98357a.txt  |  22 +
 drivers/core/acpi.c                           |  34 ++
 drivers/gpio/intel_gpio.c                     |  49 +-
 drivers/i2c/designware_i2c.c                  |  35 +-
 drivers/i2c/designware_i2c.h                  |  15 +
 drivers/i2c/designware_i2c_pci.c              | 104 +++-
 drivers/i2c/i2c-uclass.c                      |   4 +-
 drivers/misc/irq-uclass.c                     |   2 +-
 drivers/misc/p2sb-uclass.c                    |  26 +-
 drivers/mmc/pci_mmc.c                         |  78 ++-
 drivers/pinctrl/intel/Kconfig                 |   4 +
 drivers/pinctrl/intel/pinctrl.c               |  21 +-
 drivers/pinctrl/intel/pinctrl_apl.c           |   4 -
 drivers/power/acpi_pmc/acpi-pmc-uclass.c      |   9 -
 drivers/sound/Kconfig                         |  18 +
 drivers/sound/Makefile                        |   2 +
 drivers/sound/da7219.c                        | 189 +++++++
 drivers/sound/max98357a.c                     | 160 ++++++
 include/acpi/acpi_device.h                    |   1 +
 include/acpi/acpigen.h                        | 165 ++++++
 include/binman.h                              |  30 ++
 include/dm/acpi.h                             |  39 ++
 .../interrupt-controller/x86-irq.h            |  14 +
 include/dt-bindings/sound/nhlt.h              |  23 +
 include/p2sb.h                                |  34 +-
 include/power/acpi_pmc.h                      |  14 +
 lib/acpi/acpigen.c                            | 134 +++++
 lib/binman.c                                  |  58 ++-
 test/dm/acpi.c                                |   3 +-
 test/dm/acpigen.c                             | 229 ++++++++-
 tools/dtoc/dtb_platdata.py                    |   4 +-
 tools/dtoc/dtoc_test_simple.dts               |   1 +
 tools/dtoc/test_dtoc.py                       |   3 +
 65 files changed, 2663 insertions(+), 137 deletions(-)
 create mode 100644 arch/x86/include/asm/acpi_nhlt.h
 create mode 100644 arch/x86/lib/acpi_nhlt.c
 create mode 100644 doc/device-tree-bindings/sound/da7219.txt
 create mode 100644 doc/device-tree-bindings/sound/max98357a.txt
 create mode 100644 drivers/sound/da7219.c
 create mode 100644 drivers/sound/max98357a.c
 create mode 100644 include/dt-bindings/interrupt-controller/x86-irq.h
 create mode 100644 include/dt-bindings/sound/nhlt.h

-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 01/43] binman: Allow setting the ROM offset

[Simon Glass]

On x86 the SPI ROM can be memory-mapped, at least most of it. Add a way
to tell binman the offset from a ROM address to a RAM address.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v1:
- Add a way to set the binman ROM offset

 include/binman.h |  8 ++++++++
 lib/binman.c     | 17 +++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/include/binman.h b/include/binman.h
index b462dc8542..baf49f7876 100644
--- a/include/binman.h
+++ b/include/binman.h
@@ -20,6 +20,14 @@ struct binman_entry {
 	u32 size;
 };
 
+/**
+ * binman_set_rom_offset() - Set the ROM memory-map offset
+ *
+ * @rom_offset: Offset from an image_pos to the memory-mapped address. This
+ *	tells binman that ROM image_pos x can be addressed at rom_offset + x
+ */
+void binman_set_rom_offset(int rom_offset);
+
 /**
  * binman_entry_find() - Find a binman symbol
  *
diff --git a/lib/binman.c b/lib/binman.c
index fd7de24bd2..dc3a880882 100644
--- a/lib/binman.c
+++ b/lib/binman.c
@@ -12,10 +12,21 @@
 #include <log.h>
 #include <malloc.h>
 
+/**
+ * struct binman_info - Information needed by the binman library
+ *
+ * @image: Node describing the image we are running from
+ * @rom_offset: Offset from an image_pos to the memory-mapped address, or
+ *	ROM_OFFSET_NONE if the ROM is not memory-mapped. Can be positive or
+ *	negative
+ */
 struct binman_info {
 	ofnode image;
+	int rom_offset;
 };
 
+#define ROM_OFFSET_NONE		(-1)
+
 static struct binman_info *binman;
 
 int binman_entry_find(const char *name, struct binman_entry *entry)
@@ -37,6 +48,11 @@ int binman_entry_find(const char *name, struct binman_entry *entry)
 	return 0;
 }
 
+void binman_set_rom_offset(int rom_offset)
+{
+	binman->rom_offset = rom_offset;
+}
+
 int binman_init(void)
 {
 	binman = malloc(sizeof(struct binman_info));
@@ -45,6 +61,7 @@ int binman_init(void)
 	binman->image = ofnode_path("/binman");
 	if (!ofnode_valid(binman->image))
 		return log_msg_ret("binman node", -EINVAL);
+	binman->rom_offset = ROM_OFFSET_NONE;
 
 	return 0;
 }
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 02/43] binman: Refactor binman_entry_find() to allow other nodes

[Simon Glass]

At present we can only read from a top-level binman node entry. Refactor
this function to produce a second local function which supports reading
from any node.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 lib/binman.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/lib/binman.c b/lib/binman.c
index dc3a880882..79d01230dd 100644
--- a/lib/binman.c
+++ b/lib/binman.c
@@ -29,25 +29,31 @@ struct binman_info {
 
 static struct binman_info *binman;
 
-int binman_entry_find(const char *name, struct binman_entry *entry)
+int binman_entry_find_(ofnode node, const char *name, struct binman_entry *entry)
 {
-	ofnode node;
 	int ret;
 
-	node = ofnode_find_subnode(binman->image, name);
 	if (!ofnode_valid(node))
-		return log_msg_ret("no binman node", -ENOENT);
+		node = binman->image;
+	node = ofnode_find_subnode(node, name);
+	if (!ofnode_valid(node))
+		return log_msg_ret("node", -ENOENT);
 
 	ret = ofnode_read_u32(node, "image-pos", &entry->image_pos);
 	if (ret)
-		return log_msg_ret("bad binman node1", ret);
+		return log_msg_ret("import-pos", ret);
 	ret = ofnode_read_u32(node, "size", &entry->size);
 	if (ret)
-		return log_msg_ret("bad binman node2", ret);
+		return log_msg_ret("size", ret);
 
 	return 0;
 }
 
+int binman_entry_find(const char *name, struct binman_entry *entry)
+{
+	return binman_entry_find_(binman->image, name, entry);
+}
+
 void binman_set_rom_offset(int rom_offset)
 {
 	binman->rom_offset = rom_offset;
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 03/43] binman: Add way to locate an entry in memory

[Simon Glass]

Add support for accessing an entry's contents in memory-mapped SPI flash.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/binman.h | 22 ++++++++++++++++++++++
 lib/binman.c     | 23 +++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/include/binman.h b/include/binman.h
index baf49f7876..e0b92075e2 100644
--- a/include/binman.h
+++ b/include/binman.h
@@ -9,6 +9,8 @@
 #ifndef _BINMAN_H_
 #define _BINMAN_H_
 
+#include <dm/ofnode.h>
+
 /**
  *struct binman_entry - information about a binman entry
  *
@@ -20,6 +22,18 @@ struct binman_entry {
 	u32 size;
 };
 
+/**
+ * binman_entry_map() - Look up the address of an entry in memory
+ *
+ * @parent: Parent binman node
+ * @name: Name of entry
+ * @bufp: Returns a pointer to the entry
+ * @sizep: Returns the size of the entry
+ * @return 0 on success, -EPERM if the ROM offset is not set, -ENOENT if the
+ *	entry cannot be found, other error code other error
+ */
+int binman_entry_map(ofnode parent, const char *name, void **bufp, int *sizep);
+
 /**
  * binman_set_rom_offset() - Set the ROM memory-map offset
  *
@@ -41,6 +55,14 @@ void binman_set_rom_offset(int rom_offset);
  */
 int binman_entry_find(const char *name, struct binman_entry *entry);
 
+/**
+ * binman_section_find_node() - Find a binman node
+ *
+ * @name: Name of node to look for
+ * @return Node that was found, ofnode_null() if not found
+ */
+ofnode binman_section_find_node(const char *name);
+
 /**
  * binman_init() - Set up the binman symbol information
  *
diff --git a/lib/binman.c b/lib/binman.c
index 79d01230dd..ba4d82963d 100644
--- a/lib/binman.c
+++ b/lib/binman.c
@@ -11,6 +11,7 @@
 #include <dm.h>
 #include <log.h>
 #include <malloc.h>
+#include <mapmem.h>
 
 /**
  * struct binman_info - Information needed by the binman library
@@ -54,6 +55,28 @@ int binman_entry_find(const char *name, struct binman_entry *entry)
 	return binman_entry_find_(binman->image, name, entry);
 }
 
+int binman_entry_map(ofnode parent, const char *name, void **bufp, int *sizep)
+{
+	struct binman_entry entry;
+	int ret;
+
+	if (binman->rom_offset == ROM_OFFSET_NONE)
+		return -EPERM;
+	ret = binman_entry_find_(parent, name, &entry);
+	if (ret)
+		return log_msg_ret("entry", ret);
+	if (sizep)
+		*sizep = entry.size;
+	*bufp = map_sysmem(entry.image_pos + binman->rom_offset, entry.size);
+
+	return 0;
+}
+
+ofnode binman_section_find_node(const char *name)
+{
+	return ofnode_find_subnode(binman->image, name);
+}
+
 void binman_set_rom_offset(int rom_offset)
 {
 	binman->rom_offset = rom_offset;
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 04/43] acpi: Allow creating the GNVS to fail

[Simon Glass]

In some cases an internal error may prevent this from working. Update the
function return value and report the error. At present the API for writing
tables does not easily support reporting errors, but once it is fully
updated to use a context pointer, this will be easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v1:
- Add linux/err.h header

 arch/x86/cpu/baytrail/acpi.c      |  4 +++-
 arch/x86/cpu/quark/acpi.c         |  4 +++-
 arch/x86/cpu/tangier/acpi.c       |  4 +++-
 arch/x86/include/asm/acpi_table.h | 10 +++++++++-
 arch/x86/lib/acpi_table.c         | 11 +++++++++--
 5 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index b17bc62a2d..07757b88a3 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -139,7 +139,7 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
 	header->checksum = table_compute_checksum(fadt, header->length);
 }
 
-void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 {
 	struct udevice *dev;
 	int ret;
@@ -159,6 +159,8 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 		gnvs->iuart_en = 1;
 	else
 		gnvs->iuart_en = 0;
+
+	return 0;
 }
 
 /*
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
index 26cda3b337..b0406a04e9 100644
--- a/arch/x86/cpu/quark/acpi.c
+++ b/arch/x86/cpu/quark/acpi.c
@@ -133,8 +133,10 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
 	header->checksum = table_compute_checksum(fadt, header->length);
 }
 
-void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 {
 	/* quark is a uni-processor */
 	gnvs->pcnt = 1;
+
+	return 0;
 }
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
index 4ec8fdd6f8..41bd177e09 100644
--- a/arch/x86/cpu/tangier/acpi.c
+++ b/arch/x86/cpu/tangier/acpi.c
@@ -107,7 +107,7 @@ u32 acpi_fill_csrt(u32 current)
 	return current;
 }
 
-void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 {
 	struct udevice *dev;
 	int ret;
@@ -122,4 +122,6 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 		if (ret > 0)
 			gnvs->pcnt = ret;
 	}
+
+	return 0;
 }
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 928475cef4..733085c178 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -35,7 +35,15 @@ int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
 			      u16 seg_nr, u8 start, u8 end);
 u32 acpi_fill_mcfg(u32 current);
 u32 acpi_fill_csrt(u32 current);
-void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
+
+/**
+ * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
+ *
+ * @gnvs: Table to fill in
+ * @return 0 if OK, -ve on error
+ */
+int acpi_create_gnvs(struct acpi_global_nvs *gnvs);
+
 ulong write_acpi_tables(ulong start);
 
 /**
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index eeacfe9b06..27869a0e5e 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -23,6 +23,7 @@
 #include <asm/tables.h>
 #include <asm/arch/global_nvs.h>
 #include <dm/acpi.h>
+#include <linux/err.h>
 
 /*
  * IASL compiles the dsdt entries and writes the hex values
@@ -443,8 +444,14 @@ ulong write_acpi_tables(ulong start_addr)
 	dsdt->checksum = 0;
 	dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
 
-	/* Fill in platform-specific global NVS variables */
-	acpi_create_gnvs(ctx->current);
+	/*
+	 * Fill in platform-specific global NVS variables. If this fails we
+	 * cannot return the error but this should only happen while debugging.
+	 */
+	addr = acpi_create_gnvs(ctx->current);
+	if (IS_ERR_VALUE(addr))
+		printf("Error: Gailed to create GNVS\n");
+
 	acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
 
 	debug("ACPI:    * FADT\n");
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 05/43] dtoc: Support ACPI paths in of-platdata

[Simon Glass]

The start of an ACPI path typically has backslashes in it. These are not
preserved during the translation from device tree to C code, since dtc
(correctly) uses the first backslash as an escape character, and dtoc
therefore leaves it out of the C string.

Fix this with special-case handling.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 tools/dtoc/dtb_platdata.py      | 4 +++-
 tools/dtoc/dtoc_test_simple.dts | 1 +
 tools/dtoc/test_dtoc.py         | 3 +++
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py
index ecfe0624d1..0f903f54e8 100644
--- a/tools/dtoc/dtb_platdata.py
+++ b/tools/dtoc/dtb_platdata.py
@@ -102,7 +102,9 @@ def get_value(ftype, value):
     elif ftype == fdt.TYPE_BYTE:
         return '%#x' % tools.ToByte(value[0])
     elif ftype == fdt.TYPE_STRING:
-        return '"%s"' % value
+        # Handle evil ACPI backslashes by adding another backslash before them.
+        # So "\\_SB.GPO0" in the device tree effectively stays like that in C
+        return '"%s"' % value.replace('\\', '\\\\')
     elif ftype == fdt.TYPE_BOOL:
         return 'true'
     elif ftype == fdt.TYPE_INT64:
diff --git a/tools/dtoc/dtoc_test_simple.dts b/tools/dtoc/dtoc_test_simple.dts
index 165680bd4b..11bfc4c47a 100644
--- a/tools/dtoc/dtoc_test_simple.dts
+++ b/tools/dtoc/dtoc_test_simple.dts
@@ -34,6 +34,7 @@
 		longbytearray = [09 0a 0b 0c];
 		stringval = "message2";
 		stringarray = "another", "multi-word", "message";
+		acpi-name =  "\\_SB.GPO0";
 	};
 
 	spl-test3 {
diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py
index 8498e8303c..86cb5a7c05 100755
--- a/tools/dtoc/test_dtoc.py
+++ b/tools/dtoc/test_dtoc.py
@@ -68,6 +68,7 @@ class TestDtoc(unittest.TestCase):
     @classmethod
     def setUpClass(cls):
         tools.PrepareOutputDir(None)
+        cls.maxDiff = None
 
     @classmethod
     def tearDownClass(cls):
@@ -179,6 +180,7 @@ struct dtd_sandbox_pmic_test {
 \tfdt64_t\t\treg[2];
 };
 struct dtd_sandbox_spl_test {
+\tconst char *	acpi_name;
 \tbool\t\tboolval;
 \tunsigned char\tbytearray[3];
 \tunsigned char\tbyteval;
@@ -216,6 +218,7 @@ U_BOOT_DEVICE(spl_test) = {
 };
 
 static const struct dtd_sandbox_spl_test dtv_spl_test2 = {
+\t.acpi_name\t\t= "\\\\_SB.GPO0",
 \t.bytearray\t\t= {0x1, 0x23, 0x34},
 \t.byteval\t\t= 0x8,
 \t.intarray\t\t= {0x5, 0x0, 0x0, 0x0},
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 06/43] dm: core: Add a way of overriding the ACPI device path

[Simon Glass]

Some devices such as GPIO need to override the normal path that would be
generated by driver model. Add a device-tree property for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 doc/device-tree-bindings/device.txt | 23 +++++++++++++++++++++++
 drivers/core/acpi.c                 | 19 +++++++++++++++++++
 include/dm/acpi.h                   | 13 +++++++++++++
 3 files changed, 55 insertions(+)

diff --git a/doc/device-tree-bindings/device.txt b/doc/device-tree-bindings/device.txt
index 7140339623..2a5736c598 100644
--- a/doc/device-tree-bindings/device.txt
+++ b/doc/device-tree-bindings/device.txt
@@ -17,6 +17,8 @@ the acpi,compatible property.
     System) Device Name)
  - acpi,hid : Contains the string to use as the HID (Hardware ID)
     identifier _HID
+ - acpi,path : Specifies the full ACPI path for a device. This overrides the
+    normal path built from the driver-model hierarchy
  - acpi,name : Provides the ACPI name for a device, which is a string consisting
    of four alphanumeric character (upper case)
  - acpi,uid : _UID value for device
@@ -47,3 +49,24 @@ pcie-a0 at 14,0 {
 		interrupts-extended = <&acpi_gpe 0x3c 0>;
 	};
 };
+
+p2sb: p2sb at d,0 {
+	u-boot,dm-pre-reloc;
+	reg = <0x02006810 0 0 0 0>;
+	compatible = "intel,apl-p2sb";
+	early-regs = <IOMAP_P2SB_BAR 0x100000>;
+	pci,no-autoconfig;
+
+	n {
+		compatible = "intel,apl-pinctrl";
+		u-boot,dm-pre-reloc;
+		intel,p2sb-port-id = <PID_GPIO_N>;
+		acpi,path = "\\_SB.GPO0";
+		gpio_n: gpio-n {
+			compatible = "intel,gpio";
+			u-boot,dm-pre-reloc;
+			gpio-controller;
+			#gpio-cells = <2>;
+			linux-name = "INT3452:00";
+		};
+	};
diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
index fd58c76087..ea304a3067 100644
--- a/drivers/core/acpi.c
+++ b/drivers/core/acpi.c
@@ -82,6 +82,25 @@ int acpi_get_name(const struct udevice *dev, char *out_name)
 	return 0;
 }
 
+int acpi_get_path(const struct udevice *dev, char *out_path, int maxlen)
+{
+	const char *path;
+	int ret;
+
+	path = dev_read_string(dev, "acpi,path");
+	if (path) {
+		if (strlen(path) >= maxlen)
+			return -E2BIG;
+		strcpy(out_path, path);
+		return 0;
+	}
+	ret = acpi_device_path(dev, out_path, maxlen);
+	if (ret)
+		return log_msg_ret("dev", ret);
+
+	return 0;
+}
+
 /**
  * acpi_add_item() - Add a new item to the list of data collected
  *
diff --git a/include/dm/acpi.h b/include/dm/acpi.h
index 28d9275ccc..b6308b9fa6 100644
--- a/include/dm/acpi.h
+++ b/include/dm/acpi.h
@@ -180,6 +180,19 @@ int acpi_inject_dsdt(struct acpi_ctx *ctx);
  */
 void acpi_dump_items(enum acpi_dump_option option);
 
+/**
+ * acpi_get_path() - Get the full ACPI path for a device
+ *
+ * This checks for any override in the device tree and calls acpi_device_path()
+ * if not
+ *
+ * @dev: Device to check
+ * @out_path: Buffer to place the path in (should be ACPI_PATH_MAX long)
+ * @maxlen: Size of buffer (typically ACPI_PATH_MAX)
+ * @return 0 if OK, -ve on error
+ */
+int acpi_get_path(const struct udevice *dev, char *out_path, int maxlen);
+
 #endif /* __ACPI__ */
 
 #endif
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Simon Glass]

The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.

Add core support for this, based on a structure which is built up through
calls to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/core/acpi.c | 15 +++++++++++++++
 include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
index ea304a3067..a5053fec6f 100644
--- a/drivers/core/acpi.c
+++ b/drivers/core/acpi.c
@@ -31,6 +31,7 @@ enum method_t {
 	METHOD_WRITE_TABLES,
 	METHOD_FILL_SSDT,
 	METHOD_INJECT_DSDT,
+	METHOD_SETUP_NHLT,
 };
 
 /* Prototype for all methods */
@@ -239,6 +240,8 @@ acpi_method acpi_get_method(struct udevice *dev, enum method_t method)
 			return aops->fill_ssdt;
 		case METHOD_INJECT_DSDT:
 			return aops->inject_dsdt;
+		case METHOD_SETUP_NHLT:
+			return aops->setup_nhlt;
 		}
 	}
 
@@ -325,3 +328,15 @@ int acpi_write_dev_tables(struct acpi_ctx *ctx)
 
 	return ret;
 }
+
+int acpi_setup_nhlt(struct acpi_ctx *ctx, struct nhlt *nhlt)
+{
+	int ret;
+
+	log_debug("Setup NHLT\n");
+	ctx->nhlt = nhlt;
+	ret = acpi_recurse_method(ctx, dm_root(), METHOD_SETUP_NHLT, TYPE_NONE);
+	log_debug("Setup finished, err=%d\n", ret);
+
+	return ret;
+}
diff --git a/include/dm/acpi.h b/include/dm/acpi.h
index b6308b9fa6..a7f8e10ee2 100644
--- a/include/dm/acpi.h
+++ b/include/dm/acpi.h
@@ -27,6 +27,8 @@
 
 #if !defined(__ACPI__)
 
+struct nhlt;
+
 /** enum acpi_dump_option - selects what ACPI information to dump */
 enum acpi_dump_option {
 	ACPI_DUMP_LIST,		/* Just the list of items */
@@ -44,6 +46,9 @@ enum acpi_dump_option {
  *	adding a new table. The RSDP holds pointers to the RSDT and XSDT.
  * @rsdt: Pointer to the Root System Description Table
  * @xsdt: Pointer to the Extended System Description Table
+ * @nhlt: Intel Non-High-Definition-Audio Link Table (NHLT) pointer, used to
+ *	build up information that audio codecs need to provide in the NHLT ACPI
+ *	table
  * @len_stack: Stack of 'length' words to fix up later
  * @ltop: Points to current top of stack (0 = empty)
  */
@@ -53,6 +58,7 @@ struct acpi_ctx {
 	struct acpi_rsdp *rsdp;
 	struct acpi_rsdt *rsdt;
 	struct acpi_xsdt *xsdt;
+	struct nhlt *nhlt;
 	char *len_stack[ACPIGEN_LENSTACK_SIZE];
 	int ltop;
 };
@@ -106,6 +112,15 @@ struct acpi_ops {
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*inject_dsdt)(const struct udevice *dev, struct acpi_ctx *ctx);
+
+	/**
+	 * setup_nhlt() - Set up audio information for this device
+	 *
+	 * The method can add information to ctx->nhlt if it likes
+	 *
+	 * @return 0 if OK, -ENODATA if nothing to add, -ve on error
+	 */
+	int (*setup_nhlt)(const struct udevice *dev, struct acpi_ctx *ctx);
 };
 
 #define device_get_acpi_ops(dev)	((dev)->driver->acpi_ops)
@@ -170,6 +185,17 @@ int acpi_fill_ssdt(struct acpi_ctx *ctx);
  */
 int acpi_inject_dsdt(struct acpi_ctx *ctx);
 
+/**
+ * acpi_setup_nhlt() - Set up audio information
+ *
+ * This is called to set up the nhlt information for all devices.
+ *
+ * @ctx: ACPI context to use
+ * @nhlt: Pointer to nhlt information to add to
+ * @return 0 if OK, -ve on error
+ */
+int acpi_setup_nhlt(struct acpi_ctx *ctx, struct nhlt *nhlt);
+
 /**
  * acpi_dump_items() - Dump out the collected ACPI items
  *
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 08/43] acpi: Export functions to write sized values

[Simon Glass]

At present only acpigen_write_integer() is exported for use by other code.
But in some cases it is useful to call the specific function depending on
the size of the value.

Export these functions and add a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/acpi/acpigen.h | 46 ++++++++++++++++++++++++++++++++++++++++++
 test/dm/acpigen.c      | 45 ++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index d68dca5dde..7c117c1cf6 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -169,6 +169,52 @@ void acpigen_pop_len(struct acpi_ctx *ctx);
  */
 char *acpigen_write_package(struct acpi_ctx *ctx, int nr_el);
 
+/**
+ * acpigen_write_byte() - Write a byte
+ *
+ * @ctx: ACPI context pointer
+ * @data: Value to write
+ */
+void acpigen_write_byte(struct acpi_ctx *ctx, unsigned int data);
+
+/**
+ * acpigen_write_word() - Write a word
+ *
+ * @ctx: ACPI context pointer
+ * @data: Value to write
+ */
+void acpigen_write_word(struct acpi_ctx *ctx, unsigned int data);
+
+/**
+ * acpigen_write_dword() - Write a dword
+ *
+ * @ctx: ACPI context pointer
+ * @data: Value to write
+ */
+void acpigen_write_dword(struct acpi_ctx *ctx, unsigned int data);
+
+/**
+ * acpigen_write_qword() - Write a qword
+ *
+ * @ctx: ACPI context pointer
+ * @data: Value to write
+ */
+void acpigen_write_qword(struct acpi_ctx *ctx, u64 data);
+
+/**
+ * acpigen_write_zero() - Write zero
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_zero(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_one() - Write one
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_one(struct acpi_ctx *ctx);
+
 /**
  * acpigen_write_integer() - Write an integer
  *
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index ea2033a27c..0322dd4f60 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -861,5 +861,48 @@ static int dm_test_acpi_power_seq(struct unit_test_state *uts)
 
 	return 0;
 }
-
 DM_TEST(dm_test_acpi_power_seq, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test writing values */
+static int dm_test_acpi_write_values(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+	ptr = acpigen_get_current(ctx);
+
+	acpigen_write_zero(ctx);
+	acpigen_write_one(ctx);
+	acpigen_write_byte(ctx, TEST_INT8);
+	acpigen_write_word(ctx, TEST_INT16);
+	acpigen_write_dword(ctx, TEST_INT32);
+	acpigen_write_qword(ctx, TEST_INT64);
+
+	ut_asserteq(ZERO_OP, *ptr++);
+
+	ut_asserteq(ONE_OP, *ptr++);
+
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(TEST_INT8, *ptr++);
+
+	ut_asserteq(WORD_PREFIX, *ptr++);
+	ut_asserteq(TEST_INT16, get_unaligned((u16 *)ptr));
+	ptr += 2;
+
+	ut_asserteq(DWORD_PREFIX, *ptr++);
+	ut_asserteq(TEST_INT32, get_unaligned((u32 *)ptr));
+	ptr += 4;
+
+	ut_asserteq(QWORD_PREFIX, *ptr++);
+	ut_asserteq_64(TEST_INT64, get_unaligned((u64 *)ptr));
+	ptr += 8;
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_values, 0);
+
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 09/43] acpi: Support generation of a scope

[Simon Glass]

Add a function to write a scope to the generated ACPI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/acpi/acpigen.h | 10 ++++++++++
 lib/acpi/acpigen.c     |  7 +++++++
 test/dm/acpi.c         |  3 +--
 test/dm/acpigen.c      | 33 ++++++++++++++++++++++++++++++++-
 4 files changed, 50 insertions(+), 3 deletions(-)

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 7c117c1cf6..af66c9828f 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -31,6 +31,7 @@ enum {
 	DWORD_PREFIX		= 0x0c,
 	STRING_PREFIX		= 0x0d,
 	QWORD_PREFIX		= 0x0e,
+	SCOPE_OP		= 0x10,
 	BUFFER_OP		= 0x11,
 	PACKAGE_OP		= 0x12,
 	METHOD_OP		= 0x14,
@@ -258,6 +259,14 @@ void acpigen_emit_namestring(struct acpi_ctx *ctx, const char *namepath);
  */
 void acpigen_write_name(struct acpi_ctx *ctx, const char *namepath);
 
+/**
+ * acpigen_write_scope() - Write a scope
+ *
+ * @ctx: ACPI context pointer
+ * @name: Scope to write (e.g. "\\_SB.ABCD")
+ */
+void acpigen_write_scope(struct acpi_ctx *ctx, const char *name);
+
 /**
  * acpigen_write_uuid() - Write a UUID
  *
@@ -396,6 +405,7 @@ void acpigen_write_power_res(struct acpi_ctx *ctx, const char *name, uint level,
  */
 int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32 tx_state_val,
 			       const char *dw0_name, struct acpi_gpio *gpio,
+
 			       bool enable);
 
 #endif
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index e0af36f775..77d6434806 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -257,6 +257,13 @@ void acpigen_write_name(struct acpi_ctx *ctx, const char *namepath)
 	acpigen_emit_namestring(ctx, namepath);
 }
 
+void acpigen_write_scope(struct acpi_ctx *ctx, const char *name)
+{
+	acpigen_emit_byte(ctx, SCOPE_OP);
+	acpigen_write_len_f(ctx);
+	acpigen_emit_namestring(ctx, name);
+}
+
 static void acpigen_write_method_(struct acpi_ctx *ctx, const char *name,
 				  uint flags)
 {
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 7768f9514c..b94c4ba4d1 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -20,9 +20,8 @@
 #include <dm/acpi.h>
 #include <dm/test.h>
 #include <test/ut.h>
+#include "acpi.h"
 
-#define ACPI_TEST_DEV_NAME	"ABCD"
-#define ACPI_TEST_CHILD_NAME	"EFGH"
 #define BUF_SIZE		4096
 
 /**
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 0322dd4f60..93dfa301d6 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -18,6 +18,7 @@
 #include <dm/test.h>
 #include <dm/uclass-internal.h>
 #include <test/ut.h>
+#include "acpi.h"
 
 #define TEST_STRING	"frogmore"
 #define TEST_STRING2	"ranch"
@@ -359,7 +360,7 @@ DM_TEST(dm_test_acpi_spi, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
  */
 static int get_length(u8 *ptr)
 {
-	if (!(*ptr & 0x80))
+	if (!(*ptr & ACPI_PKG_LEN_3_BYTES))
 		return -EINVAL;
 
 	return (*ptr & 0xf) | ptr[1] << 4 | ptr[2] << 12;
@@ -906,3 +907,33 @@ static int dm_test_acpi_write_values(struct unit_test_state *uts)
 }
 DM_TEST(dm_test_acpi_write_values, 0);
 
+/* Test writing a scope */
+static int dm_test_acpi_scope(struct unit_test_state *uts)
+{
+	char buf[ACPI_PATH_MAX];
+	struct acpi_ctx *ctx;
+	struct udevice *dev;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+	ptr = acpigen_get_current(ctx);
+
+	ut_assertok(uclass_first_device_err(UCLASS_TEST_ACPI, &dev));
+	ut_assertok(acpi_device_path(dev, buf, sizeof(buf)));
+	acpigen_write_scope(ctx, buf);
+	acpigen_pop_len(ctx);
+
+	ut_asserteq(SCOPE_OP, *ptr++);
+	ut_asserteq(13, get_length(ptr));
+	ptr += 3;
+	ut_asserteq(ROOT_PREFIX, *ptr++);
+	ut_asserteq(DUAL_NAME_PREFIX, *ptr++);
+	ut_asserteq_strn("_SB_" ACPI_TEST_DEV_NAME, (char *)ptr);
+	ptr += 8;
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_scope, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 10/43] acpi: Support generation of a generic register

[Simon Glass]

Allow writing out a generic register.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/acpi/acpi_device.h |  1 +
 include/acpi/acpigen.h     | 28 +++++++++++++++
 lib/acpi/acpigen.c         | 71 ++++++++++++++++++++++++++++++++++++++
 test/dm/acpigen.c          | 46 ++++++++++++++++++++++++
 4 files changed, 146 insertions(+)

diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index d076b452b5..474ac8955f 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h
@@ -20,6 +20,7 @@ struct udevice;
 
 /* ACPI descriptor values for common descriptors: SERIAL_BUS means I2C */
 #define ACPI_DESCRIPTOR_LARGE		BIT(7)
+#define ACPI_DESCRIPTOR_REGISTER	(ACPI_DESCRIPTOR_LARGE | 2)
 #define ACPI_DESCRIPTOR_INTERRUPT	(ACPI_DESCRIPTOR_LARGE | 9)
 #define ACPI_DESCRIPTOR_GPIO		(ACPI_DESCRIPTOR_LARGE | 12)
 #define ACPI_DESCRIPTOR_SERIAL_BUS	(ACPI_DESCRIPTOR_LARGE | 14)
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index af66c9828f..4361a28a08 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -13,6 +13,7 @@
 #include <linux/types.h>
 
 struct acpi_ctx;
+struct acpi_gen_regaddr;
 struct acpi_gpio;
 
 /* Top 4 bits of the value used to indicate a three-byte length value */
@@ -21,6 +22,8 @@ struct acpi_gpio;
 #define ACPI_METHOD_NARGS_MASK		0x7
 #define ACPI_METHOD_SERIALIZED_MASK	BIT(3)
 
+#define ACPI_END_TAG			0x79
+
 /* ACPI Op/Prefix codes */
 enum {
 	ZERO_OP			= 0x00,
@@ -315,6 +318,31 @@ void acpigen_write_method_serialized(struct acpi_ctx *ctx, const char *name,
  */
 void acpigen_write_sta(struct acpi_ctx *ctx, uint status);
 
+/**
+ * acpigen_write_resourcetemplate_header() - Write a ResourceTemplate header
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_resourcetemplate_header(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_resourcetemplate_footer() - Write a ResourceTemplate footer
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_resourcetemplate_footer(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_register_resource() - Write a register resource
+ *
+ * This writes a header, the address information and a footer
+ *
+ * @ctx: ACPI context pointer
+ * @addr: Address to write
+ */
+void acpigen_write_register_resource(struct acpi_ctx *ctx,
+				     const struct acpi_gen_regaddr *addr);
+
 /**
  * acpigen_write_sleep() - Write a sleep operation
  *
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index 77d6434806..6f5972f1f7 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -14,6 +14,7 @@
 #include <uuid.h>
 #include <acpi/acpigen.h>
 #include <acpi/acpi_device.h>
+#include <acpi/acpi_table.h>
 #include <dm/acpi.h>
 
 u8 *acpigen_get_current(struct acpi_ctx *ctx)
@@ -296,6 +297,76 @@ void acpigen_write_sta(struct acpi_ctx *ctx, uint status)
 	acpigen_pop_len(ctx);
 }
 
+static void acpigen_write_register(struct acpi_ctx *ctx,
+				   const struct acpi_gen_regaddr *addr)
+{
+	/* See ACPI v6.3 section 6.4.3.7: Generic Register Descriptor */
+	acpigen_emit_byte(ctx, ACPI_DESCRIPTOR_REGISTER);
+	acpigen_emit_byte(ctx, 0x0c);		/* Register Length 7:0 */
+	acpigen_emit_byte(ctx, 0x00);		/* Register Length 15:8 */
+	acpigen_emit_byte(ctx, addr->space_id);
+	acpigen_emit_byte(ctx, addr->bit_width);
+	acpigen_emit_byte(ctx, addr->bit_offset);
+	acpigen_emit_byte(ctx, addr->access_size);
+	acpigen_emit_dword(ctx, addr->addrl);
+	acpigen_emit_dword(ctx, addr->addrh);
+}
+
+void acpigen_write_resourcetemplate_header(struct acpi_ctx *ctx)
+{
+	/*
+	 * A ResourceTemplate() is a Buffer() with a
+	 * (Byte|Word|DWord) containing the length, followed by one or more
+	 * resource items, terminated by the end tag.
+	 * (small item 0xf, len 1)
+	 */
+	acpigen_emit_byte(ctx, BUFFER_OP);
+	acpigen_write_len_f(ctx);
+	acpigen_emit_byte(ctx, WORD_PREFIX);
+	ctx->len_stack[ctx->ltop++] = ctx->current;
+
+	/*
+	 * Add two dummy bytes for the ACPI word (keep aligned with the
+	 * calculation in acpigen_write_resourcetemplate_footer() below)
+	 */
+	acpigen_emit_byte(ctx, 0x00);
+	acpigen_emit_byte(ctx, 0x00);
+}
+
+void acpigen_write_resourcetemplate_footer(struct acpi_ctx *ctx)
+{
+	char *p = ctx->len_stack[--ctx->ltop];
+	int len;
+	/*
+	 * See ACPI v6.3 section 6.4.2.9: End Tag
+	 * 0x79 <checksum>
+	 * 0x00 is treated as a good checksum according to the spec
+	 * and is what iasl generates.
+	 */
+	acpigen_emit_byte(ctx, ACPI_END_TAG);
+	acpigen_emit_byte(ctx, 0x00);
+
+	/*
+	 * Start counting past the 2-bytes length added in
+	 * acpigen_write_resourcetemplate_header() above
+	 */
+	len = (char *)ctx->current - (p + 2);
+
+	/* patch len word */
+	p[0] = len & 0xff;
+	p[1] = (len >> 8) & 0xff;
+
+	acpigen_pop_len(ctx);
+}
+
+void acpigen_write_register_resource(struct acpi_ctx *ctx,
+				     const struct acpi_gen_regaddr *addr)
+{
+	acpigen_write_resourcetemplate_header(ctx);
+	acpigen_write_register(ctx, addr);
+	acpigen_write_resourcetemplate_footer(ctx);
+}
+
 /*
  * ToUUID(uuid)
  *
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 93dfa301d6..80697300e7 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -12,6 +12,7 @@
 #include <malloc.h>
 #include <acpi/acpigen.h>
 #include <acpi/acpi_device.h>
+#include <acpi/acpi_table.h>
 #include <asm/gpio.h>
 #include <asm/unaligned.h>
 #include <dm/acpi.h>
@@ -937,3 +938,48 @@ static int dm_test_acpi_scope(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_acpi_scope, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test writing a resource template */
+static int dm_test_acpi_resource_template(struct unit_test_state *uts)
+{
+	struct acpi_gen_regaddr addr;
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+	ptr = acpigen_get_current(ctx);
+
+	addr.space_id = ACPI_ADDRESS_SPACE_EC;
+	addr.bit_width = 32;
+	addr.bit_offset = 8;
+	addr.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	addr.addrl = TEST_INT64 & 0xffffffff;
+	addr.addrh = TEST_INT64 >> 32;
+	acpigen_write_register_resource(ctx, &addr);
+
+	ut_asserteq(BUFFER_OP, *ptr++);
+	ut_asserteq(0x17, get_length(ptr));
+	ptr += 3;
+	ut_asserteq(WORD_PREFIX, *ptr++);
+	ut_asserteq(0x11, get_unaligned((u16 *)ptr));
+	ptr += 2;
+	ut_asserteq(ACPI_DESCRIPTOR_REGISTER, *ptr++);
+	ut_asserteq(0xc, *ptr++);
+	ut_asserteq(0, *ptr++);
+	ut_asserteq(ACPI_ADDRESS_SPACE_EC, *ptr++);
+	ut_asserteq(32, *ptr++);
+	ut_asserteq(8, *ptr++);
+	ut_asserteq(ACPI_ACCESS_SIZE_DWORD_ACCESS, *ptr++);
+	ut_asserteq(TEST_INT64 & 0xffffffff, get_unaligned((u32 *)ptr));
+	ptr += 4;
+	ut_asserteq(TEST_INT64 >> 32, get_unaligned((u32 *)ptr));
+	ptr += 4;
+	ut_asserteq(ACPI_END_TAG, *ptr++);
+	ut_asserteq(0x00, *ptr++);
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_resource_template, 0);
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 11/43] acpi: mmc: Generate ACPI info for the PCI SD Card

[Simon Glass]

Write required information into the SSDT to describe the SD card
card-detect pin. Since the required GPIO properties are not present in
the device-tree binding, set them manually for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v1:
- Capitalise ACPI_OPS_PTR

 configs/sandbox_defconfig |  2 +
 drivers/mmc/pci_mmc.c     | 78 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 79 insertions(+), 1 deletion(-)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 982075c568..cb6b4b0ee7 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -143,7 +143,9 @@ CONFIG_P2SB=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
 CONFIG_I2C_EEPROM=y
+CONFIG_MMC_PCI=y
 CONFIG_MMC_SANDBOX=y
+CONFIG_MMC_SDHCI=y
 CONFIG_MTD=y
 CONFIG_SPI_FLASH_SANDBOX=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 404264a697..0c45e1b893 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -7,10 +7,15 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
+#include <log.h>
 #include <malloc.h>
 #include <mapmem.h>
 #include <sdhci.h>
-#include <asm/pci.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpi_dp.h>
+#include <asm-generic/gpio.h>
+#include <dm/acpi.h>
 
 struct pci_mmc_plat {
 	struct mmc_config cfg;
@@ -20,6 +25,7 @@ struct pci_mmc_plat {
 struct pci_mmc_priv {
 	struct sdhci_host host;
 	void *base;
+	struct gpio_desc cd_gpio;
 };
 
 static int pci_mmc_probe(struct udevice *dev)
@@ -44,6 +50,15 @@ static int pci_mmc_probe(struct udevice *dev)
 	return sdhci_probe(dev);
 }
 
+static int pci_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+	struct pci_mmc_priv *priv = dev_get_priv(dev);
+
+	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+
+	return 0;
+}
+
 static int pci_mmc_bind(struct udevice *dev)
 {
 	struct pci_mmc_plat *plat = dev_get_platdata(dev);
@@ -51,14 +66,75 @@ static int pci_mmc_bind(struct udevice *dev)
 	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 }
 
+static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev,
+				  struct acpi_ctx *ctx)
+{
+	struct pci_mmc_priv *priv = dev_get_priv(dev);
+	char path[ACPI_PATH_MAX];
+	struct acpi_gpio gpio;
+	struct acpi_dp *dp;
+	int ret;
+
+	if (!dev_of_valid(dev))
+		return 0;
+
+	ret = gpio_get_acpi(&priv->cd_gpio, &gpio);
+	if (ret)
+		return log_msg_ret("gpio", ret);
+	gpio.type = ACPI_GPIO_TYPE_INTERRUPT;
+	gpio.pull = ACPI_GPIO_PULL_NONE;
+	gpio.irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
+	gpio.irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
+	gpio.irq.shared = ACPI_IRQ_SHARED;
+	gpio.irq.wake = ACPI_IRQ_WAKE;
+	gpio.interrupt_debounce_timeout = 10000; /* 100ms */
+
+	/* Use device path as the Scope for the SSDT */
+	ret = acpi_device_path(dev, path, sizeof(path));
+	if (ret)
+		return log_msg_ret("path", ret);
+	acpigen_write_scope(ctx, path);
+	acpigen_write_name(ctx, "_CRS");
+
+	/* Write GpioInt() as default (if set) or custom from devicetree */
+	acpigen_write_resourcetemplate_header(ctx);
+	acpi_device_write_gpio(ctx, &gpio);
+	acpigen_write_resourcetemplate_footer(ctx);
+
+	/* Bind the cd-gpio name to the GpioInt() resource */
+	dp = acpi_dp_new_table("_DSD");
+	if (!dp)
+		return -ENOMEM;
+	acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1);
+	ret = acpi_dp_write(ctx, dp);
+	if (ret)
+		return log_msg_ret("cd", ret);
+
+	acpigen_pop_len(ctx);
+
+	return 0;
+}
+
+struct acpi_ops pci_mmc_acpi_ops = {
+	.fill_ssdt	= pci_mmc_acpi_fill_ssdt,
+};
+
+static const struct udevice_id pci_mmc_match[] = {
+	{ .compatible = "intel,apl-sd" },
+	{ }
+};
+
 U_BOOT_DRIVER(pci_mmc) = {
 	.name	= "pci_mmc",
 	.id	= UCLASS_MMC,
+	.of_match = pci_mmc_match,
 	.bind	= pci_mmc_bind,
+	.ofdata_to_platdata	= pci_mmc_ofdata_to_platdata,
 	.probe	= pci_mmc_probe,
 	.ops	= &sdhci_ops,
 	.priv_auto_alloc_size = sizeof(struct pci_mmc_priv),
 	.platdata_auto_alloc_size = sizeof(struct pci_mmc_plat),
+	ACPI_OPS_PTR(&pci_mmc_acpi_ops)
 };
 
 static struct pci_device_id mmc_supported[] = {
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 12/43] x86: Add bindings for NHLT

[Simon Glass]

Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table
(NHLT).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/dt-bindings/sound/nhlt.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 include/dt-bindings/sound/nhlt.h

diff --git a/include/dt-bindings/sound/nhlt.h b/include/dt-bindings/sound/nhlt.h
new file mode 100644
index 0000000000..c33f874966
--- /dev/null
+++ b/include/dt-bindings/sound/nhlt.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _DT_BINDINGS_SOUND_NHLT_H
+#define _DT_BINDINGS_SOUND_NHLT_H
+
+#define NHLT_VID	0x8086
+#define NHLT_DID_DMIC	0xae20
+#define NHLT_DID_BT	0xae30
+#define NHLT_DID_SSP	0xae34
+
+/* Hardware links available to use for codecs */
+#define AUDIO_LINK_SSP0		0
+#define AUDIO_LINK_SSP1		1
+#define AUDIO_LINK_SSP2		2
+#define AUDIO_LINK_SSP3		3
+#define AUDIO_LINK_SSP4		4
+#define AUDIO_LINK_SSP5		5
+#define AUDIO_LINK_DMIC		6
+
+#endif /* _DT_BINDINGS_SOUND_NHLT_H */
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 13/43] acpi: Support generation of a device

[Simon Glass]

Allow writing an ACPI device to the generated ACPI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/acpi/acpigen.h |  9 +++++++++
 lib/acpi/acpigen.c     |  7 +++++++
 test/dm/acpigen.c      | 27 +++++++++++++++++++++++++++
 3 files changed, 43 insertions(+)

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 4361a28a08..19f84dc867 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -56,6 +56,7 @@ enum {
 	AND_OP			= 0x7b,
 	OR_OP			= 0x7d,
 	NOT_OP			= 0x80,
+	DEVICE_OP		= 0x82,
 	POWER_RES_OP		= 0x84,
 	RETURN_OP		= 0xa4,
 };
@@ -310,6 +311,14 @@ void acpigen_write_method(struct acpi_ctx *ctx, const char *name, int nargs);
 void acpigen_write_method_serialized(struct acpi_ctx *ctx, const char *name,
 				     int nargs);
 
+/**
+ * acpigen_write_device() - Write an ACPI device
+ *
+ * @ctx: ACPI context pointer
+ * @name: Device name to write
+ */
+void acpigen_write_device(struct acpi_ctx *ctx, const char *name);
+
 /**
  * acpigen_write_sta() - Write a _STA method
  *
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index 6f5972f1f7..5fe1f59f82 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -288,6 +288,13 @@ void acpigen_write_method_serialized(struct acpi_ctx *ctx, const char *name,
 			      ACPI_METHOD_SERIALIZED_MASK);
 }
 
+void acpigen_write_device(struct acpi_ctx *ctx, const char *name)
+{
+	acpigen_emit_ext_op(ctx, DEVICE_OP);
+	acpigen_write_len_f(ctx);
+	acpigen_emit_namestring(ctx, name);
+}
+
 void acpigen_write_sta(struct acpi_ctx *ctx, uint status)
 {
 	/* Method (_STA, 0, NotSerialized) { Return (status) } */
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 80697300e7..5cd7fb5657 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -983,3 +983,30 @@ static int dm_test_acpi_resource_template(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_acpi_resource_template, 0);
+
+/* Test writing a device */
+static int dm_test_acpi_device(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+	ptr = acpigen_get_current(ctx);
+
+	acpigen_write_device(ctx, "\\_SB." ACPI_TEST_DEV_NAME);
+	acpigen_pop_len(ctx);
+
+	ut_asserteq(EXT_OP_PREFIX, *ptr++);
+	ut_asserteq(DEVICE_OP, *ptr++);
+	ut_asserteq(0xd, get_length(ptr));
+	ptr += 3;
+	ut_asserteq(ROOT_PREFIX, *ptr++);
+	ut_asserteq(DUAL_NAME_PREFIX, *ptr++);
+	ptr += 8;
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_device, 0);
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 14/43] acpi: Support writing named values

[Simon Glass]

Allow writing named integers and strings to the generated ACPI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/acpi/acpigen.h | 72 ++++++++++++++++++++++++++++++++++++++
 lib/acpi/acpigen.c     | 49 ++++++++++++++++++++++++++
 test/dm/acpigen.c      | 78 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 199 insertions(+)

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 19f84dc867..01620fd36b 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -231,6 +231,78 @@ void acpigen_write_one(struct acpi_ctx *ctx);
  */
 void acpigen_write_integer(struct acpi_ctx *ctx, u64 data);
 
+/**
+ * acpigen_write_name_zero() - Write a named zero value
+ *
+ * @ctx: ACPI context pointer
+ * @name: Name of the value
+ */
+void acpigen_write_name_zero(struct acpi_ctx *ctx, const char *name);
+
+/**
+ * acpigen_write_name_one() - Write a named one value
+ *
+ * @ctx: ACPI context pointer
+ * @name: Name of the value
+ */
+void acpigen_write_name_one(struct acpi_ctx *ctx, const char *name);
+
+/**
+ * acpigen_write_name_byte() - Write a named byte value
+ *
+ * @ctx: ACPI context pointer
+ * @name: Name of the value
+ * @val: Value to write
+ */
+void acpigen_write_name_byte(struct acpi_ctx *ctx, const char *name, uint val);
+
+/**
+ * acpigen_write_name_word() - Write a named word value
+ *
+ * @ctx: ACPI context pointer
+ * @name: Name of the value
+ * @val: Value to write
+ */
+void acpigen_write_name_word(struct acpi_ctx *ctx, const char *name, uint val);
+
+/**
+ * acpigen_write_name_dword() - Write a named dword value
+ *
+ * @ctx: ACPI context pointer
+ * @name: Name of the value
+ * @val: Value to write
+ */
+void acpigen_write_name_dword(struct acpi_ctx *ctx, const char *name, uint val);
+
+/**
+ * acpigen_write_name_qword() - Write a named qword value
+ *
+ * @ctx: ACPI context pointer
+ * @name: Name of the value
+ * @val: Value to write
+ */
+void acpigen_write_name_qword(struct acpi_ctx *ctx, const char *name, u64 val);
+
+/**
+ * acpigen_write_name_integer() - Write a named integer value
+ *
+ * @ctx: ACPI context pointer
+ * @name: Name of the value
+ * @val: Value to write
+ */
+void acpigen_write_name_integer(struct acpi_ctx *ctx, const char *name,
+				u64 val);
+
+/**
+ * acpigen_write_name_string() - Write a named string value
+ *
+ * @ctx: ACPI context pointer
+ * @name: Name of the value
+ * @string: String to write
+ */
+void acpigen_write_name_string(struct acpi_ctx *ctx, const char *name,
+			       const char *string);
+
 /**
  * acpigen_write_string() - Write a string
  *
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index 5fe1f59f82..86af88d1bc 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -142,6 +142,55 @@ void acpigen_write_integer(struct acpi_ctx *ctx, u64 data)
 		acpigen_write_qword(ctx, data);
 }
 
+void acpigen_write_name_zero(struct acpi_ctx *ctx, const char *name)
+{
+	acpigen_write_name(ctx, name);
+	acpigen_write_zero(ctx);
+}
+
+void acpigen_write_name_one(struct acpi_ctx *ctx, const char *name)
+{
+	acpigen_write_name(ctx, name);
+	acpigen_write_one(ctx);
+}
+
+void acpigen_write_name_byte(struct acpi_ctx *ctx, const char *name, uint val)
+{
+	acpigen_write_name(ctx, name);
+	acpigen_write_byte(ctx, val);
+}
+
+void acpigen_write_name_word(struct acpi_ctx *ctx, const char *name, uint val)
+{
+	acpigen_write_name(ctx, name);
+	acpigen_write_word(ctx, val);
+}
+
+void acpigen_write_name_dword(struct acpi_ctx *ctx, const char *name, uint val)
+{
+	acpigen_write_name(ctx, name);
+	acpigen_write_dword(ctx, val);
+}
+
+void acpigen_write_name_qword(struct acpi_ctx *ctx, const char *name, u64 val)
+{
+	acpigen_write_name(ctx, name);
+	acpigen_write_qword(ctx, val);
+}
+
+void acpigen_write_name_integer(struct acpi_ctx *ctx, const char *name, u64 val)
+{
+	acpigen_write_name(ctx, name);
+	acpigen_write_integer(ctx, val);
+}
+
+void acpigen_write_name_string(struct acpi_ctx *ctx, const char *name,
+			       const char *string)
+{
+	acpigen_write_name(ctx, name);
+	acpigen_write_string(ctx, string);
+}
+
 void acpigen_emit_stream(struct acpi_ctx *ctx, const char *data, int size)
 {
 	int i;
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 5cd7fb5657..4fcd155b93 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -1010,3 +1010,81 @@ static int dm_test_acpi_device(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_acpi_device, 0);
+
+/* Test writing named values */
+static int dm_test_acpi_write_name(struct unit_test_state *uts)
+{
+	const char *name = "\\_SB." ACPI_TEST_DEV_NAME;
+	struct acpi_ctx *ctx;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+	ptr = acpigen_get_current(ctx);
+
+	acpigen_write_name_zero(ctx, name);
+	acpigen_write_name_one(ctx, name);
+	acpigen_write_name_byte(ctx, name, TEST_INT8);
+	acpigen_write_name_word(ctx, name, TEST_INT16);
+	acpigen_write_name_dword(ctx, name, TEST_INT32);
+	acpigen_write_name_qword(ctx, name, TEST_INT64);
+	acpigen_write_name_integer(ctx, name, TEST_INT64 + 1);
+	acpigen_write_name_string(ctx, name, "baldrick");
+	acpigen_write_name_string(ctx, name, NULL);
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ut_asserteq_strn("\\._SB_ABCD", (char *)ptr);
+	ptr += 10;
+	ut_asserteq(ZERO_OP, *ptr++);
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ptr += 10;
+	ut_asserteq(ONE_OP, *ptr++);
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ptr += 10;
+	ut_asserteq(BYTE_PREFIX, *ptr++);
+	ut_asserteq(TEST_INT8, *ptr++);
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ptr += 10;
+	ut_asserteq(WORD_PREFIX, *ptr++);
+	ut_asserteq(TEST_INT16, get_unaligned((u16 *)ptr));
+	ptr += 2;
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ptr += 10;
+	ut_asserteq(DWORD_PREFIX, *ptr++);
+	ut_asserteq(TEST_INT32, get_unaligned((u32 *)ptr));
+	ptr += 4;
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ptr += 10;
+	ut_asserteq(QWORD_PREFIX, *ptr++);
+	ut_asserteq_64(TEST_INT64, get_unaligned((u64 *)ptr));
+	ptr += 8;
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ptr += 10;
+	ut_asserteq(QWORD_PREFIX, *ptr++);
+	ut_asserteq_64(TEST_INT64 + 1, get_unaligned((u64 *)ptr));
+	ptr += 8;
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ptr += 10;
+	ut_asserteq(STRING_PREFIX, *ptr++);
+	ut_asserteq_str("baldrick", (char *)ptr)
+	ptr += 9;
+
+	ut_asserteq(NAME_OP, *ptr++);
+	ptr += 10;
+	ut_asserteq(STRING_PREFIX, *ptr++);
+	ut_asserteq('\0', *ptr++);
+
+	ut_asserteq_ptr(ptr, ctx->current);
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_write_name, 0);
+
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 15/43] sound: Add an ACPI driver for Dialog Semicondutor da7219

[Simon Glass]

This chip is used on coral and we need to generate ACPI tables for sound
to make it work. Add a driver that does just this (i.e. at present does
not actually support playing sound).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v1:
- Use acpi,ddn instead of acpi,desc
- Add a check for invalid node
- Add NHLT support
- Capitalise ACPI_OPS_PTR
- Rebase to master

 configs/sandbox_defconfig                 |   1 +
 doc/device-tree-bindings/sound/da7219.txt | 113 +++++++++++++
 drivers/sound/Kconfig                     |   9 ++
 drivers/sound/Makefile                    |   1 +
 drivers/sound/da7219.c                    | 189 ++++++++++++++++++++++
 5 files changed, 313 insertions(+)
 create mode 100644 doc/device-tree-bindings/sound/da7219.txt
 create mode 100644 drivers/sound/da7219.c

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index cb6b4b0ee7..6368e278f2 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -202,6 +202,7 @@ CONFIG_SANDBOX_SERIAL=y
 CONFIG_SMEM=y
 CONFIG_SANDBOX_SMEM=y
 CONFIG_SOUND=y
+CONFIG_SOUND_DA7219=y
 CONFIG_SOUND_SANDBOX=y
 CONFIG_SANDBOX_SPI=y
 CONFIG_SPMI=y
diff --git a/doc/device-tree-bindings/sound/da7219.txt b/doc/device-tree-bindings/sound/da7219.txt
new file mode 100644
index 0000000000..5fd8a9f1e7
--- /dev/null
+++ b/doc/device-tree-bindings/sound/da7219.txt
@@ -0,0 +1,113 @@
+Dialog Semiconductor DA7219 Audio Codec bindings
+
+DA7219 is an audio codec with advanced accessory detect features.
+
+======
+
+Required properties:
+- compatible : Should be "dlg,da7219"
+- reg: Specifies the I2C slave address
+
+- interrupts : IRQ line info for DA7219.
+  (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+   further information relating to interrupt properties)
+
+- VDD-supply: VDD power supply for the device
+- VDDMIC-supply: VDDMIC power supply for the device
+- VDDIO-supply: VDDIO power supply for the device
+  (See Documentation/devicetree/bindings/regulator/regulator.txt for further
+   information relating to regulators)
+
+Optional properties:
+- interrupt-names : Name associated with interrupt line. Should be "wakeup" if
+  interrupt is to be used to wake system, otherwise "irq" should be used.
+- wakeup-source: Flag to indicate this device can wake system (suspend/resume).
+
+- #clock-cells :  Should be set to '<0>', only one clock source provided;
+- clock-output-names : Name given for DAI clocks output;
+
+- clocks : phandle and clock specifier for codec MCLK.
+- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
+
+- dlg,micbias-lvl : Voltage (mV) for Mic Bias
+	[<1600>, <1800>, <2000>, <2200>, <2400>, <2600>]
+- dlg,mic-amp-in-sel : Mic input source type
+	["diff", "se_p", "se_n"]
+- dlg,mclk-name : String name of MCLK for ACPI
+
+Deprecated properties:
+- dlg,ldo-lvl : Required internal LDO voltage (mV) level for digital engine
+  (LDO unavailable in production HW so property no longer required).
+
+======
+
+Child node - 'da7219_aad':
+
+Optional properties:
+- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
+	[<2800>, <2900>]
+- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
+- dlg,btn-cfg : Periodic button press measurements for 4-pole jack (ms)
+	[<2>, <5>, <10>, <50>, <100>, <200>, <500>]
+- dlg,mic-det-thr : Impedance threshold for mic detection measurement (Ohms)
+	[<200>, <500>, <750>, <1000>]
+- dlg,jack-ins-deb : Debounce time for jack insertion (ms)
+	[<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>]
+- dlg,jack-det-rate: Jack type detection latency (3/4 pole)
+	["32ms_64ms", "64ms_128ms", "128ms_256ms", "256ms_512ms"]
+- dlg,jack-rem-deb : Debounce time for jack removal (ms)
+	[<1>, <5>, <10>, <20>]
+- dlg,a-d-btn-thr : Impedance threshold between buttons A and D
+	[0x0 - 0xFF]
+- dlg,d-b-btn-thr : Impedance threshold between buttons D and B
+	[0x0 - 0xFF]
+- dlg,b-c-btn-thr : Impedance threshold between buttons B and C
+	[0x0 - 0xFF]
+- dlg,c-mic-btn-thr : Impedance threshold between button C and Mic
+	[0x0 - 0xFF]
+- dlg,btn-avg : Number of 8-bit readings for averaged button measurement
+	[<1>, <2>, <4>, <8>]
+- dlg,adc-1bit-rpt : Repeat count for 1-bit button measurement
+	[<1>, <2>, <4>, <8>]
+
+======
+
+Example:
+
+	codec: da7219 at 1a {
+		compatible = "dlg,da7219";
+		reg = <0x1a>;
+
+		interrupt-parent = <&gpio6>;
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+
+		VDD-supply = <&reg_audio>;
+		VDDMIC-supply = <&reg_audio>;
+		VDDIO-supply = <&reg_audio>;
+
+		#clock-cells = <0>;
+		clock-output-names = "dai-clks";
+
+		clocks = <&clks 201>;
+		clock-names = "mclk";
+
+		dlg,ldo-lvl = <1200>;
+		dlg,micbias-lvl = <2600>;
+		dlg,mic-amp-in-sel = "diff";
+
+		da7219_aad {
+			dlg,btn-cfg = <50>;
+			dlg,mic-det-thr = <500>;
+			dlg,jack-ins-deb = <20>;
+			dlg,jack-det-rate = "32ms_64ms";
+			dlg,jack-rem-deb = <1>;
+
+			dlg,a-d-btn-thr = <0xa>;
+			dlg,d-b-btn-thr = <0x16>;
+			dlg,b-c-btn-thr = <0x21>;
+			dlg,c-mic-btn-thr = <0x3E>;
+
+			dlg,btn-avg = <4>;
+			dlg,adc-1bit-rpt = <1>;
+		};
+	};
diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
index 4ebc719be2..7f214b97be 100644
--- a/drivers/sound/Kconfig
+++ b/drivers/sound/Kconfig
@@ -40,6 +40,15 @@ config I2S_SAMSUNG
 	  option provides an implementation for sound_init() and
 	  sound_play().
 
+config SOUND_DA7219
+	bool "Dialog Semiconductor audio codec"
+	depends on SOUND
+	help
+	  The DA7219 is an ultra-low-power audio codec with Advanced Accessory
+	  Detection (AAD). This driver only supports generation of ACPI tables.
+	  It does not support sound output or any of the other codec
+	  features.
+
 config SOUND_I8254
 	bool "Intel i8254 timer / beeper"
 	depends on SOUND
diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
index 73ed7fe53c..8c3933ad15 100644
--- a/drivers/sound/Makefile
+++ b/drivers/sound/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SOUND)	+= sound.o
 obj-$(CONFIG_SOUND)	+= codec-uclass.o
 obj-$(CONFIG_SOUND)	+= i2s-uclass.o
 obj-$(CONFIG_SOUND)	+= sound-uclass.o
+obj-$(CONFIG_SOUND_DA7219)	+= da7219.o
 obj-$(CONFIG_I2S_SAMSUNG)	+= samsung-i2s.o
 obj-$(CONFIG_SOUND_SANDBOX)	+= sandbox.o
 obj-$(CONFIG_I2S_ROCKCHIP)	+= rockchip_i2s.o rockchip_sound.o
diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c
new file mode 100644
index 0000000000..454e2591ed
--- /dev/null
+++ b/drivers/sound/da7219.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ACPI driver for DA7219 codec
+ *
+ * Copyright 2019 Google LLC
+ * Parts taken from coreboot
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <irq.h>
+#include <log.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpi_dp.h>
+#ifdef CONFIG_X86
+#include <asm/acpi_nhlt.h>
+#endif
+#include <asm-generic/gpio.h>
+#include <dt-bindings/sound/nhlt.h>
+#include <dm/acpi.h>
+
+#define DA7219_ACPI_HID		"DLGS7219"
+
+static int da7219_acpi_fill_ssdt(const struct udevice *dev,
+				 struct acpi_ctx *ctx)
+{
+	char scope[ACPI_PATH_MAX];
+	char name[ACPI_NAME_MAX];
+	struct acpi_dp *dsd, *aad;
+	ofnode node;
+	u32 val;
+	int ret;
+
+	ret = acpi_device_scope(dev, scope, sizeof(scope));
+	if (ret)
+		return log_msg_ret("scope", ret);
+	ret = acpi_get_name(dev, name);
+	if (ret)
+		return log_msg_ret("name", ret);
+
+	/* Device */
+	acpigen_write_scope(ctx, scope);
+	acpigen_write_device(ctx, name);
+	acpigen_write_name_string(ctx, "_HID", DA7219_ACPI_HID);
+	acpigen_write_name_integer(ctx, "_UID", 1);
+	acpigen_write_name_string(ctx, "_DDN",
+				  dev_read_string(dev, "acpi,ddn"));
+	acpigen_write_name_integer(ctx, "_S0W", 4);
+	acpigen_write_sta(ctx, acpi_device_status(dev));
+
+	/* Resources */
+	acpigen_write_name(ctx, "_CRS");
+	acpigen_write_resourcetemplate_header(ctx);
+	ret = acpi_device_write_i2c_dev(ctx, dev);
+	if (ret)
+		return log_msg_ret("i2c", ret);
+
+	/* Use either Interrupt() or GpioInt() */
+	ret = acpi_device_write_interrupt_or_gpio(ctx, (struct udevice *)dev,
+						  "req-gpios");
+	if (ret)
+		return log_msg_ret("irq_gpio", ret);
+	acpigen_write_resourcetemplate_footer(ctx);
+
+	/* AAD Child Device Properties */
+	aad = acpi_dp_new_table("DAAD");
+	if (!aad)
+		return log_msg_ret("aad", -ENOMEM);
+
+	node = ofnode_find_subnode(dev_ofnode(dev), "da7219_aad");
+	if (!ofnode_valid(node))
+		return log_msg_ret("da7219_aad", -EINVAL);
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,btn-cfg");
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,mic-det-thr");
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,jack-ins-deb");
+	acpi_dp_ofnode_copy_str(node, aad, "dlg,jack-det-rate");
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,jack-rem-deb");
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,a-d-btn-thr");
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,d-b-btn-thr");
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,b-c-btn-thr");
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,c-mic-btn-thr");
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,btn-avg");
+	acpi_dp_ofnode_copy_int(node, aad, "dlg,adc-1bit-rpt");
+	if (!ofnode_read_u32(node, "dlg,micbias-pulse-lvl", &val)) {
+		acpi_dp_ofnode_copy_int(node, aad, "dlg,micbias-pulse-lvl");
+		acpi_dp_ofnode_copy_int(node, aad, "dlg,micbias-pulse-time");
+	}
+
+	/* DA7219 Properties */
+	dsd = acpi_dp_new_table("_DSD");
+	if (!dsd)
+		return log_msg_ret("dsd", -ENOMEM);
+	acpi_dp_dev_copy_int(dev, dsd, "dlg,micbias-lvl");
+	acpi_dp_dev_copy_str(dev, dsd, "dlg,mic-amp-in-sel");
+	acpi_dp_dev_copy_str(dev, dsd, "dlg,mclk-name");
+	acpi_dp_add_child(dsd, "da7219_aad", aad);
+
+	/* Write Device Property Hierarchy */
+	acpi_dp_write(ctx, dsd);
+
+	acpigen_pop_len(ctx); /* Device */
+	acpigen_pop_len(ctx); /* Scope */
+
+	return 0;
+}
+
+#ifdef CONFIG_X86
+static const struct nhlt_format_config da7219_formats[] = {
+	/* 48 KHz 24-bits per sample. */
+	{
+		.num_channels = 2,
+		.sample_freq_khz = 48,
+		.container_bits_per_sample = 32,
+		.valid_bits_per_sample = 24,
+		.settings_file = "dialog-2ch-48khz-24b.dat",
+	},
+};
+
+static const struct nhlt_tdm_config tdm_config = {
+	.virtual_slot = 0,
+	.config_type = NHLT_TDM_BASIC,
+};
+
+static const struct nhlt_endp_descriptor da7219_descriptors[] = {
+	/* Render Endpoint */
+	{
+		.link = NHLT_LINK_SSP,
+		.device = NHLT_SSP_DEV_I2S,
+		.direction = NHLT_DIR_RENDER,
+		.vid = NHLT_VID,
+		.did = NHLT_DID_SSP,
+		.cfg = &tdm_config,
+		.cfg_size = sizeof(tdm_config),
+		.formats = da7219_formats,
+		.num_formats = ARRAY_SIZE(da7219_formats),
+	},
+	/* Capture Endpoint */
+	{
+		.link = NHLT_LINK_SSP,
+		.device = NHLT_SSP_DEV_I2S,
+		.direction = NHLT_DIR_CAPTURE,
+		.vid = NHLT_VID,
+		.did = NHLT_DID_SSP,
+		.cfg = &tdm_config,
+		.cfg_size = sizeof(tdm_config),
+		.formats = da7219_formats,
+		.num_formats = ARRAY_SIZE(da7219_formats),
+	},
+};
+
+static int da7219_acpi_setup_nhlt(const struct udevice *dev,
+				  struct acpi_ctx *ctx)
+{
+	u32 hwlink;
+	int ret;
+
+	if (dev_read_u32(dev, "acpi,audio-link", &hwlink))
+		return log_msg_ret("link", -EINVAL);
+
+	/* Virtual bus id of SSP links are the hardware port ids proper. */
+	ret = nhlt_add_ssp_endpoints(ctx->nhlt, hwlink, da7219_descriptors,
+				     ARRAY_SIZE(da7219_descriptors));
+	if (ret)
+		return log_msg_ret("add", ret);
+
+	return 0;
+}
+#endif
+
+struct acpi_ops da7219_acpi_ops = {
+	.fill_ssdt	= da7219_acpi_fill_ssdt,
+#ifdef CONFIG_X86
+	.setup_nhlt	= da7219_acpi_setup_nhlt,
+#endif
+};
+
+static const struct udevice_id da7219_ids[] = {
+	{ .compatible = "dlg,da7219" },
+	{ }
+};
+
+U_BOOT_DRIVER(da7219) = {
+	.name		= "da7219",
+	.id		= UCLASS_MISC,
+	.of_match	= da7219_ids,
+	ACPI_OPS_PTR(&da7219_acpi_ops)
+};
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 16/43] sound: Add an ACPI driver for Maxim MAX98357ac

[Simon Glass]

This chip is used on coral and we need to generate ACPI tables for sound
to make it work. Add a driver that does just this (i.e. at present does
not actually support playing sound).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v1:
- Use acpi,ddn instead of acpi,desc
- Drop the unwanted acpi_device_write_gpio_desc()
- Rename max97357a to max98357a
- Add NHLT support
- Capitalise ACPI_OPS_PTR
- Rebase to master

 configs/sandbox_defconfig                    |   1 +
 doc/device-tree-bindings/sound/max98357a.txt |  22 +++
 drivers/sound/Kconfig                        |   9 ++
 drivers/sound/Makefile                       |   1 +
 drivers/sound/max98357a.c                    | 160 +++++++++++++++++++
 5 files changed, 193 insertions(+)
 create mode 100644 doc/device-tree-bindings/sound/max98357a.txt
 create mode 100644 drivers/sound/max98357a.c

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 6368e278f2..96c6e0fcd5 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -203,6 +203,7 @@ CONFIG_SMEM=y
 CONFIG_SANDBOX_SMEM=y
 CONFIG_SOUND=y
 CONFIG_SOUND_DA7219=y
+CONFIG_SOUND_MAX98357A=y
 CONFIG_SOUND_SANDBOX=y
 CONFIG_SANDBOX_SPI=y
 CONFIG_SPMI=y
diff --git a/doc/device-tree-bindings/sound/max98357a.txt b/doc/device-tree-bindings/sound/max98357a.txt
new file mode 100644
index 0000000000..4bce14ce80
--- /dev/null
+++ b/doc/device-tree-bindings/sound/max98357a.txt
@@ -0,0 +1,22 @@
+Maxim MAX98357A audio DAC
+
+This node models the Maxim MAX98357A DAC.
+
+Required properties:
+- compatible   : "maxim,max98357a"
+
+Optional properties:
+- sdmode-gpios : GPIO specifier for the chip's SD_MODE pin.
+        If this option is not specified then driver does not manage
+        the pin state (e.g. chip is always on).
+- sdmode-delay : specify delay time for SD_MODE pin.
+        If this option is specified, which means it's required i2s clocks
+        ready before SD_MODE is unmuted in order to avoid the speaker pop noise.
+        It's observed that 5ms is sufficient.
+
+Example:
+
+max98357a {
+	compatible = "maxim,max98357a";
+	sdmode-gpios = <&qcom_pinmux 25 0>;
+};
diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
index 7f214b97be..0948d8caab 100644
--- a/drivers/sound/Kconfig
+++ b/drivers/sound/Kconfig
@@ -113,6 +113,15 @@ config SOUND_MAX98095
 	  audio data and I2C for codec control. At present it only works
 	  with the Samsung I2S driver.
 
+config SOUND_MAX98357A
+	bool "Support Maxim max98357a audio codec"
+	depends on PCI
+	help
+	  Enable the max98357a audio codec. This is connected on PCI for
+	  audio data codec control. This is currently only capable of providing
+	  ACPI information. A full driver (with sound in U-Boot) is currently
+	  not available.
+
 config SOUND_RT5677
 	bool "Support Realtek RT5677 audio codec"
 	depends on SOUND
diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
index 8c3933ad15..9b40c8012f 100644
--- a/drivers/sound/Makefile
+++ b/drivers/sound/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_SOUND_WM8994)	+= wm8994.o
 obj-$(CONFIG_SOUND_MAX98088)	+= max98088.o maxim_codec.o
 obj-$(CONFIG_SOUND_MAX98090)	+= max98090.o maxim_codec.o
 obj-$(CONFIG_SOUND_MAX98095)	+= max98095.o maxim_codec.o
+obj-$(CONFIG_SOUND_MAX98357A)	+= max98357a.o
 obj-$(CONFIG_SOUND_INTEL_HDA)	+= hda_codec.o
 obj-$(CONFIG_SOUND_I8254)	+= i8254_beep.o
 obj-$(CONFIG_SOUND_RT5677)	+= rt5677.o
diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c
new file mode 100644
index 0000000000..33fdd0ba1e
--- /dev/null
+++ b/drivers/sound/max98357a.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * max98357a.c -- MAX98357A Audio driver
+ *
+ * Copyright 2019 Google LLC
+ * Parts taken from coreboot
+ */
+
+#include <common.h>
+#include <audio_codec.h>
+#include <dm.h>
+#include <log.h>
+#include <sound.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpi_dp.h>
+#include <asm-generic/gpio.h>
+#ifdef CONFIG_X86
+#include <asm/acpi_nhlt.h>
+#endif
+#include <dt-bindings/sound/nhlt.h>
+#include <dm/acpi.h>
+
+struct max98357a_priv {
+	struct gpio_desc sdmode_gpio;
+};
+
+static int max98357a_ofdata_to_platdata(struct udevice *dev)
+{
+	struct max98357a_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = gpio_request_by_name(dev, "sdmode-gpios", 0, &priv->sdmode_gpio,
+				   GPIOD_IS_IN);
+	if (ret)
+		return log_msg_ret("gpio", ret);
+
+	return 0;
+}
+
+static int max98357a_acpi_fill_ssdt(const struct udevice *dev,
+				    struct acpi_ctx *ctx)
+{
+	struct max98357a_priv *priv = dev_get_priv(dev);
+	char scope[ACPI_PATH_MAX];
+	char name[ACPI_NAME_MAX];
+	char path[ACPI_PATH_MAX];
+	struct acpi_dp *dp;
+	int ret;
+
+	ret = acpi_device_scope(dev, scope, sizeof(scope));
+	if (ret)
+		return log_msg_ret("scope", ret);
+	ret = acpi_get_name(dev, name);
+	if (ret)
+		return log_msg_ret("name", ret);
+
+	/* Device */
+	acpigen_write_scope(ctx, scope);
+	acpigen_write_device(ctx, name);
+	acpigen_write_name_string(ctx, "_HID",
+				  dev_read_string(dev, "acpi,hid"));
+	acpigen_write_name_integer(ctx, "_UID", 0);
+	acpigen_write_name_string(ctx, "_DDN",
+				  dev_read_string(dev, "acpi,ddn"));
+	acpigen_write_sta(ctx, acpi_device_status(dev));
+
+	/* Resources */
+	acpigen_write_name(ctx, "_CRS");
+	acpigen_write_resourcetemplate_header(ctx);
+	ret = acpi_device_write_gpio_desc(ctx, &priv->sdmode_gpio);
+	if (ret)
+		return log_msg_ret("gpio", ret);
+	acpigen_write_resourcetemplate_footer(ctx);
+
+	/* _DSD for devicetree properties */
+	/* This points to the first pin in the first gpio entry in _CRS */
+	ret = acpi_device_path(dev, path, sizeof(path));
+	if (ret)
+		return log_msg_ret("path", ret);
+	dp = acpi_dp_new_table("_DSD");
+	acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0,
+			 priv->sdmode_gpio.flags & GPIOD_ACTIVE_LOW ?
+			 ACPI_GPIO_ACTIVE_LOW : ACPI_GPIO_ACTIVE_HIGH);
+	acpi_dp_add_integer(dp, "sdmode-delay",
+			    dev_read_u32_default(dev, "sdmode-delay", 0));
+	acpi_dp_write(ctx, dp);
+
+	acpigen_pop_len(ctx); /* Device */
+	acpigen_pop_len(ctx); /* Scope */
+
+	return 0;
+}
+
+#ifdef CONFIG_X86
+static const struct nhlt_format_config max98357a_formats[] = {
+	/* 48 KHz 24-bits per sample. */
+	{
+		.num_channels = 2,
+		.sample_freq_khz = 48,
+		.container_bits_per_sample = 32,
+		.valid_bits_per_sample = 24,
+		.settings_file = "max98357-render-2ch-48khz-24b.dat",
+	},
+};
+
+static const struct nhlt_endp_descriptor max98357a_descriptors[] = {
+	{
+		.link = NHLT_LINK_SSP,
+		.device = NHLT_SSP_DEV_I2S,
+		.direction = NHLT_DIR_RENDER,
+		.vid = NHLT_VID,
+		.did = NHLT_DID_SSP,
+		.formats = max98357a_formats,
+		.num_formats = ARRAY_SIZE(max98357a_formats),
+	},
+};
+
+static int max98357a_acpi_setup_nhlt(const struct udevice *dev,
+				     struct acpi_ctx *ctx)
+{
+	u32 hwlink;
+	int ret;
+
+	if (dev_read_u32(dev, "acpi,audio-link", &hwlink))
+		return log_msg_ret("link", -EINVAL);
+
+	/* Virtual bus id of SSP links are the hardware port ids proper. */
+	ret = nhlt_add_ssp_endpoints(ctx->nhlt, hwlink, max98357a_descriptors,
+				     ARRAY_SIZE(max98357a_descriptors));
+	if (ret)
+		return log_msg_ret("add", ret);
+
+	return 0;
+}
+#endif
+
+struct acpi_ops max98357a_acpi_ops = {
+	.fill_ssdt	= max98357a_acpi_fill_ssdt,
+#ifdef CONFIG_X86
+	.setup_nhlt	= max98357a_acpi_setup_nhlt,
+#endif
+};
+
+static const struct audio_codec_ops max98357a_ops = {
+};
+
+static const struct udevice_id max98357a_ids[] = {
+	{ .compatible = "maxim,max98357a" },
+	{ }
+};
+
+U_BOOT_DRIVER(max98357a) = {
+	.name		= "max98357a",
+	.id		= UCLASS_AUDIO_CODEC,
+	.of_match	= max98357a_ids,
+	.ofdata_to_platdata	= max98357a_ofdata_to_platdata,
+	.ops		= &max98357a_ops,
+	ACPI_OPS_PTR(&max98357a_acpi_ops)
+};
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 17/43] x86: pinctrl: Add a way to get the pinctrl reg address

[Simon Glass]

At present we can query the offset of a pinctrl register within the p2sb.
For ACPI we need to get the actual address of the register. Add a function
to handle this and rename the old one to more accurately reflect its
purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/intel_pinctrl.h | 16 ++++++++++++++--
 drivers/gpio/intel_gpio.c            | 15 +++++++++++----
 drivers/misc/p2sb-uclass.c           | 16 ++++++++--------
 drivers/pinctrl/intel/pinctrl.c      | 11 +++++++++--
 include/p2sb.h                       |  9 +++++++++
 5 files changed, 51 insertions(+), 16 deletions(-)

diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
index e2524b089d..f39ebde539 100644
--- a/arch/x86/include/asm/intel_pinctrl.h
+++ b/arch/x86/include/asm/intel_pinctrl.h
@@ -263,11 +263,23 @@ int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
 int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size);
 
 /**
- * intel_pinctrl_get_config_reg_addr() - Get address of the pin config registers
+ * intel_pinctrl_get_config_reg_offset() - Get offset of pin config registers
  *
+ * This works out the register offset of a pin within the p2sb region.
+ *
+ * @dev: Pinctrl device
+ * @offset: GPIO offset within this device
+ * @return register offset of first register within the GPIO p2sb region
+ */
+u32 intel_pinctrl_get_config_reg_offset(struct udevice *dev, uint offset);
+
+/**
+ * intel_pinctrl_get_config_reg_offset() - Get address of pin config registers
+ *
+ * This works out the absolute address of the registers for a pin
  * @dev: Pinctrl device
  * @offset: GPIO offset within this device
- * @return register offset within the GPIO p2sb region
+ * @return register offset of first register within the GPIO p2sb region
  */
 u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset);
 
diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c
index 711fea1b58..b4d5be97da 100644
--- a/drivers/gpio/intel_gpio.c
+++ b/drivers/gpio/intel_gpio.c
@@ -24,7 +24,9 @@
 static int intel_gpio_direction_input(struct udevice *dev, uint offset)
 {
 	struct udevice *pinctrl = dev_get_parent(dev);
-	uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
+	uint config_offset;
+
+	config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
 
 	pcr_clrsetbits32(pinctrl, config_offset,
 			 PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
@@ -38,7 +40,9 @@ static int intel_gpio_direction_output(struct udevice *dev, uint offset,
 				       int value)
 {
 	struct udevice *pinctrl = dev_get_parent(dev);
-	uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
+	uint config_offset;
+
+	config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
 
 	pcr_clrsetbits32(pinctrl, config_offset,
 			 PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
@@ -68,10 +72,13 @@ static int intel_gpio_get_value(struct udevice *dev, uint offset)
 	return 0;
 }
 
-static int intel_gpio_set_value(struct udevice *dev, unsigned offset, int value)
+static int intel_gpio_set_value(struct udevice *dev, unsigned int offset,
+				int value)
 {
 	struct udevice *pinctrl = dev_get_parent(dev);
-	uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
+	uint config_offset;
+
+	config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
 
 	pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
 			 value ? PAD_CFG0_TX_STATE : 0);
diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c
index 06b1e8d9ad..d5fe12ebd8 100644
--- a/drivers/misc/p2sb-uclass.c
+++ b/drivers/misc/p2sb-uclass.c
@@ -18,7 +18,7 @@
 
 #define PCR_COMMON_IOSF_1_0	1
 
-static void *_pcr_reg_address(struct udevice *dev, uint offset)
+void *pcr_reg_address(struct udevice *dev, uint offset)
 {
 	struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
 	struct udevice *p2sb = dev_get_parent(dev);
@@ -55,7 +55,7 @@ uint pcr_read32(struct udevice *dev, uint offset)
 	/* Ensure the PCR offset is correctly aligned */
 	assert(IS_ALIGNED(offset, sizeof(uint32_t)));
 
-	ptr = _pcr_reg_address(dev, offset);
+	ptr = pcr_reg_address(dev, offset);
 	val = readl(ptr);
 	unmap_sysmem(ptr);
 
@@ -67,7 +67,7 @@ uint pcr_read16(struct udevice *dev, uint offset)
 	/* Ensure the PCR offset is correctly aligned */
 	check_pcr_offset_align(offset, sizeof(uint16_t));
 
-	return readw(_pcr_reg_address(dev, offset));
+	return readw(pcr_reg_address(dev, offset));
 }
 
 uint pcr_read8(struct udevice *dev, uint offset)
@@ -75,7 +75,7 @@ uint pcr_read8(struct udevice *dev, uint offset)
 	/* Ensure the PCR offset is correctly aligned */
 	check_pcr_offset_align(offset, sizeof(uint8_t));
 
-	return readb(_pcr_reg_address(dev, offset));
+	return readb(pcr_reg_address(dev, offset));
 }
 
 /*
@@ -86,7 +86,7 @@ uint pcr_read8(struct udevice *dev, uint offset)
  */
 static void write_completion(struct udevice *dev, uint offset)
 {
-	readl(_pcr_reg_address(dev, ALIGN_DOWN(offset, sizeof(uint32_t))));
+	readl(pcr_reg_address(dev, ALIGN_DOWN(offset, sizeof(uint32_t))));
 }
 
 void pcr_write32(struct udevice *dev, uint offset, uint indata)
@@ -94,7 +94,7 @@ void pcr_write32(struct udevice *dev, uint offset, uint indata)
 	/* Ensure the PCR offset is correctly aligned */
 	assert(IS_ALIGNED(offset, sizeof(indata)));
 
-	writel(indata, _pcr_reg_address(dev, offset));
+	writel(indata, pcr_reg_address(dev, offset));
 	/* Ensure the writes complete */
 	write_completion(dev, offset);
 }
@@ -104,7 +104,7 @@ void pcr_write16(struct udevice *dev, uint offset, uint indata)
 	/* Ensure the PCR offset is correctly aligned */
 	check_pcr_offset_align(offset, sizeof(uint16_t));
 
-	writew(indata, _pcr_reg_address(dev, offset));
+	writew(indata, pcr_reg_address(dev, offset));
 	/* Ensure the writes complete */
 	write_completion(dev, offset);
 }
@@ -114,7 +114,7 @@ void pcr_write8(struct udevice *dev, uint offset, uint indata)
 	/* Ensure the PCR offset is correctly aligned */
 	check_pcr_offset_align(offset, sizeof(uint8_t));
 
-	writeb(indata, _pcr_reg_address(dev, offset));
+	writeb(indata, pcr_reg_address(dev, offset));
 	/* Ensure the writes complete */
 	write_completion(dev, offset);
 }
diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c
index ba8206350e..bf3989bf32 100644
--- a/drivers/pinctrl/intel/pinctrl.c
+++ b/drivers/pinctrl/intel/pinctrl.c
@@ -394,7 +394,7 @@ static int pinctrl_configure_pad(struct udevice *dev,
 	return 0;
 }
 
-u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
+u32 intel_pinctrl_get_config_reg_offset(struct udevice *dev, uint offset)
 {
 	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
 	const struct pad_community *comm = priv->comm;
@@ -407,9 +407,16 @@ u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
 	return config_offset;
 }
 
+u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset)
+{
+	uint config_offset = intel_pinctrl_get_config_reg_offset(dev, offset);
+
+	return (u32)(ulong)pcr_reg_address(dev, config_offset);
+}
+
 u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset)
 {
-	uint config_offset = intel_pinctrl_get_config_reg_addr(dev, offset);
+	uint config_offset = intel_pinctrl_get_config_reg_offset(dev, offset);
 
 	return pcr_read32(dev, config_offset);
 }
diff --git a/include/p2sb.h b/include/p2sb.h
index 60c7f70773..74eb08b7ff 100644
--- a/include/p2sb.h
+++ b/include/p2sb.h
@@ -132,4 +132,13 @@ int p2sb_set_port_id(struct udevice *dev, int portid);
  */
 int p2sb_get_port_id(struct udevice *dev);
 
+/**
+ * pcr_reg_address() Convert an offset in p2sb space to an absolute address
+ *
+ * @dev: Child device (whose parent is UCLASS_P2SB)
+ * @offset: Offset within that child's address space
+ * @return pointer to that offset within the child's address space
+ */
+void *pcr_reg_address(struct udevice *dev, uint offset);
+
 #endif
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 18/43] x86: pinctrl: Update comment for intel_pinctrl_get_pad()

[Simon Glass]

Add information about what is returned on error.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/intel_pinctrl.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
index f39ebde539..982b2514a0 100644
--- a/arch/x86/include/asm/intel_pinctrl.h
+++ b/arch/x86/include/asm/intel_pinctrl.h
@@ -300,6 +300,7 @@ u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
  * @pad: Pad to check
  * @devp: Returns pinctrl device containing that pad
  * @offsetp: Returns offset of pad within that pinctrl device
+ * @return 0 if OK, -ENOTBLK if pad number is invalid
  */
 int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp);
 
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 19/43] x86: pinctrl: Add multi-ACPI control

[Simon Glass]

Add a Kconfig to control whether pinctrl is represented as a single ACPI
device or as multiple devices. In the latter case (the default) we should
return the pin number relative to the pinctrl device.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/pinctrl/intel/Kconfig   | 4 ++++
 drivers/pinctrl/intel/pinctrl.c | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index e62a2e0349..05a314af88 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -15,6 +15,10 @@ config INTEL_PINCTRL_IOSTANDBY
 	bool
 	default y
 
+config INTEL_PINCTRL_MULTI_ACPI_DEVICES
+	bool
+	default y
+
 config PINCTRL_INTEL_APL
 	bool "Support Intel Apollo Lake (APL)"
 	help
diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c
index bf3989bf32..32ca303b27 100644
--- a/drivers/pinctrl/intel/pinctrl.c
+++ b/drivers/pinctrl/intel/pinctrl.c
@@ -427,6 +427,8 @@ int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset)
 	const struct pad_community *comm = priv->comm;
 	int group;
 
+	if (IS_ENABLED(CONFIG_INTEL_PINCTRL_MULTI_ACPI_DEVICES))
+		return offset;
 	group = pinctrl_group_index(comm, offset);
 
 	/* If pad base is not set then use GPIO number as ACPI pin number */
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 20/43] x86: pinctrl: Set up itss in the probe() method

[Simon Glass]

At present the itss is probed in the ofdata_to_platdata() method. This is
incorrect since itss is a child of p2sb which itself needs to probe the
pinctrl device. This means that p2sb is effectively not probed when the
itss is probed, so we get the wrong register address from p2sb.

Fix this by moving the itss probe to the correct place.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/pinctrl/intel/pinctrl.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c
index 32ca303b27..ba21c9dcc2 100644
--- a/drivers/pinctrl/intel/pinctrl.c
+++ b/drivers/pinctrl/intel/pinctrl.c
@@ -619,15 +619,11 @@ int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
 {
 	struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
 	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
-	int ret;
 
 	if (!comm) {
 		log_err("Cannot find community for pid %d\n", pplat->pid);
 		return -EDOM;
 	}
-	ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss);
-	if (ret)
-		return log_msg_ret("Cannot find ITSS", ret);
 	priv->comm = comm;
 	priv->num_cfgs = num_cfgs;
 
@@ -637,8 +633,12 @@ int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
 int intel_pinctrl_probe(struct udevice *dev)
 {
 	struct intel_pinctrl_priv *priv = dev_get_priv(dev);
+	int ret;
 
 	priv->itss_pol_cfg = true;
+	ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss);
+	if (ret)
+		return log_msg_ret("Cannot find ITSS", ret);
 
 	return 0;
 }
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 21/43] x86: pinctrl: Drop the acpi_name member

[Simon Glass]

This is in the device tree now, so drop the unnecessary field here.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/intel_pinctrl.h | 2 --
 drivers/pinctrl/intel/pinctrl_apl.c  | 4 ----
 2 files changed, 6 deletions(-)

diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
index 982b2514a0..e734f4a7f0 100644
--- a/arch/x86/include/asm/intel_pinctrl.h
+++ b/arch/x86/include/asm/intel_pinctrl.h
@@ -99,7 +99,6 @@ struct pad_group {
  * groups exist inside a community
  *
  * @name: Community name
- * @acpi_path: ACPI path
  * @num_gpi_regs: number of gpi registers in community
  * @max_pads_per_group: number of pads in each group; number of pads bit-mapped
  *	in each GPI status/en and Host Own Reg
@@ -120,7 +119,6 @@ struct pad_group {
  */
 struct pad_community {
 	const char *name;
-	const char *acpi_path;
 	size_t num_gpi_regs;
 	size_t max_pads_per_group;
 	uint first_pad;
diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c
index c14176d4a7..7624a9974f 100644
--- a/drivers/pinctrl/intel/pinctrl_apl.c
+++ b/drivers/pinctrl/intel/pinctrl_apl.c
@@ -75,7 +75,6 @@ static const struct pad_community apl_gpio_communities[] = {
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 		.name = "GPIO_GPE_N",
-		.acpi_path = "\\_SB.GPO0",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = apl_community_n_groups,
@@ -94,7 +93,6 @@ static const struct pad_community apl_gpio_communities[] = {
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 		.name = "GPIO_GPE_NW",
-		.acpi_path = "\\_SB.GPO1",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = apl_community_nw_groups,
@@ -113,7 +111,6 @@ static const struct pad_community apl_gpio_communities[] = {
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 		.name = "GPIO_GPE_W",
-		.acpi_path = "\\_SB.GPO2",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = apl_community_w_groups,
@@ -132,7 +129,6 @@ static const struct pad_community apl_gpio_communities[] = {
 		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 		.name = "GPIO_GPE_SW",
-		.acpi_path = "\\_SB.GPO3",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = apl_community_sw_groups,
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 22/43] x86: Add support for building up an NHLT structure

[Simon Glass]

The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.

Add functions to allow adding to the structure that is eventually written
to the ACPI tables. Also add the device-tree bindings.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v1:
- Add a new patch to support building up an NHLT structure

 arch/x86/include/asm/acpi_nhlt.h | 314 ++++++++++++++++++++
 arch/x86/lib/Makefile            |   1 +
 arch/x86/lib/acpi_nhlt.c         | 482 +++++++++++++++++++++++++++++++
 3 files changed, 797 insertions(+)
 create mode 100644 arch/x86/include/asm/acpi_nhlt.h
 create mode 100644 arch/x86/lib/acpi_nhlt.c

diff --git a/arch/x86/include/asm/acpi_nhlt.h b/arch/x86/include/asm/acpi_nhlt.h
new file mode 100644
index 0000000000..4d2573d5ff
--- /dev/null
+++ b/arch/x86/include/asm/acpi_nhlt.h
@@ -0,0 +1,314 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ *
+ * Modified from coreboot nhlt.h
+ */
+
+#ifndef _NHLT_H_
+#define _NHLT_H_
+
+struct acpi_ctx;
+struct nhlt;
+struct nhlt_endpoint;
+struct nhlt_format;
+struct nhlt_format_config;
+
+/*
+ * Non HD Audio ACPI support. This table is typically used for Intel Smart
+ * Sound Technology DSP. It provides a way to encode opaque settings in
+ * the ACPI tables.
+ *
+ * While the structure fields of the NHLT structs are exposed below
+ * the SoC/chipset code should be the only other user manipulating the
+ * fields directly aside from the library itself.
+ *
+ * The NHLT table consists of endpoints which in turn contain different
+ * supporting stream formats. Each endpoint may contain a device specific
+ * configuration payload as well as each stream format.
+ *
+ * Most code should use the SoC variants of the functions because
+ * there is required logic needed to be performed by the SoC. The SoC
+ * code should be abstracting the inner details of these functions that
+ * specically apply to NHLT objects for that SoC.
+ *
+ * An example sequence:
+ *
+ * nhlt = nhlt_init()
+ * ep = nhlt_add_endpoint()
+ * nhlt_endpoint_append_config(ep)
+ * nhlt_endpoint_add_formats(ep)
+ * nhlt_soc_serialise()
+ */
+
+/* Obtain an nhlt object for adding endpoints. Returns NULL on error. */
+struct nhlt *nhlt_init(void);
+
+/* Return the size of the NHLT table including ACPI header. */
+size_t nhlt_current_size(struct nhlt *nhlt);
+
+/*
+ * Helper functions for adding NHLT devices utilizing an nhlt_endp_descriptor
+ * to drive the logic.
+ */
+
+struct nhlt_endp_descriptor {
+	/* NHLT endpoint types. */
+	int link;
+	int device;
+	int direction;
+	u16 vid;
+	u16 did;
+	/* Optional endpoint specific configuration data. */
+	const void *cfg;
+	size_t cfg_size;
+	/* Formats supported for endpoint. */
+	const struct nhlt_format_config *formats;
+	size_t num_formats;
+};
+
+/*
+ * Add the number of endpoints described by each descriptor. The virtual bus
+ * id for each descriptor is the default value of 0.
+ * Returns < 0 on error, 0 on success.
+ */
+int nhlt_add_endpoints(struct nhlt *nhlt,
+		       const struct nhlt_endp_descriptor *epds,
+		       size_t num_epds);
+
+/*
+ * Add the number of endpoints associated with a single NHLT SSP instance id.
+ * Each endpoint described in the endpoint descriptor array uses the provided
+ * virtual bus id. Returns < 0 on error, 0 on success.
+ */
+int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id,
+			   const struct nhlt_endp_descriptor *epds,
+			   size_t num_epds);
+
+/*
+ * Add endpoint to NHLT object. Returns NULL on error.
+ *
+ * generic nhlt_add_endpoint() is called by the SoC code to provide
+ * the specific assumptions/uses for NHLT for that platform. All fields
+ * are the NHLT enumerations found within this header file.
+ */
+struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type,
+					int device_type, int dir,
+					u16 vid, u16 did);
+
+/*
+ * Append blob of configuration to the endpoint proper. Returns 0 on
+ * success, < 0 on error. A copy of the configuration is made so any
+ * resources pointed to by config can be freed after the call.
+ */
+int nhlt_endpoint_append_config(struct nhlt_endpoint *endpoint,
+				const void *config, size_t config_sz);
+
+/* Add a format type to the provided endpoint. Returns NULL on error. */
+struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endpoint,
+				    int num_channels, int sample_freq_khz,
+				    int container_bits_per_sample,
+				    int valid_bits_per_sample,
+				    u32 speaker_mask);
+
+/*
+ * Append blob of configuration to the format proper. Returns 0 on
+ * success, < 0 on error. A copy of the configuration is made so any
+ * resources pointed to by config can be freed after the call.
+ */
+int nhlt_format_append_config(struct nhlt_format *format, const void *config,
+			      size_t config_sz);
+
+/*
+ * Add num_formats described by formats to the endpoint. This function
+ * effectively wraps nhlt_add_format() and nhlt_format_config() using the
+ * data found in each nhlt_format_config object. Returns 0 on success, < 0
+ * on error.
+ */
+int nhlt_endpoint_add_formats(struct nhlt_endpoint *endpoint,
+			      const struct nhlt_format_config *formats,
+			      size_t num_formats);
+
+/*
+ * Increment the instance id for a given link type. This function is
+ * used for marking a device being completely added to the NHLT object.
+ * Subsequent endpoints added to the nhlt object with the same link type
+ * will use incremented instance id.
+ */
+void nhlt_next_instance(struct nhlt *nhlt, int link_type);
+
+/*
+ * Serialize NHLT object to ACPI table. Take in the beginning address of where
+ * the table will reside and return the address of the next ACPI table. On
+ * error 0 will be returned. The NHLT object is no longer valid after this
+ * function is called.
+ */
+uintptr_t nhlt_serialise(struct nhlt *nhlt, uintptr_t acpi_addr);
+
+/*
+ * Serialize NHLT object to ACPI table. Take in the beginning address of where
+ * the table will reside oem_id and oem_table_id and return the address of the
+ * next ACPI table. On error 0 will be returned. The NHLT object is no longer
+ * valid after this function is called.
+ */
+int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt,
+				 const char *oem_id, const char *oem_table_id,
+				 u32 oem_revision);
+
+int nhlt_setup(struct nhlt *nhlt, ofnode node);
+
+/* Link and device types. */
+enum {
+	NHLT_LINK_HDA,
+	NHLT_LINK_DSP,
+	NHLT_LINK_PDM,
+	NHLT_LINK_SSP,
+	NHLT_MAX_LINK_TYPES,
+};
+
+enum {
+	NHLT_SSP_DEV_BT, /* Bluetooth */
+	NHLT_SSP_DEV_MODEM,
+	NHLT_SSP_DEV_FM,
+	NHLT_SSP_DEV_RESERVED,
+	NHLT_SSP_DEV_I2S = 4,
+};
+
+enum {
+	NHLT_PDM_DEV,
+};
+
+/* Endpoint direction. */
+enum {
+	NHLT_DIR_RENDER,
+	NHLT_DIR_CAPTURE,
+	NHLT_DIR_BIDIRECTIONAL,
+};
+
+/*
+ * Channel mask for an endpoint. While they are prefixed with 'SPEAKER' the
+ * channel masks are also used for capture devices
+ */
+enum {
+	SPEAKER_FRONT_LEFT = 1 << 0,
+	SPEAKER_FRONT_RIGHT = 1 << 1,
+	SPEAKER_FRONT_CENTER = 1 << 2,
+	SPEAKER_LOW_FREQUENCY = 1 << 3,
+	SPEAKER_BACK_LEFT = 1 << 4,
+	SPEAKER_BACK_RIGHT = 1 << 5,
+	SPEAKER_FRONT_LEFT_OF_CENTER = 1 << 6,
+	SPEAKER_FRONT_RIGHT_OF_CENTER = 1 << 7,
+	SPEAKER_BACK_CENTER = 1 << 8,
+	SPEAKER_SIDE_LEFT = 1 << 9,
+	SPEAKER_SIDE_RIGHT = 1 << 10,
+	SPEAKER_TOP_CENTER = 1 << 11,
+	SPEAKER_TOP_FRONT_LEFT = 1 << 12,
+	SPEAKER_TOP_FRONT_CENTER = 1 << 13,
+	SPEAKER_TOP_FRONT_RIGHT = 1 << 14,
+	SPEAKER_TOP_BACK_LEFT = 1 << 15,
+	SPEAKER_TOP_BACK_CENTER = 1 << 16,
+	SPEAKER_TOP_BACK_RIGHT = 1 << 17,
+};
+
+/*
+ * Supporting structures. Only SoC/chipset and the library code directly should
+ * be manipulating these structures
+ */
+struct sub_format {
+	u32 data1;
+	u16 data2;
+	u16 data3;
+	u8 data4[8];
+};
+
+struct nhlt_specific_config {
+	u32 size;
+	void *capabilities;
+};
+
+struct nhlt_waveform {
+	u16 tag;
+	u16 num_channels;
+	u32 samples_per_second;
+	u32 bytes_per_second;
+	u16 block_align;
+	u16 bits_per_sample;
+	u16 extra_size;
+	u16 valid_bits_per_sample;
+	u32 channel_mask;
+	struct sub_format sub_format;
+};
+
+struct nhlt_format {
+	struct nhlt_waveform waveform;
+	struct nhlt_specific_config config;
+};
+
+/*
+ * This struct is used by nhlt_endpoint_add_formats() for easily adding
+ * waveform formats with associated settings file.
+ */
+struct nhlt_format_config {
+	int num_channels;
+	int sample_freq_khz;
+	int container_bits_per_sample;
+	int valid_bits_per_sample;
+	u32 speaker_mask;
+	const char *settings_file;
+};
+
+/* Arbitrary max number of formats per endpoint. */
+#define MAX_FORMATS 2
+struct nhlt_endpoint {
+	u32 length;
+	u8 link_type;
+	u8 instance_id;
+	u16 vendor_id;
+	u16 device_id;
+	u16 revision_id;
+	u32 subsystem_id;
+	u8 device_type;
+	u8 direction;
+	u8 virtual_bus_id;
+	struct nhlt_specific_config config;
+	u8 num_formats;
+	struct nhlt_format formats[MAX_FORMATS];
+};
+
+#define MAX_ENDPOINTS 8
+struct nhlt {
+	u32 subsystem_id;
+	u8 num_endpoints;
+	struct nhlt_endpoint endpoints[MAX_ENDPOINTS];
+	u8 current_instance_id[NHLT_MAX_LINK_TYPES];
+};
+
+struct nhlt_tdm_config {
+	u8 virtual_slot;
+	u8 config_type;
+};
+
+enum {
+	NHLT_TDM_BASIC,
+	NHLT_TDM_MIC_ARRAY,
+};
+
+struct nhlt_dmic_array_config {
+	struct nhlt_tdm_config tdm_config;
+	u8 array_type;
+};
+
+/*
+ * Microphone array definitions may be found here:
+ * https://msdn.microsoft.com/en-us/library/windows/hardware/dn613960%28v=vs.85%29.aspx
+ */
+enum {
+	NHLT_MIC_ARRAY_2CH_SMALL = 0xa,
+	NHLT_MIC_ARRAY_2CH_BIG = 0xb,
+	NHLT_MIC_ARRAY_4CH_1ST_GEOM = 0xc,
+	NHLT_MIC_ARRAY_4CH_L_SHAPED = 0xd,
+	NHLT_MIC_ARRAY_4CH_2ND_GEOM = 0xe,
+	NHLT_MIC_ARRAY_VENDOR_DEFINED = 0xf,
+};
+
+#endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 5cd4587480..4f3e9ad6b6 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -23,6 +23,7 @@ obj-y	+= interrupts.o
 obj-y	+= lpc-uclass.o
 obj-y	+= mpspec.o
 obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
+obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi_nhlt.o
 obj-y	+= northbridge-uclass.o
 obj-$(CONFIG_I8259_PIC) += i8259.o
 obj-$(CONFIG_I8254_TIMER) += i8254.o
diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c
new file mode 100644
index 0000000000..c64dd9c008
--- /dev/null
+++ b/arch/x86/lib/acpi_nhlt.c
@@ -0,0 +1,482 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Google LLC
+ *
+ * Modified from coreboot nhlt.c
+ */
+
+#define LOG_CATEGORY	LOGC_ACPI
+
+#include <common.h>
+#include <binman.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <tables_csum.h>
+#include <acpi/acpi_table.h>
+#include <asm/acpi_nhlt.h>
+#include <asm/unaligned.h>
+#include <dm/acpi.h>
+
+#define NHLT_RID		1
+#define NHLT_SSID		1
+#define WAVEFORMAT_TAG		0xfffe
+#define DEFAULT_VIRTUAL_BUS_ID	0
+
+static const struct sub_format pcm_subformat = {
+	.data1 = 0x00000001,
+	.data2 = 0x0000,
+	.data3 = 0x0010,
+	.data4 = { 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71 },
+};
+
+struct nhlt *nhlt_init(void)
+{
+	struct nhlt *nhlt;
+
+	nhlt = malloc(sizeof(*nhlt));
+
+	if (!nhlt)
+		return NULL;
+
+	memset(nhlt, 0, sizeof(*nhlt));
+	nhlt->subsystem_id = NHLT_SSID;
+
+	return nhlt;
+}
+
+struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type,
+					int device_type, int dir,
+					u16 vid, u16 did)
+{
+	struct nhlt_endpoint *endp;
+
+	if (link_type < NHLT_LINK_HDA || link_type >= NHLT_MAX_LINK_TYPES)
+		return NULL;
+
+	if (nhlt->num_endpoints >= MAX_ENDPOINTS)
+		return NULL;
+
+	endp = &nhlt->endpoints[nhlt->num_endpoints];
+
+	endp->link_type = link_type;
+	endp->instance_id = nhlt->current_instance_id[link_type];
+	endp->vendor_id = vid;
+	endp->device_id = did;
+	endp->revision_id = NHLT_RID;
+	endp->subsystem_id = nhlt->subsystem_id;
+	endp->device_type = device_type;
+	endp->direction = dir;
+	endp->virtual_bus_id = DEFAULT_VIRTUAL_BUS_ID;
+
+	nhlt->num_endpoints++;
+
+	return endp;
+}
+
+static int append_specific_config(struct nhlt_specific_config *spec_cfg,
+				  const void *config, size_t config_sz)
+{
+	size_t new_sz;
+	void *new_cfg;
+
+	new_sz = spec_cfg->size + config_sz;
+	new_cfg = malloc(new_sz);
+	if (!new_cfg)
+		return -ENOMEM;
+
+	/* Append new config */
+	memcpy(new_cfg, spec_cfg->capabilities, spec_cfg->size);
+	memcpy(new_cfg + spec_cfg->size, config, config_sz);
+
+	free(spec_cfg->capabilities);
+
+	/* Update with new config data */
+	spec_cfg->size = new_sz;
+	spec_cfg->capabilities = new_cfg;
+
+	return 0;
+}
+
+int nhlt_endpoint_append_config(struct nhlt_endpoint *endp, const void *config,
+				size_t config_sz)
+{
+	return append_specific_config(&endp->config, config, config_sz);
+}
+
+struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endp,
+				    int num_channels, int sample_freq_khz,
+				    int container_bits_per_sample,
+				    int valid_bits_per_sample,
+				    uint32_t speaker_mask)
+{
+	struct nhlt_format *fmt;
+	struct nhlt_waveform *wave;
+
+	if (endp->num_formats >= MAX_FORMATS)
+		return NULL;
+
+	fmt = &endp->formats[endp->num_formats];
+	wave = &fmt->waveform;
+
+	wave->tag = WAVEFORMAT_TAG;
+	wave->num_channels = num_channels;
+	wave->samples_per_second = sample_freq_khz * 1000;
+	wave->bits_per_sample = container_bits_per_sample;
+	wave->extra_size = sizeof(wave->valid_bits_per_sample);
+	wave->extra_size += sizeof(wave->channel_mask);
+	wave->extra_size += sizeof(wave->sub_format);
+	wave->valid_bits_per_sample = valid_bits_per_sample;
+	wave->channel_mask = speaker_mask;
+	memcpy(&wave->sub_format, &pcm_subformat, sizeof(wave->sub_format));
+
+	/* Calculate the dervied fields */
+	wave->block_align = wave->num_channels * wave->bits_per_sample / 8;
+	wave->bytes_per_second = wave->block_align * wave->samples_per_second;
+
+	endp->num_formats++;
+
+	return fmt;
+}
+
+int nhlt_format_append_config(struct nhlt_format *fmt, const void *config,
+			      size_t config_sz)
+{
+	return append_specific_config(&fmt->config, config, config_sz);
+}
+
+int nhlt_endpoint_add_formats(struct nhlt_endpoint *endp,
+			      const struct nhlt_format_config *formats,
+			      size_t num_formats)
+{
+	ofnode node;
+	size_t i;
+
+	node = binman_section_find_node("private-files");
+
+	for (i = 0; i < num_formats; i++) {
+		const struct nhlt_format_config *cfg = &formats[i];
+		struct nhlt_format *fmt;
+		void *data;
+		int size;
+		int ret;
+
+		fmt = nhlt_add_format(endp, cfg->num_channels,
+				      cfg->sample_freq_khz,
+				      cfg->container_bits_per_sample,
+				      cfg->valid_bits_per_sample,
+				      cfg->speaker_mask);
+		if (!fmt)
+			return -ENOSPC;
+
+		if (!cfg->settings_file)
+			continue;
+
+		ret = binman_entry_map(node, cfg->settings_file, &data, &size);
+		if (ret) {
+			log_warning("Failed to find settings file %s\n",
+				    cfg->settings_file);
+			return log_msg_ret("settings", ret);
+		}
+
+		ret = nhlt_format_append_config(fmt, data, size);
+		if (ret)
+			return log_msg_ret("append", ret);
+	}
+
+	return 0;
+}
+
+void nhlt_next_instance(struct nhlt *nhlt, int link_type)
+{
+	if (link_type < NHLT_LINK_HDA || link_type >= NHLT_MAX_LINK_TYPES)
+		return;
+
+	nhlt->current_instance_id[link_type]++;
+}
+
+static size_t calc_specific_config_size(struct nhlt_specific_config *cfg)
+{
+	return sizeof(cfg->size) + cfg->size;
+}
+
+static size_t calc_format_size(struct nhlt_format *fmt)
+{
+	size_t sz = 0;
+
+	/* Wave format first */
+	sz += sizeof(fmt->waveform.tag);
+	sz += sizeof(fmt->waveform.num_channels);
+	sz += sizeof(fmt->waveform.samples_per_second);
+	sz += sizeof(fmt->waveform.bytes_per_second);
+	sz += sizeof(fmt->waveform.block_align);
+	sz += sizeof(fmt->waveform.bits_per_sample);
+	sz += sizeof(fmt->waveform.extra_size);
+	sz += sizeof(fmt->waveform.valid_bits_per_sample);
+	sz += sizeof(fmt->waveform.channel_mask);
+	sz += sizeof(fmt->waveform.sub_format);
+
+	sz += calc_specific_config_size(&fmt->config);
+
+	return sz;
+}
+
+static size_t calc_endpoint_size(struct nhlt_endpoint *endp)
+{
+	int i;
+	size_t sz = 0;
+
+	sz += sizeof(endp->length) + sizeof(endp->link_type);
+	sz += sizeof(endp->instance_id) + sizeof(endp->vendor_id);
+	sz += sizeof(endp->device_id) + sizeof(endp->revision_id);
+	sz += sizeof(endp->subsystem_id) + sizeof(endp->device_type);
+	sz += sizeof(endp->direction) + sizeof(endp->virtual_bus_id);
+	sz += calc_specific_config_size(&endp->config);
+	sz += sizeof(endp->num_formats);
+
+	for (i = 0; i < endp->num_formats; i++)
+		sz += calc_format_size(&endp->formats[i]);
+
+	/* Adjust endpoint length to reflect current configuration */
+	endp->length = sz;
+
+	return sz;
+}
+
+static size_t calc_endpoints_size(struct nhlt *nhlt)
+{
+	size_t sz = 0;
+	int i;
+
+	for (i = 0; i < nhlt->num_endpoints; i++)
+		sz += calc_endpoint_size(&nhlt->endpoints[i]);
+
+	return sz;
+}
+
+static size_t calc_size(struct nhlt *nhlt)
+{
+	return sizeof(nhlt->num_endpoints) + calc_endpoints_size(nhlt);
+}
+
+size_t nhlt_current_size(struct nhlt *nhlt)
+{
+	return calc_size(nhlt) + sizeof(struct acpi_table_header);
+}
+
+static void nhlt_free_resources(struct nhlt *nhlt)
+{
+	int i, j;
+
+	/* Free all specific configs */
+	for (i = 0; i < nhlt->num_endpoints; i++) {
+		struct nhlt_endpoint *endp = &nhlt->endpoints[i];
+
+		free(endp->config.capabilities);
+		for (j = 0; j < endp->num_formats; j++) {
+			struct nhlt_format *fmt = &endp->formats[j];
+
+			free(fmt->config.capabilities);
+		}
+	}
+
+	/* Free nhlt object proper */
+	free(nhlt);
+}
+
+struct cursor {
+	u8 *buf;
+};
+
+static void ser8(struct cursor *cur, uint val)
+{
+	*cur->buf = val;
+	cur->buf += sizeof(val);
+}
+
+static void ser16(struct cursor *cur, uint val)
+{
+	put_unaligned_le16(val, cur->buf);
+	cur->buf += sizeof(val);
+}
+
+static void ser32(struct cursor *cur, uint val)
+{
+	put_unaligned_le32(val, cur->buf);
+	cur->buf += sizeof(val);
+}
+
+static void serblob(struct cursor *cur, void *from, size_t sz)
+{
+	memcpy(cur->buf, from, sz);
+	cur->buf += sz;
+}
+
+static void serialise_specific_config(struct nhlt_specific_config *cfg,
+				      struct cursor *cur)
+{
+	ser32(cur, cfg->size);
+	serblob(cur, cfg->capabilities, cfg->size);
+}
+
+static void serialise_waveform(struct nhlt_waveform *wave, struct cursor *cur)
+{
+	ser16(cur, wave->tag);
+	ser16(cur, wave->num_channels);
+	ser32(cur, wave->samples_per_second);
+	ser32(cur, wave->bytes_per_second);
+	ser16(cur, wave->block_align);
+	ser16(cur, wave->bits_per_sample);
+	ser16(cur, wave->extra_size);
+	ser16(cur, wave->valid_bits_per_sample);
+	ser32(cur, wave->channel_mask);
+	ser32(cur, wave->sub_format.data1);
+	ser16(cur, wave->sub_format.data2);
+	ser16(cur, wave->sub_format.data3);
+	serblob(cur, wave->sub_format.data4, sizeof(wave->sub_format.data4));
+}
+
+static void serialise_format(struct nhlt_format *fmt, struct cursor *cur)
+{
+	serialise_waveform(&fmt->waveform, cur);
+	serialise_specific_config(&fmt->config, cur);
+}
+
+static void serialise_endpoint(struct nhlt_endpoint *endp, struct cursor *cur)
+{
+	int i;
+
+	ser32(cur, endp->length);
+	ser8(cur, endp->link_type);
+	ser8(cur, endp->instance_id);
+	ser16(cur, endp->vendor_id);
+	ser16(cur, endp->device_id);
+	ser16(cur, endp->revision_id);
+	ser32(cur, endp->subsystem_id);
+	ser8(cur, endp->device_type);
+	ser8(cur, endp->direction);
+	ser8(cur, endp->virtual_bus_id);
+	serialise_specific_config(&endp->config, cur);
+	ser8(cur, endp->num_formats);
+
+	for (i = 0; i < endp->num_formats; i++)
+		serialise_format(&endp->formats[i], cur);
+}
+
+static void nhlt_serialise_endpoints(struct nhlt *nhlt, struct cursor *cur)
+{
+	int i;
+
+	ser8(cur, nhlt->num_endpoints);
+
+	for (i = 0; i < nhlt->num_endpoints; i++)
+		serialise_endpoint(&nhlt->endpoints[i], cur);
+}
+
+int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt,
+				 const char *oem_id, const char *oem_table_id,
+				 uint32_t oem_revision)
+{
+	struct cursor cur;
+	struct acpi_table_header *header;
+	size_t sz;
+	size_t oem_id_len;
+	size_t oem_table_id_len;
+	int ret;
+
+	log_info("ACPI:    * NHLT\n");
+	sz = nhlt_current_size(nhlt);
+
+	/* Create header */
+	header = (void *)ctx->current;
+	memset(header, '\0', sizeof(struct acpi_table_header));
+	acpi_fill_header(header, "NHLT");
+	header->length = sz;
+	header->revision = acpi_get_table_revision(ACPITAB_NHLT);
+
+	if (oem_id) {
+		oem_id_len = min((int)strlen(oem_id), 6);
+		memcpy(header->oem_id, oem_id, oem_id_len);
+	}
+	if (oem_table_id) {
+		oem_table_id_len = min((int)strlen(oem_table_id), 8);
+		memcpy(header->oem_table_id, oem_table_id, oem_table_id_len);
+	}
+	header->oem_revision = oem_revision;
+
+	cur.buf = (void *)(header + 1);
+	nhlt_serialise_endpoints(nhlt, &cur);
+
+	header->checksum = table_compute_checksum(header, sz);
+	nhlt_free_resources(nhlt);
+
+	ret = acpi_add_table(ctx, ctx->current);
+	if (ret)
+		return log_msg_ret("add", ret);
+	acpi_inc_align(ctx, sz);
+
+	return 0;
+}
+
+static int _nhlt_add_single_endpoint(struct nhlt *nhlt, int virtual_bus_id,
+				     const struct nhlt_endp_descriptor *epd)
+{
+	struct nhlt_endpoint *endp;
+	int ret;
+
+	endp = nhlt_add_endpoint(nhlt, epd->link, epd->device, epd->direction,
+				 epd->vid, epd->did);
+	if (!endp)
+		return -EINVAL;
+
+	endp->virtual_bus_id = virtual_bus_id;
+
+	ret = nhlt_endpoint_append_config(endp, epd->cfg, epd->cfg_size);
+	if (ret)
+		return ret;
+
+	ret = nhlt_endpoint_add_formats(endp, epd->formats, epd->num_formats);
+	if (ret)
+		return log_msg_ret("formats", ret);
+
+	return 0;
+}
+
+static int _nhlt_add_endpoints(struct nhlt *nhlt, int virtual_bus_id,
+			       const struct nhlt_endp_descriptor *epds,
+			       size_t num_epds)
+{
+	size_t i;
+	int ret;
+
+	for (i = 0; i < num_epds; i++) {
+		ret = _nhlt_add_single_endpoint(nhlt, virtual_bus_id, &epds[i]);
+		if (ret)
+			return log_ret(ret);
+	}
+
+	return 0;
+}
+
+int nhlt_add_endpoints(struct nhlt *nhlt,
+		       const struct nhlt_endp_descriptor *epds, size_t num_epds)
+{
+	int ret;
+
+	ret = _nhlt_add_endpoints(nhlt, DEFAULT_VIRTUAL_BUS_ID, epds, num_epds);
+
+	return ret;
+}
+
+int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id,
+			   const struct nhlt_endp_descriptor *epds,
+			   size_t num_epds)
+{
+	int ret;
+
+	ret = _nhlt_add_endpoints(nhlt, virtual_bus_id, epds, num_epds);
+	if (!ret)
+		nhlt_next_instance(nhlt, NHLT_LINK_SSP);
+
+	return ret;
+}
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 23/43] x86: Add error checking for csrt table generation

[Simon Glass]

Generation of this table can fail, so update the function to return an
error code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v1:
- Add new patch to add error checking for csrt table generation

 arch/x86/lib/acpi_table.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 27869a0e5e..b6ba547b6a 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -212,13 +212,14 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 
 __weak u32 acpi_fill_csrt(u32 current)
 {
-	return current;
+	return 0;
 }
 
-static void acpi_create_csrt(struct acpi_csrt *csrt)
+static int acpi_create_csrt(struct acpi_csrt *csrt)
 {
 	struct acpi_table_header *header = &(csrt->header);
 	u32 current = (u32)csrt + sizeof(struct acpi_csrt);
+	uint ptr;
 
 	memset((void *)csrt, 0, sizeof(struct acpi_csrt));
 
@@ -227,11 +228,16 @@ static void acpi_create_csrt(struct acpi_csrt *csrt)
 	header->length = sizeof(struct acpi_csrt);
 	header->revision = 0;
 
-	current = acpi_fill_csrt(current);
+	ptr = acpi_fill_csrt(current);
+	if (!ptr)
+		return -ENOENT;
+	current = ptr;
 
 	/* (Re)calculate length and checksum */
 	header->length = current - (u32)csrt;
 	header->checksum = table_compute_checksum((void *)csrt, header->length);
+
+	return 0;
 }
 
 static void acpi_create_spcr(struct acpi_spcr *spcr)
@@ -482,9 +488,10 @@ ulong write_acpi_tables(ulong start_addr)
 
 	debug("ACPI:    * CSRT\n");
 	csrt = ctx->current;
-	acpi_create_csrt(csrt);
-	acpi_inc_align(ctx, csrt->header.length);
-	acpi_add_table(ctx, csrt);
+	if (!acpi_create_csrt(csrt)) {
+		acpi_inc_align(ctx, csrt->header.length);
+		acpi_add_table(ctx, csrt);
+	}
 
 	debug("ACPI:    * SPCR\n");
 	spcr = ctx->current;
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 24/43] x86: apl: Use memory-mapped access for VBT

[Simon Glass]

Use the new binman memory-mapping function to access the VBT, to simplify
the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/apollolake/fsp_s.c      | 19 +++++--------------
 arch/x86/lib/fsp2/fsp_silicon_init.c |  1 +
 2 files changed, 6 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 13e6b20f08..0f5520fc7d 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -36,29 +36,20 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,
 	ofnode node;
 
 	if (IS_ENABLED(CONFIG_HAVE_VBT)) {
-		struct binman_entry vbt;
-		void *vbt_buf;
+		void *buf;
 		int ret;
 
-		ret = binman_entry_find("intel-vbt", &vbt);
+		ret = binman_entry_map(ofnode_null(), "intel-vbt", &buf, NULL);
 		if (ret)
 			return log_msg_ret("Cannot find VBT", ret);
-		vbt.image_pos += rom_offset;
-		vbt_buf = malloc(vbt.size);
-		if (!vbt_buf)
-			return log_msg_ret("Alloc VBT", -ENOMEM);
+		if (*(u32 *)buf != VBT_SIGNATURE)
+			return log_msg_ret("VBT signature", -EINVAL);
 
 		/*
 		 * Load VBT before devicetree-specific config. This only
 		 * supports memory-mapped SPI at present.
 		 */
-		bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
-		memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
-		bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
-		if (*(u32 *)vbt_buf != VBT_SIGNATURE)
-			return log_msg_ret("VBT signature", -EINVAL);
-
-		cfg->graphics_config_ptr = (ulong)vbt_buf;
+		cfg->graphics_config_ptr = (ulong)buf;
 	}
 
 	node = dev_read_subnode(dev, "fsp-s");
diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c
index 45c0c7d90b..0f221a864f 100644
--- a/arch/x86/lib/fsp2/fsp_silicon_init.c
+++ b/arch/x86/lib/fsp2/fsp_silicon_init.c
@@ -32,6 +32,7 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash)
 			     &rom_offset);
 	if (ret)
 		return log_msg_ret("locate FSP", ret);
+	binman_set_rom_offset(rom_offset);
 	gd->arch.fsp_s_hdr = hdr;
 
 	/* Copy over the default config */
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 25/43] x86: gpio: Add support for obtaining ACPI info for a GPIO

[Simon Glass]

Implement the method that converts a GPIO into the form used by ACPI, so
that GPIOs can be added to ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v1:
- Use acpi_get_path() to get device path

 drivers/gpio/intel_gpio.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c
index b4d5be97da..6a3a8c4cfa 100644
--- a/drivers/gpio/intel_gpio.c
+++ b/drivers/gpio/intel_gpio.c
@@ -12,6 +12,7 @@
 #include <pch.h>
 #include <pci.h>
 #include <syscon.h>
+#include <acpi/acpi_device.h>
 #include <asm/cpu.h>
 #include <asm/gpio.h>
 #include <asm/intel_pinctrl.h>
@@ -19,6 +20,7 @@
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/arch/gpio.h>
+#include <dm/acpi.h>
 #include <dt-bindings/gpio/x86-gpio.h>
 
 static int intel_gpio_direction_input(struct udevice *dev, uint offset)
@@ -128,6 +130,35 @@ static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(ACPIGEN)
+static int intel_gpio_get_acpi(const struct gpio_desc *desc,
+			       struct acpi_gpio *gpio)
+{
+	struct udevice *pinctrl;
+	int ret;
+
+	if (!dm_gpio_is_valid(desc))
+		return -ENOENT;
+	pinctrl = dev_get_parent(desc->dev);
+
+	memset(gpio, '\0', sizeof(*gpio));
+
+	gpio->type = ACPI_GPIO_TYPE_IO;
+	gpio->pull = ACPI_GPIO_PULL_DEFAULT;
+	gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
+	gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
+	gpio->pin_count = 1;
+	gpio->pins[0] = intel_pinctrl_get_acpi_pin(pinctrl, desc->offset);
+	gpio->pin0_addr = intel_pinctrl_get_config_reg_addr(pinctrl,
+							    desc->offset);
+	ret = acpi_get_path(pinctrl, gpio->resource, sizeof(gpio->resource));
+	if (ret)
+		return log_msg_ret("resource", ret);
+
+	return 0;
+}
+#endif
+
 static int intel_gpio_probe(struct udevice *dev)
 {
 	return 0;
@@ -152,6 +183,9 @@ static const struct dm_gpio_ops gpio_intel_ops = {
 	.set_value		= intel_gpio_set_value,
 	.get_function		= intel_gpio_get_function,
 	.xlate			= intel_gpio_xlate,
+#if CONFIG_IS_ENABLED(ACPIGEN)
+	.get_acpi		= intel_gpio_get_acpi,
+#endif
 };
 
 static const struct udevice_id intel_intel_gpio_ids[] = {
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 26/43] i2c: designware_i2c: Add a little more debugging

[Simon Glass]

Add debugging for a few more values and also use log to show return values
when something goes wrong. This makes it easier to see the root cause.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v1:
- Add new patch to improve designware_i2c debugging

 drivers/i2c/designware_i2c.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 3616e2105f..44a1f33398 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -160,9 +160,9 @@ static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 	min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 	min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 
-	debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
-	      period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
-	      spk_cnt);
+	debug("dw_i2c: mode %d, ic_clk %d, speed %d, period %d rise %d fall %d tlow %d thigh %d spk %d\n",
+	      mode, ic_clk, info->speed, period_cnt, rise_cnt, fall_cnt,
+	      min_tlow_cnt, min_thigh_cnt, spk_cnt);
 
 	/*
 	 * Back-solve for hcnt and lcnt according to the following equations:
@@ -174,7 +174,7 @@ static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 
 	if (hcnt < 0 || lcnt < 0) {
 		debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
-		return -EINVAL;
+		return log_msg_ret("counts", -EINVAL);
 	}
 
 	/*
@@ -713,7 +713,7 @@ static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 #if CONFIG_IS_ENABLED(CLK)
 	rate = clk_get_rate(&i2c->clk);
 	if (IS_ERR_VALUE(rate))
-		return -EINVAL;
+		return log_ret(-EINVAL);
 #else
 	rate = IC_CLK;
 #endif
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 27/43] i2c: Add log_ret() on error

[Simon Glass]

Add a few of these calls to make it easier to see where an error occurs,
if CONFIG_LOG_ERROR_RETURN is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/i2c/i2c-uclass.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 8bc69e870f..2373aa2ea4 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -458,7 +458,7 @@ int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len)
 	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
 
 	if (offset_len > I2C_MAX_OFFSET_LEN)
-		return -EINVAL;
+		return log_ret(-EINVAL);
 	chip->offset_len = offset_len;
 
 	return 0;
@@ -625,7 +625,7 @@ int i2c_chip_ofdata_to_platdata(struct udevice *dev, struct dm_i2c_chip *chip)
 	if (addr == -1) {
 		debug("%s: I2C Node '%s' has no 'reg' property %s\n", __func__,
 		      dev_read_name(dev), dev->name);
-		return -EINVAL;
+		return log_ret(-EINVAL);
 	}
 	chip->chip_addr = addr;
 
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 28/43] i2c: designware_i2c: Support ACPI table generation

[Simon Glass]

Update the PCI driver to generate ACPI information so that Linux has the
full information about each I2C bus.

Signed-off-by: Simon Glass <sjg@chromium.org>

---

Changes in v1:
- Capitalise ACPI_OPS_PTR

 drivers/i2c/designware_i2c.c     |  25 ++++++++
 drivers/i2c/designware_i2c.h     |  15 +++++
 drivers/i2c/designware_i2c_pci.c | 104 ++++++++++++++++++++++++++++++-
 3 files changed, 143 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 44a1f33398..630938743f 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -333,6 +333,31 @@ static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
 	/* Restore back i2c now speed set */
 	if (ena == IC_ENABLE_0B)
 		dw_i2c_enable(i2c_base, true);
+	if (priv)
+		priv->config = config;
+	return 0;
+}
+
+int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
+			    struct dw_i2c_speed_config *config)
+{
+	struct dw_i2c *priv = dev_get_priv(dev);
+	ulong rate;
+	int ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+	rate = clk_get_rate(&priv->clk);
+	if (IS_ERR_VALUE(rate))
+		return log_msg_ret("clk", -EINVAL);
+#else
+	rate = IC_CLK;
+#endif
+
+	ret = calc_bus_speed(priv, priv->regs, speed_hz, rate, config);
+	if (ret)
+		printf("%s: ret=%d\n", __func__, ret);
+	if (ret)
+		return log_msg_ret("calc_bus_speed", ret);
 
 	return 0;
 }
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index dc9a6ccb63..d87a3bff93 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -205,6 +205,7 @@ struct dw_i2c {
 #if CONFIG_IS_ENABLED(CLK)
 	struct clk clk;
 #endif
+	struct dw_i2c_speed_config config;
 };
 
 extern const struct dm_i2c_ops designware_i2c_ops;
@@ -213,4 +214,18 @@ int designware_i2c_probe(struct udevice *bus);
 int designware_i2c_remove(struct udevice *dev);
 int designware_i2c_ofdata_to_platdata(struct udevice *bus);
 
+/**
+ * dw_i2c_gen_speed_config() - Calculate config info from requested speed1
+ *
+ * Calculate the speed config from the given @speed_hz and return it so that
+ * it can be incorporated in ACPI tables
+ *
+ * @dev: I2C bus to check
+ * @speed_hz: Requested speed in Hz
+ * @config: Returns config to use for that speed
+ * @return 0 if OK, -ve on error
+ */
+int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
+			    struct dw_i2c_speed_config *config);
+
 #endif /* __DW_I2C_H_ */
diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
index bd34ec0b47..d5108e9064 100644
--- a/drivers/i2c/designware_i2c_pci.c
+++ b/drivers/i2c/designware_i2c_pci.c
@@ -9,7 +9,12 @@
 #include <dm.h>
 #include <log.h>
 #include <spl.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
 #include <asm/lpss.h>
+#include <dm/acpi.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
 #include "designware_i2c.h"
 
 enum {
@@ -87,6 +92,8 @@ static int designware_i2c_pci_bind(struct udevice *dev)
 {
 	char name[20];
 
+	if (dev_of_valid(dev))
+		return 0;
 	/*
 	 * Create a unique device name for PCI type devices
 	 * ToDo:
@@ -100,13 +107,107 @@ static int designware_i2c_pci_bind(struct udevice *dev)
 	 * be possible. We cannot use static data in drivers since they may be
 	 * used in SPL or before relocation.
 	 */
-	dev->req_seq = gd->arch.dw_i2c_num_cards++;
+	dev->req_seq = uclass_find_next_free_req_seq(UCLASS_I2C);
 	sprintf(name, "i2c_designware#%u", dev->req_seq);
 	device_set_name(dev, name);
 
 	return 0;
 }
 
+/*
+ * Write ACPI object to describe speed configuration.
+ *
+ * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
+ *
+ * SSCN: I2C_SPEED_STANDARD
+ * FMCN: I2C_SPEED_FAST
+ * FPCN: I2C_SPEED_FAST_PLUS
+ * HSCN: I2C_SPEED_HIGH
+ */
+static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
+					   struct dw_i2c_speed_config *config)
+{
+	switch (config->speed_mode) {
+	case IC_SPEED_MODE_HIGH:
+		acpigen_write_name(ctx, "HSCN");
+		break;
+	case IC_SPEED_MODE_FAST_PLUS:
+		acpigen_write_name(ctx, "FPCN");
+		break;
+	case IC_SPEED_MODE_FAST:
+		acpigen_write_name(ctx, "FMCN");
+		break;
+	case IC_SPEED_MODE_STANDARD:
+	default:
+		acpigen_write_name(ctx, "SSCN");
+	}
+
+	/* Package () { scl_lcnt, scl_hcnt, sda_hold } */
+	acpigen_write_package(ctx, 3);
+	acpigen_write_word(ctx, config->scl_hcnt);
+	acpigen_write_word(ctx, config->scl_lcnt);
+	acpigen_write_dword(ctx, config->sda_hold);
+	acpigen_pop_len(ctx);
+}
+
+/*
+ * Generate I2C timing information into the SSDT for the OS driver to consume,
+ * optionally applying override values provided by the caller.
+ */
+static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
+				 struct acpi_ctx *ctx)
+{
+	struct dw_i2c_speed_config config;
+	char path[ACPI_PATH_MAX];
+	u32 speeds[4];
+	int size, i;
+	int ret;
+
+	/* If no device-tree node, ignore this since we assume it isn't used */
+	if (!dev_of_valid(dev))
+		return 0;
+	ret = acpi_device_path(dev, path, sizeof(path));
+	if (ret)
+		return log_msg_ret("path", ret);
+
+	size = dev_read_size(dev, "i2c,speeds");
+	if (size < 0)
+		return log_msg_ret("i2c,speeds", -EINVAL);
+	size /= sizeof(u32);
+	if (size > ARRAY_SIZE(speeds))
+		return log_msg_ret("array", -E2BIG);
+
+	ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size);
+	if (ret)
+		return log_msg_ret("read", -E2BIG);
+
+	if (0) {
+		acpigen_write_scope(ctx, path);
+		for (i = 0; i < size; i++) {
+			ret = dw_i2c_gen_speed_config(dev, speeds[i], &config);
+			if (ret)
+				return log_msg_ret("config", ret);
+			dw_i2c_acpi_write_speed_config(ctx, &config);
+		}
+	} else {
+		uint speed;
+
+		speed = dev_read_u32_default(dev, "clock-frequency", 100000);
+		acpigen_write_scope(ctx, path);
+		ret = dw_i2c_gen_speed_config(dev, speed, &config);
+		if (ret)
+			return log_msg_ret("config", ret);
+		dw_i2c_acpi_write_speed_config(ctx, &config);
+	}
+	acpigen_pop_len(ctx);
+
+	return 0;
+}
+
+struct acpi_ops dw_i2c_acpi_ops = {
+	.fill_ssdt	= dw_i2c_acpi_fill_ssdt,
+};
+
 static const struct udevice_id designware_i2c_pci_ids[] = {
 	{ .compatible = "snps,designware-i2c-pci" },
 	{ .compatible = "intel,apl-i2c", .data = INTEL_APL },
@@ -124,6 +225,7 @@ U_BOOT_DRIVER(i2c_designware_pci) = {
 	.remove = designware_i2c_remove,
 	.flags = DM_FLAG_OS_PREPARE,
 	.ops	= &designware_i2c_ops,
+	ACPI_OPS_PTR(&dw_i2c_acpi_ops)
 };
 
 static struct pci_device_id designware_pci_supported[] = {
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 29/43] p2sb: Add a method to hide the bus

[Simon Glass]

The P2SB bus needs to be hidden in some cases so that it does not get
auto-configured by Linux. Add a method for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/misc/p2sb-uclass.c | 10 ++++++++++
 include/p2sb.h             | 25 ++++++++++++++++++++++++-
 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c
index d5fe12ebd8..b5219df46b 100644
--- a/drivers/misc/p2sb-uclass.c
+++ b/drivers/misc/p2sb-uclass.c
@@ -18,6 +18,16 @@
 
 #define PCR_COMMON_IOSF_1_0	1
 
+int p2sb_set_hide(struct udevice *dev, bool hide)
+{
+	struct p2sb_ops *ops = p2sb_get_ops(dev);
+
+	if (!ops->set_hide)
+		return -ENOSYS;
+
+	return ops->set_hide(dev, hide);
+}
+
 void *pcr_reg_address(struct udevice *dev, uint offset)
 {
 	struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
diff --git a/include/p2sb.h b/include/p2sb.h
index 74eb08b7ff..93e1155dca 100644
--- a/include/p2sb.h
+++ b/include/p2sb.h
@@ -31,13 +31,36 @@ struct p2sb_uc_priv {
 };
 
 /**
- * struct p2sb_ops - Operations for the P2SB (none at present)
+ * struct p2sb_ops - Operations for the P2SB
  */
 struct p2sb_ops {
+	/**
+	 * set_hide() - Set/clear the 'hide' bit on the p2sb
+	 *
+	 * This device can be hidden from the PCI bus if needed. This method
+	 * can be called before the p2sb is probed.
+	 *
+	 * @dev: P2SB device
+	 * @hide: true to hide the device, false to show it
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_hide)(struct udevice *dev, bool hide);
 };
 
 #define p2sb_get_ops(dev)        ((struct p2sb_ops *)(dev)->driver->ops)
 
+/**
+ * p2sb_set_hide() - Set/clear the 'hide' bit on the p2sb
+ *
+ * This device can be hidden from the PCI bus if needed. This method
+ * can be called before the p2sb is probed.
+ *
+ * @dev: P2SB device
+ * @hide: true to hide the device, false to show it
+ * @return 0 if OK, -ve on error
+ */
+int p2sb_set_hide(struct udevice *dev, bool hide);
+
 /**
  * pcr_read32/16/8() - Read from a PCR device
  *
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 30/43] x86: apl: Support set_hide() in p2sb driver

[Simon Glass]

Add support for this new method in the driver and in the fsp-s setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/apollolake/fsp_s.c  | 26 +++++++++++---------------
 arch/x86/cpu/intel_common/p2sb.c | 30 ++++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 0f5520fc7d..3a54297a28 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -12,6 +12,7 @@
 #include <irq.h>
 #include <log.h>
 #include <malloc.h>
+#include <p2sb.h>
 #include <acpi/acpi_s3.h>
 #include <asm/intel_pinctrl.h>
 #include <asm/io.h>
@@ -21,10 +22,11 @@
 #include <asm/pci.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/systemagent.h>
+#include <asm/arch/fsp_bindings.h>
 #include <asm/arch/fsp/fsp_configs.h>
 #include <asm/arch/fsp/fsp_s_upd.h>
+#include <dm/uclass-internal.h>
 #include <linux/bitops.h>
-#include <asm/arch/fsp_bindings.h>
 
 #define PCH_P2SB_E0		0xe0
 #define HIDE_BIT		BIT(0)
@@ -59,12 +61,6 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,
 	return fsp_s_update_config_from_dtb(node, cfg);
 }
 
-static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
-{
-	pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
-			      hide ? HIDE_BIT : 0, PCI_SIZE_8);
-}
-
 /* Configure package power limits */
 static int set_power_limits(struct udevice *dev)
 {
@@ -137,15 +133,15 @@ static int set_power_limits(struct udevice *dev)
 
 int p2sb_unhide(void)
 {
-	pci_dev_t dev = PCI_BDF(0, 0xd, 0);
-	ulong val;
-
-	p2sb_set_hide_bit(dev, 0);
-
-	pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
+	struct udevice *dev;
+	int ret;
 
-	if (val != PCI_VENDOR_ID_INTEL)
-		return log_msg_ret("p2sb unhide", -EIO);
+	ret = uclass_find_first_device(UCLASS_P2SB, &dev);
+	if (ret)
+		return log_msg_ret("p2sb", ret);
+	ret = p2sb_set_hide(dev, false);
+	if (ret)
+		return log_msg_ret("hide", ret);
 
 	return 0;
 }
diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c
index ec35d04ae5..ebf8f62aea 100644
--- a/arch/x86/cpu/intel_common/p2sb.c
+++ b/arch/x86/cpu/intel_common/p2sb.c
@@ -16,6 +16,9 @@
 #include <asm/pci.h>
 #include <linux/bitops.h>
 
+#define PCH_P2SB_E0		0xe0
+#define HIDE_BIT		BIT(0)
+
 struct p2sb_platdata {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct dtd_intel_p2sb dtplat;
@@ -127,6 +130,29 @@ static int p2sb_probe(struct udevice *dev)
 	return 0;
 }
 
+static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
+{
+	dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
+			      hide ? HIDE_BIT : 0);
+}
+
+static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
+{
+	u16 vendor;
+
+	if (!CONFIG_IS_ENABLED(PCI))
+		return -EPERM;
+	p2sb_set_hide_bit(dev, hide);
+
+	dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
+	if (hide && vendor != 0xffff)
+		return log_msg_ret("hide", -EEXIST);
+	else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
+		return log_msg_ret("unhide", -ENOMEDIUM);
+
+	return 0;
+}
+
 static int p2sb_child_post_bind(struct udevice *dev)
 {
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
@@ -143,6 +169,10 @@ static int p2sb_child_post_bind(struct udevice *dev)
 	return 0;
 }
 
+struct p2sb_ops p2sb_ops = {
+	.set_hide	= intel_p2sb_set_hide,
+};
+
 static const struct udevice_id p2sb_ids[] = {
 	{ .compatible = "intel,p2sb" },
 	{ }
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 31/43] x86: apl: Hide the p2sb on exit from U-Boot

[Simon Glass]

This confuses Linux's PCI probing so needs to be hidden when booting
Linux. Add a remove() method to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/intel_common/p2sb.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c
index ebf8f62aea..361d4c90cb 100644
--- a/arch/x86/cpu/intel_common/p2sb.c
+++ b/arch/x86/cpu/intel_common/p2sb.c
@@ -153,6 +153,17 @@ static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
 	return 0;
 }
 
+static int p2sb_remove(struct udevice *dev)
+{
+	int ret;
+
+	ret = intel_p2sb_set_hide(dev, true);
+	if (ret)
+		return log_msg_ret("hide", ret);
+
+	return 0;
+}
+
 static int p2sb_child_post_bind(struct udevice *dev)
 {
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
@@ -183,9 +194,12 @@ U_BOOT_DRIVER(p2sb_drv) = {
 	.id		= UCLASS_P2SB,
 	.of_match	= p2sb_ids,
 	.probe		= p2sb_probe,
+	.remove		= p2sb_remove,
+	.ops		= &p2sb_ops,
 	.ofdata_to_platdata = p2sb_ofdata_to_platdata,
 	.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
 	.per_child_platdata_auto_alloc_size =
 		sizeof(struct p2sb_child_platdata),
 	.child_post_bind = p2sb_child_post_bind,
+	.flags		= DM_FLAG_OS_PREPARE,
 };
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 32/43] pmc: Move common registers to the header file

[Simon Glass]

These registers need to be accesses from ACPI code, so move them to the
header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/power/acpi_pmc/acpi-pmc-uclass.c |  9 ---------
 include/power/acpi_pmc.h                 | 14 ++++++++++++++
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/power/acpi_pmc/acpi-pmc-uclass.c b/drivers/power/acpi_pmc/acpi-pmc-uclass.c
index 1c79f835c6..828963d8a0 100644
--- a/drivers/power/acpi_pmc/acpi-pmc-uclass.c
+++ b/drivers/power/acpi_pmc/acpi-pmc-uclass.c
@@ -15,15 +15,6 @@
 #include <asm/io.h>
 #include <power/acpi_pmc.h>
 
-enum {
-	PM1_STS		= 0x00,
-	PM1_EN		= 0x02,
-	PM1_CNT		= 0x04,
-
-	GPE0_STS	= 0x20,
-	GPE0_EN		= 0x30,
-};
-
 struct tco_regs {
 	u32 tco_rld;
 	u32 tco_sts;
diff --git a/include/power/acpi_pmc.h b/include/power/acpi_pmc.h
index 1f50c23f5f..5fbf745136 100644
--- a/include/power/acpi_pmc.h
+++ b/include/power/acpi_pmc.h
@@ -6,10 +6,22 @@
 #ifndef __ACPI_PMC_H
 #define __ACPI_PMC_H
 
+#ifndef __ACPI__
+
 enum {
 	GPE0_REG_MAX	= 4,
 };
 
+enum {
+	PM1_STS		= 0x00,
+	PM1_EN		= 0x02,
+	PM1_CNT		= 0x04,
+	PM1_TMR		= 0x08,
+
+	GPE0_STS	= 0x20,
+	GPE0_EN		= 0x30,
+};
+
 /**
  * struct acpi_pmc_upriv - holds common data for the x86 PMC
  *
@@ -182,4 +194,6 @@ void pmc_dump_info(struct udevice *dev);
  */
 int pmc_gpe_init(struct udevice *dev);
 
+#endif /* !__ACPI__ */
+
 #endif
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 33/43] x86: irq: Support flags for acpi_gpe

[Simon Glass]

This binding currently has a flags cell but it is not used. Make use of it
to create ACPI tables for interrupts.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/acpi_gpe.c                       | 26 +++++++++++++++++++
 .../interrupt-controller/x86-irq.h            | 14 ++++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 include/dt-bindings/interrupt-controller/x86-irq.h

diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c
index 8aa2009bd6..70badb15a3 100644
--- a/arch/x86/cpu/acpi_gpe.c
+++ b/arch/x86/cpu/acpi_gpe.c
@@ -8,7 +8,10 @@
 #include <dm.h>
 #include <irq.h>
 #include <log.h>
+#include <acpi/acpi_device.h>
 #include <asm/io.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/x86-irq.h>
 
 /**
  * struct acpi_gpe_priv - private driver information
@@ -62,13 +65,36 @@ static int acpi_gpe_ofdata_to_platdata(struct udevice *dev)
 static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
 {
 	irq->id = args->args[0];
+	irq->flags = args->args[1];
 
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(ACPIGEN)
+static int acpi_gpe_get_acpi(const struct irq *irq, struct acpi_irq *acpi_irq)
+{
+	memset(acpi_irq, '\0', sizeof(*acpi_irq));
+	acpi_irq->pin = irq->id;
+	acpi_irq->mode = irq->flags & IRQ_TYPE_EDGE_BOTH ?
+		ACPI_IRQ_EDGE_TRIGGERED : ACPI_IRQ_LEVEL_TRIGGERED;
+	acpi_irq->polarity = irq->flags &
+		 (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW) ?
+		 ACPI_IRQ_ACTIVE_LOW : ACPI_IRQ_ACTIVE_HIGH;
+	acpi_irq->shared = irq->flags & X86_IRQ_TYPE_SHARED ?
+		ACPI_IRQ_SHARED : ACPI_IRQ_EXCLUSIVE;
+	acpi_irq->wake = irq->flags & X86_IRQ_TYPE_WAKE ? ACPI_IRQ_WAKE :
+		ACPI_IRQ_NO_WAKE;
+
+	return 0;
+}
+#endif
+
 static const struct irq_ops acpi_gpe_ops = {
 	.read_and_clear		= acpi_gpe_read_and_clear,
 	.of_xlate		= acpi_gpe_of_xlate,
+#if CONFIG_IS_ENABLED(ACPIGEN)
+	.get_acpi		= acpi_gpe_get_acpi,
+#endif
 };
 
 static const struct udevice_id acpi_gpe_ids[] = {
diff --git a/include/dt-bindings/interrupt-controller/x86-irq.h b/include/dt-bindings/interrupt-controller/x86-irq.h
new file mode 100644
index 0000000000..9e0b4612e1
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/x86-irq.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ *
+ * This provides additional flags used by x86.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H
+
+#define X86_IRQ_TYPE_SHARED	(1 << 4)
+#define X86_IRQ_TYPE_WAKE	(1 << 5)
+
+#endif
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 34/43] x86: apl: Fix save/restore of ITSS priorities

[Simon Glass]

The FSP-S changes the ITSS priorities. The code that tries to save it
before running FSP-S and restore it afterwards does not work as U-Boot
relocates in between the save and restore. This means that the driver
data saved before relocation is lost and the new driver just sees zeroes.

Fix this by allocating space in the relocated memory for the ITSS data.
Save it there and access it from the driver after relocation.

This fixes interrupt handling on coral.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/apollolake/fsp_s.c    | 11 +++++------
 arch/x86/cpu/cpu.c                 | 13 +++++++++++++
 arch/x86/cpu/intel_common/itss.c   | 25 +++++++++++++++++++++++--
 arch/x86/include/asm/global_data.h |  1 +
 arch/x86/include/asm/itss.h        |  2 +-
 drivers/misc/irq-uclass.c          |  2 +-
 6 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 3a54297a28..e54b0ac104 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -160,11 +160,6 @@ int arch_fsps_preinit(void)
 	ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
 	if (ret)
 		return log_msg_ret("no itss", ret);
-	/*
-	 * Snapshot the current GPIO IRQ polarities. FSP is setting a default
-	 * policy that doesn't honour boards' requirements
-	 */
-	irq_snapshot_polarities(itss);
 
 	/*
 	 * Clear the GPI interrupt status and enable registers. These
@@ -203,7 +198,11 @@ int arch_fsp_init_r(void)
 	ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
 	if (ret)
 		return log_msg_ret("no itss", ret);
-	/* Restore GPIO IRQ polarities back to previous settings */
+
+	/*
+	 * Restore GPIO IRQ polarities back to previous settings. This was
+	 * stored in reserve_arch() - see X86_IRQT_ITSS
+	 */
 	irq_restore_polarities(itss);
 
 	/* soc_init() */
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index baa7dae172..9bc243ebc8 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -25,6 +25,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <init.h>
+#include <irq.h>
 #include <log.h>
 #include <malloc.h>
 #include <syscon.h>
@@ -274,6 +275,9 @@ int cpu_init_r(void)
 #ifndef CONFIG_EFI_STUB
 int reserve_arch(void)
 {
+	struct udevice *itss;
+	int ret;
+
 	if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
 		mrccache_reserve();
 
@@ -291,6 +295,15 @@ int reserve_arch(void)
 			fsp_save_s3_stack();
 		}
 	}
+	ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
+	if (!ret) {
+		/*
+		 * Snapshot the current GPIO IRQ polarities. FSP-S is about to
+		 * run and will set a default policy that doesn't honour boards'
+		 * requirements
+		 */
+		irq_snapshot_polarities(itss);
+	}
 
 	return 0;
 }
diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c
index 963afa8f5b..fe84ebe29f 100644
--- a/arch/x86/cpu/intel_common/itss.c
+++ b/arch/x86/cpu/intel_common/itss.c
@@ -65,14 +65,23 @@ static int snapshot_polarities(struct udevice *dev)
 	int i;
 
 	reg_start = start / IRQS_PER_IPC;
-	reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
+	reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
 
+	log_info("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot);
 	for (i = reg_start; i < reg_end; i++) {
 		uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
 
 		priv->irq_snapshot[i] = pcr_read32(dev, reg);
+		log_debug("   - %d, reg %x: irq_snapshot[i] %x\n", i, reg,
+			  priv->irq_snapshot[i]);
 	}
 
+	/* Save the snapshot for use after relocation */
+	gd->start_addr_sp -= sizeof(*priv);
+	gd->start_addr_sp &= ~0xf;
+	gd->arch.itss_priv = (void *)gd->start_addr_sp;
+	memcpy(gd->arch.itss_priv, priv, sizeof(*priv));
+
 	return 0;
 }
 
@@ -91,16 +100,26 @@ static void show_polarities(struct udevice *dev, const char *msg)
 static int restore_polarities(struct udevice *dev)
 {
 	struct itss_priv *priv = dev_get_priv(dev);
+	struct itss_priv *old_priv;
 	const int start = GPIO_IRQ_START;
 	const int end = GPIO_IRQ_END;
 	int reg_start;
 	int reg_end;
 	int i;
 
+	/* Get the snapshot which was stored by the pre-reloc device */
+	old_priv = gd->arch.itss_priv;
+	if (!old_priv)
+		return log_msg_ret("priv", -EFAULT);
+	memcpy(priv->irq_snapshot, old_priv->irq_snapshot,
+	       sizeof(priv->irq_snapshot));
+
 	show_polarities(dev, "Before");
+	log_info("priv->irq_snapshot %p\n", priv->irq_snapshot);
 
 	reg_start = start / IRQS_PER_IPC;
-	reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
+	reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
+
 
 	for (i = reg_start; i < reg_end; i++) {
 		u32 mask;
@@ -125,6 +144,8 @@ static int restore_polarities(struct udevice *dev)
 		mask &= ~((1U << irq_start) - 1);
 
 		reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
+		log_debug("   - %d, reg %x: mask %x, irq_snapshot[i] %x\n",
+			  i, reg, mask, priv->irq_snapshot[i]);
 		pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
 	}
 
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 0e64c8a46d..5bc251c0dd 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -121,6 +121,7 @@ struct arch_global_data {
 #ifdef CONFIG_FSP_VERSION2
 	struct fsp_header *fsp_s_hdr;	/* Pointer to FSP-S header */
 #endif
+	void *itss_priv;		/* Private ITSS data pointer */
 	ulong acpi_start;		/* Start address of ACPI tables */
 };
 
diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h
index c75d8fe8c2..f7d3240384 100644
--- a/arch/x86/include/asm/itss.h
+++ b/arch/x86/include/asm/itss.h
@@ -16,7 +16,7 @@
 
 #define ITSS_MAX_IRQ	119
 #define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC)
+#define NUM_IPC_REGS	DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC)
 
 /* Max PXRC registers in ITSS */
 #define MAX_PXRC_CONFIG	(PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
index 98bc79eaba..6b32b451a6 100644
--- a/drivers/misc/irq-uclass.c
+++ b/drivers/misc/irq-uclass.c
@@ -170,7 +170,7 @@ int irq_first_device_type(enum irq_dev_t type, struct udevice **devp)
 
 	ret = uclass_first_device_drvdata(UCLASS_IRQ, type, devp);
 	if (ret)
-		return log_msg_ret("find", ret);
+		return ret;
 
 	return 0;
 }
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 35/43] x86: Add debugging to table writing

[Simon Glass]

Writing tables is currently pretty opaque. Add a bit of debugging to the
process so we can see what tables are written and where they start/end in
memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/lib/tables.c | 38 ++++++++++++++++++++++++++++----------
 1 file changed, 28 insertions(+), 10 deletions(-)

diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 574d331d76..7bad5dd303 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <log.h>
 #include <malloc.h>
 #include <smbios.h>
 #include <acpi/acpi_table.h>
@@ -20,21 +21,32 @@
  */
 typedef ulong (*table_write)(ulong addr);
 
-static table_write table_write_funcs[] = {
+/**
+ * struct table_info - Information about each table to write
+ *
+ * @name: Name of table (for debugging)
+ * @write: Function to call to write this table
+ */
+struct table_info {
+	const char *name;
+	table_write write;
+};
+
+static struct table_info table_list[] = {
 #ifdef CONFIG_GENERATE_PIRQ_TABLE
-	write_pirq_routing_table,
+	{ "pirq", write_pirq_routing_table },
 #endif
 #ifdef CONFIG_GENERATE_SFI_TABLE
-	write_sfi_table,
+	{ "sfi", write_sfi_table, },
 #endif
 #ifdef CONFIG_GENERATE_MP_TABLE
-	write_mp_table,
+	{ "mp", write_mp_table, },
 #endif
 #ifdef CONFIG_GENERATE_ACPI_TABLE
-	write_acpi_tables,
+	{ "acpi", write_acpi_tables, },
 #endif
 #ifdef CONFIG_GENERATE_SMBIOS_TABLE
-	write_smbios_table,
+	{ "smbios", write_smbios_table, },
 #endif
 };
 
@@ -58,19 +70,22 @@ void write_tables(void)
 	u32 rom_table_end;
 #ifdef CONFIG_SEABIOS
 	u32 high_table, table_size;
-	struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1];
+	struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1];
 #endif
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) {
-		rom_table_end = table_write_funcs[i](rom_table_start);
+	debug("Writing tables to %x:\n", rom_table_start);
+	for (i = 0; i < ARRAY_SIZE(table_list); i++) {
+		const struct table_info *table = &table_list[i];
+
+		rom_table_end = table->write(rom_table_start);
 		rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN);
 
 #ifdef CONFIG_SEABIOS
 		table_size = rom_table_end - rom_table_start;
 		high_table = (u32)high_table_malloc(table_size);
 		if (high_table) {
-			table_write_funcs[i](high_table);
+			table->write(high_table);
 
 			cfg_tables[i].start = high_table;
 			cfg_tables[i].size = table_size;
@@ -79,6 +94,8 @@ void write_tables(void)
 		}
 #endif
 
+		debug("- wrote '%s' to %x, end %x\n", table->name,
+		      rom_table_start, rom_table_end);
 		rom_table_start = rom_table_end;
 	}
 
@@ -87,4 +104,5 @@ void write_tables(void)
 	cfg_tables[i].size = 0;
 	write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
 #endif
+	debug("- done writing tables\n");
 }
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 36/43] x86: apl: Adjust FSP-M code to avoid hard-coded address

[Simon Glass]

Update this code to calculate the address to use, rather than hard-coding
it. Obtain the requested stack size from the FSP.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/apollolake/fsp_m.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c
index 65461d85b8..cef937573b 100644
--- a/arch/x86/cpu/apollolake/fsp_m.c
+++ b/arch/x86/cpu/apollolake/fsp_m.c
@@ -24,9 +24,11 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
 	cache_ret = prepare_mrc_cache(upd);
 	if (cache_ret && cache_ret != -ENOENT)
 		return log_msg_ret("mrc", cache_ret);
-	arch->stack_base = (void *)0xfef96000;
+	arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE -
+		 arch->stack_size);
 	arch->boot_loader_tolum_size = 0;
-	arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION;
+	arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION :
+		FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
 
 	node = dev_ofnode(dev);
 	if (!ofnode_valid(node))
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 37/43] x86: Store the coreboot table address in global_data

[Simon Glass]

At present this information is used to locate and parse the tables but is
not stored. Store it so that we can display it to the user, e.g. with the
'bdinfo' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/coreboot/tables.c     | 8 +++++++-
 arch/x86/cpu/i386/cpu.c            | 7 ++++++-
 arch/x86/include/asm/global_data.h | 1 +
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index a5d31d1dea..1594b4a8b2 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -10,6 +10,8 @@
 #include <net.h>
 #include <asm/arch/sysinfo.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * This needs to be in the .data section so that it's copied over during
  * relocation. By default it's put in the .bss section which is simply filled
@@ -243,6 +245,10 @@ int get_coreboot_info(struct sysinfo_t *info)
 	if (addr < 0)
 		return addr;
 	ret = cb_parse_header((void *)addr, 0x1000, info);
+	if (!ret)
+		return -ENOENT;
+	gd->arch.coreboot_table = addr;
+	gd->flags |= GD_FLG_SKIP_LL_INIT;
 
-	return ret == 1 ? 0 : -ENOENT;
+	return 0;
 }
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index fca3f79b69..8f342dd06e 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -456,10 +456,15 @@ int x86_cpu_init_f(void)
 
 int x86_cpu_reinit_f(void)
 {
+	long addr;
+
 	setup_identity();
 	setup_pci_ram_top();
-	if (locate_coreboot_table() >= 0)
+	addr = locate_coreboot_table();
+	if (addr >= 0) {
+		gd->arch.coreboot_table = addr;
 		gd->flags |= GD_FLG_SKIP_LL_INIT;
+	}
 
 	return 0;
 }
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 5bc251c0dd..3e4044593c 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -123,6 +123,7 @@ struct arch_global_data {
 #endif
 	void *itss_priv;		/* Private ITSS data pointer */
 	ulong acpi_start;		/* Start address of ACPI tables */
+	ulong coreboot_table;		/* Address of coreboot table */
 };
 
 #endif
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 38/43] x86: mp: Allow use of mp_run_on_cpus() without MP

[Simon Glass]

At present if MP is not enabled (e.g. booting from coreboot) the 'mtrr'
command does not work correctly. It is not easy to make it work for all
CPUs, since coreboot has halted them and we would need to start them up
again, but it is easy enough to make them work on the boot CPU.

Update the code to avoid assuming that the MP init routine has completed,
so that this can work.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/mp_init.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index ef33a38017..c0ae24686e 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -454,7 +454,7 @@ static int get_bsp(struct udevice **devp, int *cpu_countp)
 	if (cpu_countp)
 		*cpu_countp = ret;
 
-	return dev->req_seq;
+	return dev->req_seq >= 0 ? dev->req_seq : 0;
 }
 
 static struct mp_callback *read_callback(struct mp_callback **slot)
@@ -589,9 +589,6 @@ int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg)
 	int num_cpus;
 	int ret;
 
-	if (!(gd->flags & GD_FLG_SMP_INIT))
-		return -ENXIO;
-
 	ret = get_bsp(&dev, &num_cpus);
 	if (ret < 0)
 		return log_msg_ret("bsp", ret);
@@ -601,6 +598,13 @@ int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg)
 		func(arg);
 	}
 
+	if (!(gd->flags & GD_FLG_SMP_INIT)) {
+		/* Allow use of this function on the BSP only */
+		if (cpu_select == MP_SELECT_BSP || !cpu_select)
+			return 0;
+		return -ENXIO;
+	}
+
 	/* Allow up to 1 second for all APs to finish */
 	ret = run_ap_work(&lcb, dev, num_cpus, 1000 /* ms */);
 	if (ret)
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 39/43] x86: Update the comment about booting for FSP2

[Simon Glass]

The comment here applies only to FSP1, so update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/start.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 01524635e9..4ad515ce08 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -124,6 +124,7 @@ car_init_ret:
 #endif
 #else
 	/*
+	 * Instructions for FSP1, but not FSP2:
 	 * U-Boot enters here twice. For the first time it comes from
 	 * car_init_done() with esp points to a temporary stack and esi
 	 * set to zero. For the second time it comes from fsp_init_done()
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 40/43] x86: Drop setup_pcat_compatibility()

[Simon Glass]

This function does not exist anymore. Drop it from the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/u-boot-x86.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index bd3f44014c..d732661f6d 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -83,8 +83,6 @@ int default_print_cpuinfo(void);
 /* Set up a UART which can be used with printch(), printhex8(), etc. */
 int setup_internal_uart(int enable);
 
-void setup_pcat_compatibility(void);
-
 void isa_unmap_rom(u32 addr);
 u32 isa_map_rom(u32 bus_addr, int size);
 
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 41/43] x86: acpi: Correct the version of the MADT

[Simon Glass]

Currently U-Boot implements version 2 but reports version 4. Correct it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/lib/acpi_table.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index b6ba547b6a..6e3276c6f6 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -155,7 +155,7 @@ static void acpi_create_madt(struct acpi_madt *madt)
 	/* Fill out header fields */
 	acpi_fill_header(header, "APIC");
 	header->length = sizeof(struct acpi_madt);
-	header->revision = 4;
+	header->revision = 2;
 
 	madt->lapic_addr = LAPIC_DEFAULT_BASE;
 	madt->flags = ACPI_MADT_PCAT_COMPAT;
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 42/43] x86: Rename board_final_cleanup() to board_final_init()

[Simon Glass]

This function sounds like something that is called when U-Boot is about to
jump to Linux. In fact it is an init function.

Rename it to reduce confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/coreboot/coreboot.c | 4 ++--
 arch/x86/cpu/cpu.c               | 8 ++++----
 arch/x86/cpu/efi/app.c           | 2 +-
 arch/x86/cpu/quark/quark.c       | 2 +-
 arch/x86/lib/fsp/fsp_common.c    | 2 +-
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index d44db1347b..22a93254a9 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -42,7 +42,7 @@ int print_cpuinfo(void)
 	return default_print_cpuinfo();
 }
 
-static void board_final_cleanup(void)
+static void board_final_init(void)
 {
 	/*
 	 * Un-cache the ROM so the kernel has one
@@ -80,7 +80,7 @@ int last_stage_init(void)
 	if (CONFIG_IS_ENABLED(USB_KEYBOARD))
 		usb_init();
 
-	board_final_cleanup();
+	board_final_init();
 
 	return 0;
 }
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 9bc243ebc8..69c14189d1 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -182,10 +182,10 @@ void show_boot_progress(int val)
 
 #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
 /*
- * Implement a weak default function for boards that optionally
- * need to clean up the system before jumping to the kernel.
+ * Implement a weak default function for boards that need to do some final init
+ * before the system is ready.
  */
-__weak void board_final_cleanup(void)
+__weak void board_final_init(void)
 {
 }
 
@@ -193,7 +193,7 @@ int last_stage_init(void)
 {
 	struct acpi_fadt __maybe_unused *fadt;
 
-	board_final_cleanup();
+	board_final_init();
 
 	if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
 		fadt = acpi_find_fadt();
diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c
index 10677ecbc2..f754489784 100644
--- a/arch/x86/cpu/efi/app.c
+++ b/arch/x86/cpu/efi/app.c
@@ -24,7 +24,7 @@ int print_cpuinfo(void)
 	return default_print_cpuinfo();
 }
 
-void board_final_cleanup(void)
+void board_final_init(void)
 {
 }
 
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index ddad02e375..30b4711b9a 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -363,7 +363,7 @@ int arch_misc_init(void)
 	return 0;
 }
 
-void board_final_cleanup(void)
+void board_final_init(void)
 {
 	struct quark_rcba *rcba;
 	u32 base, val;
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 8e3082d4c8..ea52954725 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -47,7 +47,7 @@ int fsp_init_phase_pci(void)
 	return status ? -EPERM : 0;
 }
 
-void board_final_cleanup(void)
+void board_final_init(void)
 {
 	u32 status;
 
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 43/43] acpi: Enable ACPI table generation by default on x86

[Simon Glass]

This should ideally be used by all x86 boards in U-Boot. Enable it by
default. If some boards don't use it, the cost is small.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/Kconfig b/arch/Kconfig
index a11f872938..650bc0dbca 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -190,6 +190,7 @@ config X86
 	imply PCH
 	imply RTC_MC146818
 	imply IRQ
+	imply ACPIGEN
 
 	# Thing to enable for when SPL/TPL are enabled: SPL
 	imply SPL_DM
-- 
2.27.0.290.gba653c62da-goog

[PATCH v1 29/43] p2sb: Add a method to hide the bus

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----

> Betreff: [PATCH v1 29/43] p2sb: Add a method to hide the bus
> 
> The P2SB bus needs to be hidden in some cases so that it does not get
> auto-configured by Linux. Add a method for this.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  drivers/misc/p2sb-uclass.c | 10 ++++++++++
>  include/p2sb.h             | 25 ++++++++++++++++++++++++-
>  2 files changed, 34 insertions(+), 1 deletion(-)
> 

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested on an Apollo Lake-based board.

[PATCH v1 30/43] x86: apl: Support set_hide() in p2sb driver

[Wolfgang Wallner]

Hi Simon,


-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 30/43] x86: apl: Support set_hide() in p2sb driver
> 
> Add support for this new method in the driver and in the fsp-s setup.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/cpu/apollolake/fsp_s.c  | 26 +++++++++++---------------
>  arch/x86/cpu/intel_common/p2sb.c | 30 ++++++++++++++++++++++++++++++
>  2 files changed, 41 insertions(+), 15 deletions(-)
> 

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested on an Apollo Lake-based board.

[PATCH v1 31/43] x86: apl: Hide the p2sb on exit from U-Boot

[Wolfgang Wallner]

Hi Simon,

> -----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 31/43] x86: apl: Hide the p2sb on exit from U-Boot
> 
> This confuses Linux's PCI probing so needs to be hidden when booting
> Linux. Add a remove() method to handle this.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/cpu/intel_common/p2sb.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c
> index ebf8f62aea..361d4c90cb 100644
> --- a/arch/x86/cpu/intel_common/p2sb.c
> +++ b/arch/x86/cpu/intel_common/p2sb.c
> @@ -153,6 +153,17 @@ static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
>  	return 0;
>  }
>  
> +static int p2sb_remove(struct udevice *dev)
> +{
> +	int ret;
> +
> +	ret = intel_p2sb_set_hide(dev, true);
> +	if (ret)
> +		return log_msg_ret("hide", ret);
> +
> +	return 0;
> +}
> +
>  static int p2sb_child_post_bind(struct udevice *dev)
>  {
>  #if !CONFIG_IS_ENABLED(OF_PLATDATA)
> @@ -183,9 +194,12 @@ U_BOOT_DRIVER(p2sb_drv) = {
>  	.id		= UCLASS_P2SB,
>  	.of_match	= p2sb_ids,
>  	.probe		= p2sb_probe,
> +	.remove		= p2sb_remove,
> +	.ops		= &p2sb_ops,

Nit: should this line be part of the previous patch?

>  	.ofdata_to_platdata = p2sb_ofdata_to_platdata,
>  	.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
>  	.per_child_platdata_auto_alloc_size =
>  		sizeof(struct p2sb_child_platdata),
>  	.child_post_bind = p2sb_child_post_bind,
> +	.flags		= DM_FLAG_OS_PREPARE,
>  };
> -- 
> 2.27.0.290.gba653c62da-goog

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested on an Apollo Lake-based board.

[PATCH v1 09/43] acpi: Support generation of a scope

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 09/43] acpi: Support generation of a scope
> 
> Add a function to write a scope to the generated ACPI code.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  include/acpi/acpigen.h | 10 ++++++++++
>  lib/acpi/acpigen.c     |  7 +++++++
>  test/dm/acpi.c         |  3 +--
>  test/dm/acpigen.c      | 33 ++++++++++++++++++++++++++++++++-
>  4 files changed, 50 insertions(+), 3 deletions(-)
> 
> diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
> index 7c117c1cf6..af66c9828f 100644
> --- a/include/acpi/acpigen.h
> +++ b/include/acpi/acpigen.h
> @@ -31,6 +31,7 @@ enum {
>  	DWORD_PREFIX		= 0x0c,
>  	STRING_PREFIX		= 0x0d,
>  	QWORD_PREFIX		= 0x0e,
> +	SCOPE_OP		= 0x10,
>  	BUFFER_OP		= 0x11,
>  	PACKAGE_OP		= 0x12,
>  	METHOD_OP		= 0x14,
> @@ -258,6 +259,14 @@ void acpigen_emit_namestring(struct acpi_ctx *ctx, const char *namepath);
>   */
>  void acpigen_write_name(struct acpi_ctx *ctx, const char *namepath);
>  
> +/**
> + * acpigen_write_scope() - Write a scope
> + *
> + * @ctx: ACPI context pointer
> + * @name: Scope to write (e.g. "\\_SB.ABCD")

Nit: IMHO 'path' or 'scope' wopuld be better names for this parameter, as
it is usually not a single device name.

> + */
> +void acpigen_write_scope(struct acpi_ctx *ctx, const char *name);
> +
>  /**
>   * acpigen_write_uuid() - Write a UUID
>   *
> @@ -396,6 +405,7 @@ void acpigen_write_power_res(struct acpi_ctx *ctx, const char *name, uint level,
>   */
>  int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32 tx_state_val,
>  			       const char *dw0_name, struct acpi_gpio *gpio,
> +
>  			       bool enable);
>  
>  #endif
> diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
> index e0af36f775..77d6434806 100644
> --- a/lib/acpi/acpigen.c
> +++ b/lib/acpi/acpigen.c
> @@ -257,6 +257,13 @@ void acpigen_write_name(struct acpi_ctx *ctx, const char *namepath)
>  	acpigen_emit_namestring(ctx, namepath);
>  }
>  
> +void acpigen_write_scope(struct acpi_ctx *ctx, const char *name)
> +{
> +	acpigen_emit_byte(ctx, SCOPE_OP);
> +	acpigen_write_len_f(ctx);
> +	acpigen_emit_namestring(ctx, name);
> +}
> +
>  static void acpigen_write_method_(struct acpi_ctx *ctx, const char *name,
>  				  uint flags)
>  {
> diff --git a/test/dm/acpi.c b/test/dm/acpi.c
> index 7768f9514c..b94c4ba4d1 100644
> --- a/test/dm/acpi.c
> +++ b/test/dm/acpi.c
> @@ -20,9 +20,8 @@
>  #include <dm/acpi.h>
>  #include <dm/test.h>
>  #include <test/ut.h>
> +#include "acpi.h"
>  
> -#define ACPI_TEST_DEV_NAME	"ABCD"
> -#define ACPI_TEST_CHILD_NAME	"EFGH"
>  #define BUF_SIZE		4096
>  
>  /**
> diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
> index 0322dd4f60..93dfa301d6 100644
> --- a/test/dm/acpigen.c
> +++ b/test/dm/acpigen.c
> @@ -18,6 +18,7 @@
>  #include <dm/test.h>
>  #include <dm/uclass-internal.h>
>  #include <test/ut.h>
> +#include "acpi.h"
>  
>  #define TEST_STRING	"frogmore"
>  #define TEST_STRING2	"ranch"
> @@ -359,7 +360,7 @@ DM_TEST(dm_test_acpi_spi, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
>   */
>  static int get_length(u8 *ptr)
>  {
> -	if (!(*ptr & 0x80))
> +	if (!(*ptr & ACPI_PKG_LEN_3_BYTES))
>  		return -EINVAL;
>  
>  	return (*ptr & 0xf) | ptr[1] << 4 | ptr[2] << 12;
> @@ -906,3 +907,33 @@ static int dm_test_acpi_write_values(struct unit_test_state *uts)
>  }
>  DM_TEST(dm_test_acpi_write_values, 0);
>  
> +/* Test writing a scope */
> +static int dm_test_acpi_scope(struct unit_test_state *uts)
> +{
> +	char buf[ACPI_PATH_MAX];
> +	struct acpi_ctx *ctx;
> +	struct udevice *dev;
> +	u8 *ptr;
> +
> +	ut_assertok(alloc_context(&ctx));
> +	ptr = acpigen_get_current(ctx);
> +
> +	ut_assertok(uclass_first_device_err(UCLASS_TEST_ACPI, &dev));
> +	ut_assertok(acpi_device_path(dev, buf, sizeof(buf)));
> +	acpigen_write_scope(ctx, buf);
> +	acpigen_pop_len(ctx);
> +
> +	ut_asserteq(SCOPE_OP, *ptr++);
> +	ut_asserteq(13, get_length(ptr));
> +	ptr += 3;
> +	ut_asserteq(ROOT_PREFIX, *ptr++);
> +	ut_asserteq(DUAL_NAME_PREFIX, *ptr++);
> +	ut_asserteq_strn("_SB_" ACPI_TEST_DEV_NAME, (char *)ptr);
> +	ptr += 8;
> +	ut_asserteq_ptr(ptr, ctx->current);
> +
> +	free_context(&ctx);
> +
> +	return 0;
> +}
> +DM_TEST(dm_test_acpi_scope, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
> -- 
> 2.27.0.290.gba653c62da-goog

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 10/43] acpi: Support generation of a generic register

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 10/43] acpi: Support generation of a generic register
> 
> Allow writing out a generic register.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  include/acpi/acpi_device.h |  1 +
>  include/acpi/acpigen.h     | 28 +++++++++++++++
>  lib/acpi/acpigen.c         | 71 ++++++++++++++++++++++++++++++++++++++
>  test/dm/acpigen.c          | 46 ++++++++++++++++++++++++
>  4 files changed, 146 insertions(+)
> 

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 13/43] acpi: Support generation of a device

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> 
> Betreff: [PATCH v1 13/43] acpi: Support generation of a device
> 
> Allow writing an ACPI device to the generated ACPI code.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  include/acpi/acpigen.h |  9 +++++++++
>  lib/acpi/acpigen.c     |  7 +++++++
>  test/dm/acpigen.c      | 27 +++++++++++++++++++++++++++
>  3 files changed, 43 insertions(+)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 14/43] acpi: Support writing named values

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 14/43] acpi: Support writing named values
> 
> Allow writing named integers and strings to the generated ACPI code.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  include/acpi/acpigen.h | 72 ++++++++++++++++++++++++++++++++++++++
>  lib/acpi/acpigen.c     | 49 ++++++++++++++++++++++++++
>  test/dm/acpigen.c      | 78 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 199 insertions(+)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 21/43] x86: pinctrl: Drop the acpi_name member

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 21/43] x86: pinctrl: Drop the acpi_name member

Nit: You are dropping the acpi_path member, not acpi_name.

> 
> This is in the device tree now, so drop the unnecessary field here.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/include/asm/intel_pinctrl.h | 2 --
>  drivers/pinctrl/intel/pinctrl_apl.c  | 4 ----
>  2 files changed, 6 deletions(-)
> 
> diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
> index 982b2514a0..e734f4a7f0 100644
> --- a/arch/x86/include/asm/intel_pinctrl.h
> +++ b/arch/x86/include/asm/intel_pinctrl.h
> @@ -99,7 +99,6 @@ struct pad_group {
>   * groups exist inside a community
>   *
>   * @name: Community name
> - * @acpi_path: ACPI path
>   * @num_gpi_regs: number of gpi registers in community
>   * @max_pads_per_group: number of pads in each group; number of pads bit-mapped
>   *	in each GPI status/en and Host Own Reg
> @@ -120,7 +119,6 @@ struct pad_group {
>   */
>  struct pad_community {
>  	const char *name;
> -	const char *acpi_path;
>  	size_t num_gpi_regs;
>  	size_t max_pads_per_group;
>  	uint first_pad;
> diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c
> index c14176d4a7..7624a9974f 100644
> --- a/drivers/pinctrl/intel/pinctrl_apl.c
> +++ b/drivers/pinctrl/intel/pinctrl_apl.c
> @@ -75,7 +75,6 @@ static const struct pad_community apl_gpio_communities[] = {
>  		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
>  		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
>  		.name = "GPIO_GPE_N",
> -		.acpi_path = "\\_SB.GPO0",
>  		.reset_map = rst_map,
>  		.num_reset_vals = ARRAY_SIZE(rst_map),
>  		.groups = apl_community_n_groups,
> @@ -94,7 +93,6 @@ static const struct pad_community apl_gpio_communities[] = {
>  		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
>  		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
>  		.name = "GPIO_GPE_NW",
> -		.acpi_path = "\\_SB.GPO1",
>  		.reset_map = rst_map,
>  		.num_reset_vals = ARRAY_SIZE(rst_map),
>  		.groups = apl_community_nw_groups,
> @@ -113,7 +111,6 @@ static const struct pad_community apl_gpio_communities[] = {
>  		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
>  		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
>  		.name = "GPIO_GPE_W",
> -		.acpi_path = "\\_SB.GPO2",
>  		.reset_map = rst_map,
>  		.num_reset_vals = ARRAY_SIZE(rst_map),
>  		.groups = apl_community_w_groups,
> @@ -132,7 +129,6 @@ static const struct pad_community apl_gpio_communities[] = {
>  		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
>  		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
>  		.name = "GPIO_GPE_SW",
> -		.acpi_path = "\\_SB.GPO3",
>  		.reset_map = rst_map,
>  		.num_reset_vals = ARRAY_SIZE(rst_map),
>  		.groups = apl_community_sw_groups,
> -- 
> 2.27.0.290.gba653c62da-goog

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 36/43] x86: apl: Adjust FSP-M code to avoid hard-coded address

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 36/43] x86: apl: Adjust FSP-M code to avoid hard-coded address
> 
> Update this code to calculate the address to use, rather than hard-coding
> it. Obtain the requested stack size from the FSP.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/cpu/apollolake/fsp_m.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c
> index 65461d85b8..cef937573b 100644
> --- a/arch/x86/cpu/apollolake/fsp_m.c
> +++ b/arch/x86/cpu/apollolake/fsp_m.c
> @@ -24,9 +24,11 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
>  	cache_ret = prepare_mrc_cache(upd);
>  	if (cache_ret && cache_ret != -ENOENT)
>  		return log_msg_ret("mrc", cache_ret);
> -	arch->stack_base = (void *)0xfef96000;
> +	arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE -
> +		 arch->stack_size);
>  	arch->boot_loader_tolum_size = 0;
> -	arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION;
> +	arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION :
> +		FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;

This change is not related to the change calculation of stack_base, and so I
think it should be a separate commit.

I see that arch-boot_mode is handled similarly in Coreboot, so I assume this
is correct, but I could not find documentation about what 
FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES is doing differently.
Could you point me to the relevant documentation?

>  
>  	node = dev_ofnode(dev);
>  	if (!ofnode_valid(node))
> -- 
> 2.27.0.290.gba653c62da-goog

I think both changes are correct, just that they should be separate patches.
So if you split them up both of them are:

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

regards, Wolfgang

[PATCH v1 04/43] acpi: Allow creating the GNVS to fail

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 04/43] acpi: Allow creating the GNVS to fail
> 
> In some cases an internal error may prevent this from working. Update the
> function return value and report the error. At present the API for writing
> tables does not easily support reporting errors, but once it is fully
> updated to use a context pointer, this will be easier.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v1:
> - Add linux/err.h header
> 
>  arch/x86/cpu/baytrail/acpi.c      |  4 +++-
>  arch/x86/cpu/quark/acpi.c         |  4 +++-
>  arch/x86/cpu/tangier/acpi.c       |  4 +++-
>  arch/x86/include/asm/acpi_table.h | 10 +++++++++-
>  arch/x86/lib/acpi_table.c         | 11 +++++++++--
>  5 files changed, 27 insertions(+), 6 deletions(-)
> 

[snip]

> diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
> index eeacfe9b06..27869a0e5e 100644
> --- a/arch/x86/lib/acpi_table.c
> +++ b/arch/x86/lib/acpi_table.c
> @@ -23,6 +23,7 @@
>  #include <asm/tables.h>
>  #include <asm/arch/global_nvs.h>
>  #include <dm/acpi.h>
> +#include <linux/err.h>
>  
>  /*
>   * IASL compiles the dsdt entries and writes the hex values
> @@ -443,8 +444,14 @@ ulong write_acpi_tables(ulong start_addr)
>  	dsdt->checksum = 0;
>  	dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
>  
> -	/* Fill in platform-specific global NVS variables */
> -	acpi_create_gnvs(ctx->current);
> +	/*
> +	 * Fill in platform-specific global NVS variables. If this fails we
> +	 * cannot return the error but this should only happen while debugging.
> +	 */
> +	addr = acpi_create_gnvs(ctx->current);
> +	if (IS_ERR_VALUE(addr))
> +		printf("Error: Gailed to create GNVS\n");

Typo: Failed

> +
>  	acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
>  
>  	debug("ACPI:    * FADT\n");
> -- 
> 2.27.0.290.gba653c62da-goog

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 06/43] dm: core: Add a way of overriding the ACPI device path

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 06/43] dm: core: Add a way of overriding the ACPI device path
> 
> Some devices such as GPIO need to override the normal path that would be
> generated by driver model. Add a device-tree property for this.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  doc/device-tree-bindings/device.txt | 23 +++++++++++++++++++++++
>  drivers/core/acpi.c                 | 19 +++++++++++++++++++
>  include/dm/acpi.h                   | 13 +++++++++++++
>  3 files changed, 55 insertions(+)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 26/43] i2c: designware_i2c: Add a little more debugging

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 26/43] i2c: designware_i2c: Add a little more debugging
> 
> Add debugging for a few more values and also use log to show return values
> when something goes wrong. This makes it easier to see the root cause.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v1:
> - Add new patch to improve designware_i2c debugging
> 
>  drivers/i2c/designware_i2c.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 27/43] i2c: Add log_ret() on error

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 27/43] i2c: Add log_ret() on error
> 
> Add a few of these calls to make it easier to see where an error occurs,
> if CONFIG_LOG_ERROR_RETURN is enabled.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  drivers/i2c/i2c-uclass.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 28/43] i2c: designware_i2c: Support ACPI table generation

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 28/43] i2c: designware_i2c: Support ACPI table generation
> 
> Update the PCI driver to generate ACPI information so that Linux has the
> full information about each I2C bus.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> 
> ---
> 
> Changes in v1:
> - Capitalise ACPI_OPS_PTR
> 
>  drivers/i2c/designware_i2c.c     |  25 ++++++++
>  drivers/i2c/designware_i2c.h     |  15 +++++
>  drivers/i2c/designware_i2c_pci.c | 104 ++++++++++++++++++++++++++++++-
>  3 files changed, 143 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
> index 44a1f33398..630938743f 100644
> --- a/drivers/i2c/designware_i2c.c
> +++ b/drivers/i2c/designware_i2c.c
> @@ -333,6 +333,31 @@ static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
>  	/* Restore back i2c now speed set */
>  	if (ena == IC_ENABLE_0B)
>  		dw_i2c_enable(i2c_base, true);
> +	if (priv)
> +		priv->config = config;
> +	return 0;
> +}
> +
> +int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
> +			    struct dw_i2c_speed_config *config)
> +{
> +	struct dw_i2c *priv = dev_get_priv(dev);
> +	ulong rate;
> +	int ret;
> +
> +#if CONFIG_IS_ENABLED(CLK)
> +	rate = clk_get_rate(&priv->clk);
> +	if (IS_ERR_VALUE(rate))
> +		return log_msg_ret("clk", -EINVAL);
> +#else
> +	rate = IC_CLK;
> +#endif
> +
> +	ret = calc_bus_speed(priv, priv->regs, speed_hz, rate, config);
> +	if (ret)
> +		printf("%s: ret=%d\n", __func__, ret);
> +	if (ret)
> +		return log_msg_ret("calc_bus_speed", ret);
>  
>  	return 0;
>  }
> diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
> index dc9a6ccb63..d87a3bff93 100644
> --- a/drivers/i2c/designware_i2c.h
> +++ b/drivers/i2c/designware_i2c.h
> @@ -205,6 +205,7 @@ struct dw_i2c {
>  #if CONFIG_IS_ENABLED(CLK)
>  	struct clk clk;
>  #endif
> +	struct dw_i2c_speed_config config;
>  };
>  
>  extern const struct dm_i2c_ops designware_i2c_ops;
> @@ -213,4 +214,18 @@ int designware_i2c_probe(struct udevice *bus);
>  int designware_i2c_remove(struct udevice *dev);
>  int designware_i2c_ofdata_to_platdata(struct udevice *bus);
>  
> +/**
> + * dw_i2c_gen_speed_config() - Calculate config info from requested speed1
> + *
> + * Calculate the speed config from the given @speed_hz and return it so that
> + * it can be incorporated in ACPI tables
> + *
> + * @dev: I2C bus to check
> + * @speed_hz: Requested speed in Hz
> + * @config: Returns config to use for that speed
> + * @return 0 if OK, -ve on error
> + */
> +int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
> +			    struct dw_i2c_speed_config *config);
> +
>  #endif /* __DW_I2C_H_ */
> diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
> index bd34ec0b47..d5108e9064 100644
> --- a/drivers/i2c/designware_i2c_pci.c
> +++ b/drivers/i2c/designware_i2c_pci.c
> @@ -9,7 +9,12 @@
>  #include <dm.h>
>  #include <log.h>
>  #include <spl.h>
> +#include <acpi/acpigen.h>
> +#include <acpi/acpi_device.h>
>  #include <asm/lpss.h>
> +#include <dm/acpi.h>
> +#include <dm/device-internal.h>
> +#include <dm/uclass-internal.h>
>  #include "designware_i2c.h"
>  
>  enum {
> @@ -87,6 +92,8 @@ static int designware_i2c_pci_bind(struct udevice *dev)
>  {
>  	char name[20];
>  
> +	if (dev_of_valid(dev))
> +		return 0;
>  	/*
>  	 * Create a unique device name for PCI type devices
>  	 * ToDo:
> @@ -100,13 +107,107 @@ static int designware_i2c_pci_bind(struct udevice *dev)
>  	 * be possible. We cannot use static data in drivers since they may be
>  	 * used in SPL or before relocation.
>  	 */
> -	dev->req_seq = gd->arch.dw_i2c_num_cards++;
> +	dev->req_seq = uclass_find_next_free_req_seq(UCLASS_I2C);
>  	sprintf(name, "i2c_designware#%u", dev->req_seq);
>  	device_set_name(dev, name);
>  
>  	return 0;
>  }
>  
> +/*
> + * Write ACPI object to describe speed configuration.
> + *
> + * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
> + *
> + * SSCN: I2C_SPEED_STANDARD
> + * FMCN: I2C_SPEED_FAST
> + * FPCN: I2C_SPEED_FAST_PLUS
> + * HSCN: I2C_SPEED_HIGH
> + */
> +static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
> +					   struct dw_i2c_speed_config *config)
> +{
> +	switch (config->speed_mode) {
> +	case IC_SPEED_MODE_HIGH:
> +		acpigen_write_name(ctx, "HSCN");
> +		break;
> +	case IC_SPEED_MODE_FAST_PLUS:
> +		acpigen_write_name(ctx, "FPCN");
> +		break;
> +	case IC_SPEED_MODE_FAST:
> +		acpigen_write_name(ctx, "FMCN");
> +		break;
> +	case IC_SPEED_MODE_STANDARD:
> +	default:
> +		acpigen_write_name(ctx, "SSCN");
> +	}
> +
> +	/* Package () { scl_lcnt, scl_hcnt, sda_hold } */
> +	acpigen_write_package(ctx, 3);
> +	acpigen_write_word(ctx, config->scl_hcnt);
> +	acpigen_write_word(ctx, config->scl_lcnt);
> +	acpigen_write_dword(ctx, config->sda_hold);
> +	acpigen_pop_len(ctx);
> +}

This function is rather generic, and probably the same for any I2C controller.
Is the intention to implement it for Designware as a first step and move it to
a generic place if the need arises, or should it stay here?

> +
> +/*
> + * Generate I2C timing information into the SSDT for the OS driver to consume,
> + * optionally applying override values provided by the caller.
> + */
> +static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
> +				 struct acpi_ctx *ctx)
> +{
> +	struct dw_i2c_speed_config config;
> +	char path[ACPI_PATH_MAX];
> +	u32 speeds[4];
> +	int size, i;
> +	int ret;
> +
> +	/* If no device-tree node, ignore this since we assume it isn't used */
> +	if (!dev_of_valid(dev))
> +		return 0;
> +	ret = acpi_device_path(dev, path, sizeof(path));
> +	if (ret)
> +		return log_msg_ret("path", ret);
> +
> +	size = dev_read_size(dev, "i2c,speeds");
> +	if (size < 0)
> +		return log_msg_ret("i2c,speeds", -EINVAL);
> +	size /= sizeof(u32);
> +	if (size > ARRAY_SIZE(speeds))
> +		return log_msg_ret("array", -E2BIG);
> +
> +	ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size);
> +	if (ret)
> +		return log_msg_ret("read", -E2BIG);
> +
> +	if (0) {

This seems like some left-over debugging code ... ?

> +		acpigen_write_scope(ctx, path);
> +		for (i = 0; i < size; i++) {
> +			ret = dw_i2c_gen_speed_config(dev, speeds[i], &config);
> +			if (ret)
> +				return log_msg_ret("config", ret);
> +			dw_i2c_acpi_write_speed_config(ctx, &config);
> +		}
> +	} else {
> +		uint speed;
> +
> +		speed = dev_read_u32_default(dev, "clock-frequency", 100000);
> +		acpigen_write_scope(ctx, path);
> +		ret = dw_i2c_gen_speed_config(dev, speed, &config);
> +		if (ret)
> +			return log_msg_ret("config", ret);
> +		dw_i2c_acpi_write_speed_config(ctx, &config);
> +	}
> +	acpigen_pop_len(ctx);
> +
> +	return 0;
> +}
> +
> +struct acpi_ops dw_i2c_acpi_ops = {
> +	.fill_ssdt	= dw_i2c_acpi_fill_ssdt,
> +};
> +
>  static const struct udevice_id designware_i2c_pci_ids[] = {
>  	{ .compatible = "snps,designware-i2c-pci" },
>  	{ .compatible = "intel,apl-i2c", .data = INTEL_APL },
> @@ -124,6 +225,7 @@ U_BOOT_DRIVER(i2c_designware_pci) = {
>  	.remove = designware_i2c_remove,
>  	.flags = DM_FLAG_OS_PREPARE,
>  	.ops	= &designware_i2c_ops,
> +	ACPI_OPS_PTR(&dw_i2c_acpi_ops)
>  };
>  
>  static struct pci_device_id designware_pci_supported[] = {
> -- 
> 2.27.0.290.gba653c62da-goog

regards, Wolfgang

[PATCH v1 32/43] pmc: Move common registers to the header file

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 32/43] pmc: Move common registers to the header file
> 
> These registers need to be accesses from ACPI code, so move them to the
> header file.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  drivers/power/acpi_pmc/acpi-pmc-uclass.c |  9 ---------
>  include/power/acpi_pmc.h                 | 14 ++++++++++++++
>  2 files changed, 14 insertions(+), 9 deletions(-)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 35/43] x86: Add debugging to table writing

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 35/43] x86: Add debugging to table writing
> 
> Writing tables is currently pretty opaque. Add a bit of debugging to the
> process so we can see what tables are written and where they start/end in
> memory.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/lib/tables.c | 38 ++++++++++++++++++++++++++++----------
>  1 file changed, 28 insertions(+), 10 deletions(-)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 39/43] x86: Update the comment about booting for FSP2

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 39/43] x86: Update the comment about booting for FSP2
> 
> The comment here applies only to FSP1, so update it.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/cpu/start.S | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
> index 01524635e9..4ad515ce08 100644
> --- a/arch/x86/cpu/start.S
> +++ b/arch/x86/cpu/start.S
> @@ -124,6 +124,7 @@ car_init_ret:
>  #endif
>  #else
>  	/*
> +	 * Instructions for FSP1, but not FSP2:
>  	 * U-Boot enters here twice. For the first time it comes from
>  	 * car_init_done() with esp points to a temporary stack and esi
>  	 * set to zero. For the second time it comes from fsp_init_done()
> -- 
> 2.27.0.290.gba653c62da-goog

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 42/43] x86: Rename board_final_cleanup() to board_final_init()

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 42/43] x86: Rename board_final_cleanup() to board_final_init()
> 
> This function sounds like something that is called when U-Boot is about to
> jump to Linux. In fact it is an init function.
> 
> Rename it to reduce confusion.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/cpu/coreboot/coreboot.c | 4 ++--
>  arch/x86/cpu/cpu.c               | 8 ++++----
>  arch/x86/cpu/efi/app.c           | 2 +-
>  arch/x86/cpu/quark/quark.c       | 2 +-
>  arch/x86/lib/fsp/fsp_common.c    | 2 +-
>  5 files changed, 9 insertions(+), 9 deletions(-)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 07/43] dm: acpi: Add support for the NHLT table
> 
> The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> audio codecs and connections in a system. Various devices can contribute
> information to produce the table.
> 
> Add core support for this, based on a structure which is built up through
> calls to the driver.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  drivers/core/acpi.c | 15 +++++++++++++++
>  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
>  2 files changed, 41 insertions(+)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 08/43] acpi: Export functions to write sized values

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 08/43] acpi: Export functions to write sized values
> 
> At present only acpigen_write_integer() is exported for use by other code.
> But in some cases it is useful to call the specific function depending on
> the size of the value.
> 
> Export these functions and add a test.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  include/acpi/acpigen.h | 46 ++++++++++++++++++++++++++++++++++++++++++
>  test/dm/acpigen.c      | 45 ++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 90 insertions(+), 1 deletion(-)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 11/43] acpi: mmc: Generate ACPI info for the PCI SD Card

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 11/43] acpi: mmc: Generate ACPI info for the PCI SD Card
> 
> Write required information into the SSDT to describe the SD card
> card-detect pin. Since the required GPIO properties are not present in
> the device-tree binding, set them manually for now.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v1:
> - Capitalise ACPI_OPS_PTR
> 
>  configs/sandbox_defconfig |  2 +
>  drivers/mmc/pci_mmc.c     | 78 ++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 79 insertions(+), 1 deletion(-)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 12/43] x86: Add bindings for NHLT

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 12/43] x86: Add bindings for NHLT
> 
> Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table
> (NHLT).
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  include/dt-bindings/sound/nhlt.h | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 include/dt-bindings/sound/nhlt.h
> 
> diff --git a/include/dt-bindings/sound/nhlt.h b/include/dt-bindings/sound/nhlt.h
> new file mode 100644
> index 0000000000..c33f874966
> --- /dev/null
> +++ b/include/dt-bindings/sound/nhlt.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2019 Google LLC
> + */
> +
> +#ifndef _DT_BINDINGS_SOUND_NHLT_H
> +#define _DT_BINDINGS_SOUND_NHLT_H
> +

Nit: I like to know where numeric constants come from, so I would propose to
add a comment like the following:

/* See Table 2-1. NHLT Endpoint Descriptor in the NHLT Specification (0.8.1) */
> +#define NHLT_VID	0x8086
> +#define NHLT_DID_DMIC	0xae20
> +#define NHLT_DID_BT	0xae30
> +#define NHLT_DID_SSP	0xae34
> +
> +/* Hardware links available to use for codecs */
> +#define AUDIO_LINK_SSP0		0
> +#define AUDIO_LINK_SSP1		1
> +#define AUDIO_LINK_SSP2		2
> +#define AUDIO_LINK_SSP3		3
> +#define AUDIO_LINK_SSP4		4
> +#define AUDIO_LINK_SSP5		5
> +#define AUDIO_LINK_DMIC		6
> +
> +#endif /* _DT_BINDINGS_SOUND_NHLT_H */
> -- 
> 2.27.0.290.gba653c62da-goog

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 17/43] x86: pinctrl: Add a way to get the pinctrl reg address

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 17/43] x86: pinctrl: Add a way to get the pinctrl reg address
> 
> At present we can query the offset of a pinctrl register within the p2sb.
> For ACPI we need to get the actual address of the register. Add a function
> to handle this and rename the old one to more accurately reflect its
> purpose.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/include/asm/intel_pinctrl.h | 16 ++++++++++++++--
>  drivers/gpio/intel_gpio.c            | 15 +++++++++++----
>  drivers/misc/p2sb-uclass.c           | 16 ++++++++--------
>  drivers/pinctrl/intel/pinctrl.c      | 11 +++++++++--
>  include/p2sb.h                       |  9 +++++++++
>  5 files changed, 51 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
> index e2524b089d..f39ebde539 100644
> --- a/arch/x86/include/asm/intel_pinctrl.h
> +++ b/arch/x86/include/asm/intel_pinctrl.h
> @@ -263,11 +263,23 @@ int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
>  int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size);
>  
>  /**
> - * intel_pinctrl_get_config_reg_addr() - Get address of the pin config registers
> + * intel_pinctrl_get_config_reg_offset() - Get offset of pin config registers
>   *
> + * This works out the register offset of a pin within the p2sb region.
> + *
> + * @dev: Pinctrl device
> + * @offset: GPIO offset within this device
> + * @return register offset of first register within the GPIO p2sb region
> + */
> +u32 intel_pinctrl_get_config_reg_offset(struct udevice *dev, uint offset);
> +
> +/**
> + * intel_pinctrl_get_config_reg_offset() - Get address of pin config registers

Copy/Paste error: intel_pinctrl_get_config_reg_addr()

> + *
> + * This works out the absolute address of the registers for a pin
>   * @dev: Pinctrl device
>   * @offset: GPIO offset within this device
> - * @return register offset within the GPIO p2sb region
> + * @return register offset of first register within the GPIO p2sb region

Copy/Paste error: should be address, not offset

>   */
>  u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset);

[snip]

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 02/43] binman: Refactor binman_entry_find() to allow other nodes

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> At present we can only read from a top-level binman node entry. Refactor
> this function to produce a second local function which supports reading
> from any node.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  lib/binman.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/lib/binman.c b/lib/binman.c
> index dc3a880882..79d01230dd 100644
> --- a/lib/binman.c
> +++ b/lib/binman.c
> @@ -29,25 +29,31 @@ struct binman_info {
>
>  static struct binman_info *binman;
>
> -int binman_entry_find(const char *name, struct binman_entry *entry)
> +int binman_entry_find_(ofnode node, const char *name, struct binman_entry *entry)

This one should be static. We really should agree on a naming
convention for such internal APIs. I would prefer adding _internal
suffix, or using __ prefix

>  {
> -       ofnode node;
>         int ret;
>
> -       node = ofnode_find_subnode(binman->image, name);
>         if (!ofnode_valid(node))
> -               return log_msg_ret("no binman node", -ENOENT);
> +               node = binman->image;
> +       node = ofnode_find_subnode(node, name);
> +       if (!ofnode_valid(node))
> +               return log_msg_ret("node", -ENOENT);
>
>         ret = ofnode_read_u32(node, "image-pos", &entry->image_pos);
>         if (ret)
> -               return log_msg_ret("bad binman node1", ret);
> +               return log_msg_ret("import-pos", ret);
>         ret = ofnode_read_u32(node, "size", &entry->size);
>         if (ret)
> -               return log_msg_ret("bad binman node2", ret);
> +               return log_msg_ret("size", ret);
>
>         return 0;
>  }
>
> +int binman_entry_find(const char *name, struct binman_entry *entry)
> +{
> +       return binman_entry_find_(binman->image, name, entry);
> +}
> +
>  void binman_set_rom_offset(int rom_offset)
>  {
>         binman->rom_offset = rom_offset;
> --

Regards,
Bin

[PATCH v1 04/43] acpi: Allow creating the GNVS to fail

[Bin Meng]

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> In some cases an internal error may prevent this from working. Update the
> function return value and report the error. At present the API for writing
> tables does not easily support reporting errors, but once it is fully
> updated to use a context pointer, this will be easier.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v1:
> - Add linux/err.h header
>
>  arch/x86/cpu/baytrail/acpi.c      |  4 +++-
>  arch/x86/cpu/quark/acpi.c         |  4 +++-
>  arch/x86/cpu/tangier/acpi.c       |  4 +++-
>  arch/x86/include/asm/acpi_table.h | 10 +++++++++-
>  arch/x86/lib/acpi_table.c         | 11 +++++++++--
>  5 files changed, 27 insertions(+), 6 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 06/43] dm: core: Add a way of overriding the ACPI device path

[Bin Meng]

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> Some devices such as GPIO need to override the normal path that would be
> generated by driver model. Add a device-tree property for this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  doc/device-tree-bindings/device.txt | 23 +++++++++++++++++++++++
>  drivers/core/acpi.c                 | 19 +++++++++++++++++++
>  include/dm/acpi.h                   | 13 +++++++++++++
>  3 files changed, 55 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> audio codecs and connections in a system. Various devices can contribute
> information to produce the table.
>
> Add core support for this, based on a structure which is built up through
> calls to the driver.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/core/acpi.c | 15 +++++++++++++++
>  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
>  2 files changed, 41 insertions(+)
>
> diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> index ea304a3067..a5053fec6f 100644
> --- a/drivers/core/acpi.c
> +++ b/drivers/core/acpi.c
> @@ -31,6 +31,7 @@ enum method_t {
>         METHOD_WRITE_TABLES,
>         METHOD_FILL_SSDT,
>         METHOD_INJECT_DSDT,
> +       METHOD_SETUP_NHLT,

Do we really need to promote this to be an ACPI core method? Can we
reuse the SSDT/DSDT one?

>  };
>
>  /* Prototype for all methods */
> @@ -239,6 +240,8 @@ acpi_method acpi_get_method(struct udevice *dev, enum method_t method)
>                         return aops->fill_ssdt;
>                 case METHOD_INJECT_DSDT:
>                         return aops->inject_dsdt;
> +               case METHOD_SETUP_NHLT:
> +                       return aops->setup_nhlt;
>                 }
>         }
>
> @@ -325,3 +328,15 @@ int acpi_write_dev_tables(struct acpi_ctx *ctx)
>
>         return ret;
>  }
> +
> +int acpi_setup_nhlt(struct acpi_ctx *ctx, struct nhlt *nhlt)
> +{
> +       int ret;
> +
> +       log_debug("Setup NHLT\n");
> +       ctx->nhlt = nhlt;
> +       ret = acpi_recurse_method(ctx, dm_root(), METHOD_SETUP_NHLT, TYPE_NONE);
> +       log_debug("Setup finished, err=%d\n", ret);
> +
> +       return ret;
> +}
> diff --git a/include/dm/acpi.h b/include/dm/acpi.h
> index b6308b9fa6..a7f8e10ee2 100644
> --- a/include/dm/acpi.h
> +++ b/include/dm/acpi.h
> @@ -27,6 +27,8 @@
>
>  #if !defined(__ACPI__)
>
> +struct nhlt;
> +
>  /** enum acpi_dump_option - selects what ACPI information to dump */
>  enum acpi_dump_option {
>         ACPI_DUMP_LIST,         /* Just the list of items */
> @@ -44,6 +46,9 @@ enum acpi_dump_option {
>   *     adding a new table. The RSDP holds pointers to the RSDT and XSDT.
>   * @rsdt: Pointer to the Root System Description Table
>   * @xsdt: Pointer to the Extended System Description Table
> + * @nhlt: Intel Non-High-Definition-Audio Link Table (NHLT) pointer, used to
> + *     build up information that audio codecs need to provide in the NHLT ACPI
> + *     table
>   * @len_stack: Stack of 'length' words to fix up later
>   * @ltop: Points to current top of stack (0 = empty)
>   */
> @@ -53,6 +58,7 @@ struct acpi_ctx {
>         struct acpi_rsdp *rsdp;
>         struct acpi_rsdt *rsdt;
>         struct acpi_xsdt *xsdt;
> +       struct nhlt *nhlt;
>         char *len_stack[ACPIGEN_LENSTACK_SIZE];
>         int ltop;
>  };
> @@ -106,6 +112,15 @@ struct acpi_ops {
>          * @return 0 if OK, -ve on error
>          */
>         int (*inject_dsdt)(const struct udevice *dev, struct acpi_ctx *ctx);
> +
> +       /**
> +        * setup_nhlt() - Set up audio information for this device
> +        *
> +        * The method can add information to ctx->nhlt if it likes
> +        *
> +        * @return 0 if OK, -ENODATA if nothing to add, -ve on error
> +        */
> +       int (*setup_nhlt)(const struct udevice *dev, struct acpi_ctx *ctx);
>  };
>
>  #define device_get_acpi_ops(dev)       ((dev)->driver->acpi_ops)
> @@ -170,6 +185,17 @@ int acpi_fill_ssdt(struct acpi_ctx *ctx);
>   */
>  int acpi_inject_dsdt(struct acpi_ctx *ctx);
>
> +/**
> + * acpi_setup_nhlt() - Set up audio information
> + *
> + * This is called to set up the nhlt information for all devices.
> + *
> + * @ctx: ACPI context to use
> + * @nhlt: Pointer to nhlt information to add to
> + * @return 0 if OK, -ve on error
> + */
> +int acpi_setup_nhlt(struct acpi_ctx *ctx, struct nhlt *nhlt);
> +
>  /**
>   * acpi_dump_items() - Dump out the collected ACPI items
>   *
> --

Regards,
Bin

[PATCH v1 08/43] acpi: Export functions to write sized values

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> At present only acpigen_write_integer() is exported for use by other code.
> But in some cases it is useful to call the specific function depending on
> the size of the value.
>
> Export these functions and add a test.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  include/acpi/acpigen.h | 46 ++++++++++++++++++++++++++++++++++++++++++
>  test/dm/acpigen.c      | 45 ++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 90 insertions(+), 1 deletion(-)
>

Since the acpigen_write_integer() patch has not been applied, could
you please squash this patch into:

[v3,15/35] acpi: Support writing an integer
http://patchwork.ozlabs.org/project/uboot/patch/20200614025523.40183-5-sjg at chromium.org/

Regards,
Bin

[PATCH v1 10/43] acpi: Support generation of a generic register

[Bin Meng]

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> Allow writing out a generic register.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  include/acpi/acpi_device.h |  1 +
>  include/acpi/acpigen.h     | 28 +++++++++++++++
>  lib/acpi/acpigen.c         | 71 ++++++++++++++++++++++++++++++++++++++
>  test/dm/acpigen.c          | 46 ++++++++++++++++++++++++
>  4 files changed, 146 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 11/43] acpi: mmc: Generate ACPI info for the PCI SD Card

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> Write required information into the SSDT to describe the SD card
> card-detect pin. Since the required GPIO properties are not present in
> the device-tree binding, set them manually for now.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v1:
> - Capitalise ACPI_OPS_PTR
>
>  configs/sandbox_defconfig |  2 +
>  drivers/mmc/pci_mmc.c     | 78 ++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 79 insertions(+), 1 deletion(-)
>
> diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
> index 982075c568..cb6b4b0ee7 100644
> --- a/configs/sandbox_defconfig
> +++ b/configs/sandbox_defconfig
> @@ -143,7 +143,9 @@ CONFIG_P2SB=y
>  CONFIG_PWRSEQ=y
>  CONFIG_SPL_PWRSEQ=y
>  CONFIG_I2C_EEPROM=y
> +CONFIG_MMC_PCI=y
>  CONFIG_MMC_SANDBOX=y
> +CONFIG_MMC_SDHCI=y
>  CONFIG_MTD=y
>  CONFIG_SPI_FLASH_SANDBOX=y
>  CONFIG_SPI_FLASH_ATMEL=y
> diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
> index 404264a697..0c45e1b893 100644
> --- a/drivers/mmc/pci_mmc.c
> +++ b/drivers/mmc/pci_mmc.c
> @@ -7,10 +7,15 @@
>  #include <common.h>
>  #include <dm.h>
>  #include <errno.h>
> +#include <log.h>
>  #include <malloc.h>
>  #include <mapmem.h>
>  #include <sdhci.h>
> -#include <asm/pci.h>
> +#include <acpi/acpigen.h>
> +#include <acpi/acpi_device.h>
> +#include <acpi/acpi_dp.h>
> +#include <asm-generic/gpio.h>
> +#include <dm/acpi.h>
>
>  struct pci_mmc_plat {
>         struct mmc_config cfg;
> @@ -20,6 +25,7 @@ struct pci_mmc_plat {
>  struct pci_mmc_priv {
>         struct sdhci_host host;
>         void *base;
> +       struct gpio_desc cd_gpio;
>  };
>
>  static int pci_mmc_probe(struct udevice *dev)
> @@ -44,6 +50,15 @@ static int pci_mmc_probe(struct udevice *dev)
>         return sdhci_probe(dev);
>  }
>
> +static int pci_mmc_ofdata_to_platdata(struct udevice *dev)
> +{
> +       struct pci_mmc_priv *priv = dev_get_priv(dev);
> +
> +       gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
> +
> +       return 0;
> +}
> +
>  static int pci_mmc_bind(struct udevice *dev)
>  {
>         struct pci_mmc_plat *plat = dev_get_platdata(dev);
> @@ -51,14 +66,75 @@ static int pci_mmc_bind(struct udevice *dev)
>         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
>  }
>
> +static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev,
> +                                 struct acpi_ctx *ctx)
> +{
> +       struct pci_mmc_priv *priv = dev_get_priv(dev);
> +       char path[ACPI_PATH_MAX];
> +       struct acpi_gpio gpio;
> +       struct acpi_dp *dp;
> +       int ret;
> +
> +       if (!dev_of_valid(dev))
> +               return 0;
> +
> +       ret = gpio_get_acpi(&priv->cd_gpio, &gpio);
> +       if (ret)
> +               return log_msg_ret("gpio", ret);
> +       gpio.type = ACPI_GPIO_TYPE_INTERRUPT;
> +       gpio.pull = ACPI_GPIO_PULL_NONE;
> +       gpio.irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
> +       gpio.irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
> +       gpio.irq.shared = ACPI_IRQ_SHARED;
> +       gpio.irq.wake = ACPI_IRQ_WAKE;

The above are all hardcoded. Is there is way to figure out these from
DT GPIO properties?

> +       gpio.interrupt_debounce_timeout = 10000; /* 100ms */
> +
> +       /* Use device path as the Scope for the SSDT */
> +       ret = acpi_device_path(dev, path, sizeof(path));
> +       if (ret)
> +               return log_msg_ret("path", ret);
> +       acpigen_write_scope(ctx, path);
> +       acpigen_write_name(ctx, "_CRS");
> +
> +       /* Write GpioInt() as default (if set) or custom from devicetree */
> +       acpigen_write_resourcetemplate_header(ctx);
> +       acpi_device_write_gpio(ctx, &gpio);
> +       acpigen_write_resourcetemplate_footer(ctx);
> +
> +       /* Bind the cd-gpio name to the GpioInt() resource */
> +       dp = acpi_dp_new_table("_DSD");
> +       if (!dp)
> +               return -ENOMEM;
> +       acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1);
> +       ret = acpi_dp_write(ctx, dp);
> +       if (ret)
> +               return log_msg_ret("cd", ret);
> +
> +       acpigen_pop_len(ctx);
> +
> +       return 0;
> +}
> +
> +struct acpi_ops pci_mmc_acpi_ops = {
> +       .fill_ssdt      = pci_mmc_acpi_fill_ssdt,
> +};
> +
> +static const struct udevice_id pci_mmc_match[] = {
> +       { .compatible = "intel,apl-sd" },
> +       { }
> +};
> +
>  U_BOOT_DRIVER(pci_mmc) = {
>         .name   = "pci_mmc",
>         .id     = UCLASS_MMC,
> +       .of_match = pci_mmc_match,
>         .bind   = pci_mmc_bind,
> +       .ofdata_to_platdata     = pci_mmc_ofdata_to_platdata,
>         .probe  = pci_mmc_probe,
>         .ops    = &sdhci_ops,
>         .priv_auto_alloc_size = sizeof(struct pci_mmc_priv),
>         .platdata_auto_alloc_size = sizeof(struct pci_mmc_plat),
> +       ACPI_OPS_PTR(&pci_mmc_acpi_ops)
>  };
>
>  static struct pci_device_id mmc_supported[] = {

Regards,
Bin

[PATCH v1 12/43] x86: Add bindings for NHLT

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table
> (NHLT).
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  include/dt-bindings/sound/nhlt.h | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 include/dt-bindings/sound/nhlt.h
>
> diff --git a/include/dt-bindings/sound/nhlt.h b/include/dt-bindings/sound/nhlt.h
> new file mode 100644
> index 0000000000..c33f874966
> --- /dev/null
> +++ b/include/dt-bindings/sound/nhlt.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2019 Google LLC
> + */
> +
> +#ifndef _DT_BINDINGS_SOUND_NHLT_H
> +#define _DT_BINDINGS_SOUND_NHLT_H
> +
> +#define NHLT_VID       0x8086
> +#define NHLT_DID_DMIC  0xae20
> +#define NHLT_DID_BT    0xae30
> +#define NHLT_DID_SSP   0xae34

These look like PCI vendor ID (0x8086 for Intel) and device IDs. If
they are device IDs, how could they be fixed?

> +
> +/* Hardware links available to use for codecs */
> +#define AUDIO_LINK_SSP0                0
> +#define AUDIO_LINK_SSP1                1
> +#define AUDIO_LINK_SSP2                2
> +#define AUDIO_LINK_SSP3                3
> +#define AUDIO_LINK_SSP4                4
> +#define AUDIO_LINK_SSP5                5
> +#define AUDIO_LINK_DMIC                6
> +
> +#endif /* _DT_BINDINGS_SOUND_NHLT_H */
> --

Regards,
Bin

[PATCH v1 13/43] acpi: Support generation of a device

[Bin Meng]

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> Allow writing an ACPI device to the generated ACPI code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  include/acpi/acpigen.h |  9 +++++++++
>  lib/acpi/acpigen.c     |  7 +++++++
>  test/dm/acpigen.c      | 27 +++++++++++++++++++++++++++
>  3 files changed, 43 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 14/43] acpi: Support writing named values

[Bin Meng]

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> Allow writing named integers and strings to the generated ACPI code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  include/acpi/acpigen.h | 72 ++++++++++++++++++++++++++++++++++++++
>  lib/acpi/acpigen.c     | 49 ++++++++++++++++++++++++++
>  test/dm/acpigen.c      | 78 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 199 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 15/43] sound: Add an ACPI driver for Dialog Semicondutor da7219

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> This chip is used on coral and we need to generate ACPI tables for sound
> to make it work. Add a driver that does just this (i.e. at present does
> not actually support playing sound).
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v1:
> - Use acpi,ddn instead of acpi,desc
> - Add a check for invalid node
> - Add NHLT support
> - Capitalise ACPI_OPS_PTR
> - Rebase to master
>
>  configs/sandbox_defconfig                 |   1 +
>  doc/device-tree-bindings/sound/da7219.txt | 113 +++++++++++++
>  drivers/sound/Kconfig                     |   9 ++
>  drivers/sound/Makefile                    |   1 +
>  drivers/sound/da7219.c                    | 189 ++++++++++++++++++++++
>  5 files changed, 313 insertions(+)
>  create mode 100644 doc/device-tree-bindings/sound/da7219.txt
>  create mode 100644 drivers/sound/da7219.c
>
> diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
> index cb6b4b0ee7..6368e278f2 100644
> --- a/configs/sandbox_defconfig
> +++ b/configs/sandbox_defconfig
> @@ -202,6 +202,7 @@ CONFIG_SANDBOX_SERIAL=y
>  CONFIG_SMEM=y
>  CONFIG_SANDBOX_SMEM=y
>  CONFIG_SOUND=y
> +CONFIG_SOUND_DA7219=y
>  CONFIG_SOUND_SANDBOX=y
>  CONFIG_SANDBOX_SPI=y
>  CONFIG_SPMI=y
> diff --git a/doc/device-tree-bindings/sound/da7219.txt b/doc/device-tree-bindings/sound/da7219.txt
> new file mode 100644
> index 0000000000..5fd8a9f1e7
> --- /dev/null
> +++ b/doc/device-tree-bindings/sound/da7219.txt
> @@ -0,0 +1,113 @@
> +Dialog Semiconductor DA7219 Audio Codec bindings
> +
> +DA7219 is an audio codec with advanced accessory detect features.
> +
> +======
> +
> +Required properties:
> +- compatible : Should be "dlg,da7219"
> +- reg: Specifies the I2C slave address
> +
> +- interrupts : IRQ line info for DA7219.
> +  (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
> +   further information relating to interrupt properties)
> +
> +- VDD-supply: VDD power supply for the device
> +- VDDMIC-supply: VDDMIC power supply for the device
> +- VDDIO-supply: VDDIO power supply for the device
> +  (See Documentation/devicetree/bindings/regulator/regulator.txt for further
> +   information relating to regulators)
> +
> +Optional properties:
> +- interrupt-names : Name associated with interrupt line. Should be "wakeup" if
> +  interrupt is to be used to wake system, otherwise "irq" should be used.
> +- wakeup-source: Flag to indicate this device can wake system (suspend/resume).
> +
> +- #clock-cells :  Should be set to '<0>', only one clock source provided;
> +- clock-output-names : Name given for DAI clocks output;
> +
> +- clocks : phandle and clock specifier for codec MCLK.
> +- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
> +
> +- dlg,micbias-lvl : Voltage (mV) for Mic Bias
> +       [<1600>, <1800>, <2000>, <2200>, <2400>, <2600>]
> +- dlg,mic-amp-in-sel : Mic input source type
> +       ["diff", "se_p", "se_n"]
> +- dlg,mclk-name : String name of MCLK for ACPI
> +
> +Deprecated properties:
> +- dlg,ldo-lvl : Required internal LDO voltage (mV) level for digital engine
> +  (LDO unavailable in production HW so property no longer required).
> +
> +======
> +
> +Child node - 'da7219_aad':
> +
> +Optional properties:
> +- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
> +       [<2800>, <2900>]
> +- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
> +- dlg,btn-cfg : Periodic button press measurements for 4-pole jack (ms)
> +       [<2>, <5>, <10>, <50>, <100>, <200>, <500>]
> +- dlg,mic-det-thr : Impedance threshold for mic detection measurement (Ohms)
> +       [<200>, <500>, <750>, <1000>]
> +- dlg,jack-ins-deb : Debounce time for jack insertion (ms)
> +       [<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>]
> +- dlg,jack-det-rate: Jack type detection latency (3/4 pole)
> +       ["32ms_64ms", "64ms_128ms", "128ms_256ms", "256ms_512ms"]
> +- dlg,jack-rem-deb : Debounce time for jack removal (ms)
> +       [<1>, <5>, <10>, <20>]
> +- dlg,a-d-btn-thr : Impedance threshold between buttons A and D
> +       [0x0 - 0xFF]
> +- dlg,d-b-btn-thr : Impedance threshold between buttons D and B
> +       [0x0 - 0xFF]
> +- dlg,b-c-btn-thr : Impedance threshold between buttons B and C
> +       [0x0 - 0xFF]
> +- dlg,c-mic-btn-thr : Impedance threshold between button C and Mic
> +       [0x0 - 0xFF]
> +- dlg,btn-avg : Number of 8-bit readings for averaged button measurement
> +       [<1>, <2>, <4>, <8>]
> +- dlg,adc-1bit-rpt : Repeat count for 1-bit button measurement
> +       [<1>, <2>, <4>, <8>]
> +
> +======
> +
> +Example:
> +
> +       codec: da7219 at 1a {
> +               compatible = "dlg,da7219";
> +               reg = <0x1a>;
> +
> +               interrupt-parent = <&gpio6>;
> +               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
> +
> +               VDD-supply = <&reg_audio>;
> +               VDDMIC-supply = <&reg_audio>;
> +               VDDIO-supply = <&reg_audio>;
> +
> +               #clock-cells = <0>;
> +               clock-output-names = "dai-clks";
> +
> +               clocks = <&clks 201>;
> +               clock-names = "mclk";
> +
> +               dlg,ldo-lvl = <1200>;
> +               dlg,micbias-lvl = <2600>;
> +               dlg,mic-amp-in-sel = "diff";
> +
> +               da7219_aad {
> +                       dlg,btn-cfg = <50>;
> +                       dlg,mic-det-thr = <500>;
> +                       dlg,jack-ins-deb = <20>;
> +                       dlg,jack-det-rate = "32ms_64ms";
> +                       dlg,jack-rem-deb = <1>;
> +
> +                       dlg,a-d-btn-thr = <0xa>;
> +                       dlg,d-b-btn-thr = <0x16>;
> +                       dlg,b-c-btn-thr = <0x21>;
> +                       dlg,c-mic-btn-thr = <0x3E>;
> +
> +                       dlg,btn-avg = <4>;
> +                       dlg,adc-1bit-rpt = <1>;
> +               };
> +       };
> diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
> index 4ebc719be2..7f214b97be 100644
> --- a/drivers/sound/Kconfig
> +++ b/drivers/sound/Kconfig
> @@ -40,6 +40,15 @@ config I2S_SAMSUNG
>           option provides an implementation for sound_init() and
>           sound_play().
>
> +config SOUND_DA7219
> +       bool "Dialog Semiconductor audio codec"
> +       depends on SOUND
> +       help
> +         The DA7219 is an ultra-low-power audio codec with Advanced Accessory
> +         Detection (AAD). This driver only supports generation of ACPI tables.
> +         It does not support sound output or any of the other codec
> +         features.
> +
>  config SOUND_I8254
>         bool "Intel i8254 timer / beeper"
>         depends on SOUND
> diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
> index 73ed7fe53c..8c3933ad15 100644
> --- a/drivers/sound/Makefile
> +++ b/drivers/sound/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_SOUND)     += sound.o
>  obj-$(CONFIG_SOUND)    += codec-uclass.o
>  obj-$(CONFIG_SOUND)    += i2s-uclass.o
>  obj-$(CONFIG_SOUND)    += sound-uclass.o
> +obj-$(CONFIG_SOUND_DA7219)     += da7219.o
>  obj-$(CONFIG_I2S_SAMSUNG)      += samsung-i2s.o
>  obj-$(CONFIG_SOUND_SANDBOX)    += sandbox.o
>  obj-$(CONFIG_I2S_ROCKCHIP)     += rockchip_i2s.o rockchip_sound.o
> diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c
> new file mode 100644
> index 0000000000..454e2591ed
> --- /dev/null
> +++ b/drivers/sound/da7219.c
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * ACPI driver for DA7219 codec
> + *
> + * Copyright 2019 Google LLC
> + * Parts taken from coreboot
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <i2c.h>
> +#include <irq.h>
> +#include <log.h>
> +#include <acpi/acpigen.h>
> +#include <acpi/acpi_device.h>
> +#include <acpi/acpi_dp.h>
> +#ifdef CONFIG_X86
> +#include <asm/acpi_nhlt.h>
> +#endif
> +#include <asm-generic/gpio.h>
> +#include <dt-bindings/sound/nhlt.h>
> +#include <dm/acpi.h>
> +
> +#define DA7219_ACPI_HID                "DLGS7219"
> +
> +static int da7219_acpi_fill_ssdt(const struct udevice *dev,
> +                                struct acpi_ctx *ctx)
> +{
> +       char scope[ACPI_PATH_MAX];
> +       char name[ACPI_NAME_MAX];
> +       struct acpi_dp *dsd, *aad;
> +       ofnode node;
> +       u32 val;
> +       int ret;
> +
> +       ret = acpi_device_scope(dev, scope, sizeof(scope));
> +       if (ret)
> +               return log_msg_ret("scope", ret);
> +       ret = acpi_get_name(dev, name);
> +       if (ret)
> +               return log_msg_ret("name", ret);
> +
> +       /* Device */
> +       acpigen_write_scope(ctx, scope);
> +       acpigen_write_device(ctx, name);
> +       acpigen_write_name_string(ctx, "_HID", DA7219_ACPI_HID);
> +       acpigen_write_name_integer(ctx, "_UID", 1);
> +       acpigen_write_name_string(ctx, "_DDN",
> +                                 dev_read_string(dev, "acpi,ddn"));
> +       acpigen_write_name_integer(ctx, "_S0W", 4);
> +       acpigen_write_sta(ctx, acpi_device_status(dev));
> +
> +       /* Resources */
> +       acpigen_write_name(ctx, "_CRS");
> +       acpigen_write_resourcetemplate_header(ctx);
> +       ret = acpi_device_write_i2c_dev(ctx, dev);
> +       if (ret)
> +               return log_msg_ret("i2c", ret);
> +
> +       /* Use either Interrupt() or GpioInt() */
> +       ret = acpi_device_write_interrupt_or_gpio(ctx, (struct udevice *)dev,
> +                                                 "req-gpios");
> +       if (ret)
> +               return log_msg_ret("irq_gpio", ret);
> +       acpigen_write_resourcetemplate_footer(ctx);
> +
> +       /* AAD Child Device Properties */
> +       aad = acpi_dp_new_table("DAAD");
> +       if (!aad)
> +               return log_msg_ret("aad", -ENOMEM);
> +
> +       node = ofnode_find_subnode(dev_ofnode(dev), "da7219_aad");
> +       if (!ofnode_valid(node))
> +               return log_msg_ret("da7219_aad", -EINVAL);
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,btn-cfg");
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,mic-det-thr");
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,jack-ins-deb");
> +       acpi_dp_ofnode_copy_str(node, aad, "dlg,jack-det-rate");
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,jack-rem-deb");
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,a-d-btn-thr");
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,d-b-btn-thr");
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,b-c-btn-thr");
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,c-mic-btn-thr");
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,btn-avg");
> +       acpi_dp_ofnode_copy_int(node, aad, "dlg,adc-1bit-rpt");
> +       if (!ofnode_read_u32(node, "dlg,micbias-pulse-lvl", &val)) {
> +               acpi_dp_ofnode_copy_int(node, aad, "dlg,micbias-pulse-lvl");
> +               acpi_dp_ofnode_copy_int(node, aad, "dlg,micbias-pulse-time");
> +       }
> +
> +       /* DA7219 Properties */
> +       dsd = acpi_dp_new_table("_DSD");
> +       if (!dsd)
> +               return log_msg_ret("dsd", -ENOMEM);
> +       acpi_dp_dev_copy_int(dev, dsd, "dlg,micbias-lvl");
> +       acpi_dp_dev_copy_str(dev, dsd, "dlg,mic-amp-in-sel");
> +       acpi_dp_dev_copy_str(dev, dsd, "dlg,mclk-name");
> +       acpi_dp_add_child(dsd, "da7219_aad", aad);
> +
> +       /* Write Device Property Hierarchy */
> +       acpi_dp_write(ctx, dsd);
> +
> +       acpigen_pop_len(ctx); /* Device */
> +       acpigen_pop_len(ctx); /* Scope */
> +
> +       return 0;
> +}
> +
> +#ifdef CONFIG_X86

Is the following not applied to non-x86 board?

> +static const struct nhlt_format_config da7219_formats[] = {
> +       /* 48 KHz 24-bits per sample. */
> +       {
> +               .num_channels = 2,
> +               .sample_freq_khz = 48,
> +               .container_bits_per_sample = 32,
> +               .valid_bits_per_sample = 24,
> +               .settings_file = "dialog-2ch-48khz-24b.dat",
> +       },
> +};
> +
> +static const struct nhlt_tdm_config tdm_config = {
> +       .virtual_slot = 0,
> +       .config_type = NHLT_TDM_BASIC,
> +};
> +
> +static const struct nhlt_endp_descriptor da7219_descriptors[] = {
> +       /* Render Endpoint */
> +       {
> +               .link = NHLT_LINK_SSP,
> +               .device = NHLT_SSP_DEV_I2S,
> +               .direction = NHLT_DIR_RENDER,
> +               .vid = NHLT_VID,
> +               .did = NHLT_DID_SSP,
> +               .cfg = &tdm_config,
> +               .cfg_size = sizeof(tdm_config),
> +               .formats = da7219_formats,
> +               .num_formats = ARRAY_SIZE(da7219_formats),
> +       },
> +       /* Capture Endpoint */
> +       {
> +               .link = NHLT_LINK_SSP,
> +               .device = NHLT_SSP_DEV_I2S,
> +               .direction = NHLT_DIR_CAPTURE,
> +               .vid = NHLT_VID,
> +               .did = NHLT_DID_SSP,
> +               .cfg = &tdm_config,
> +               .cfg_size = sizeof(tdm_config),
> +               .formats = da7219_formats,
> +               .num_formats = ARRAY_SIZE(da7219_formats),
> +       },
> +};
> +
> +static int da7219_acpi_setup_nhlt(const struct udevice *dev,
> +                                 struct acpi_ctx *ctx)
> +{
> +       u32 hwlink;
> +       int ret;
> +
> +       if (dev_read_u32(dev, "acpi,audio-link", &hwlink))
> +               return log_msg_ret("link", -EINVAL);
> +
> +       /* Virtual bus id of SSP links are the hardware port ids proper. */
> +       ret = nhlt_add_ssp_endpoints(ctx->nhlt, hwlink, da7219_descriptors,

Where is this nhlt_add_ssp_endpoints() defined?

> +                                    ARRAY_SIZE(da7219_descriptors));
> +       if (ret)
> +               return log_msg_ret("add", ret);
> +
> +       return 0;
> +}
> +#endif
> +
> +struct acpi_ops da7219_acpi_ops = {
> +       .fill_ssdt      = da7219_acpi_fill_ssdt,
> +#ifdef CONFIG_X86
> +       .setup_nhlt     = da7219_acpi_setup_nhlt,
> +#endif
> +};
> +
> +static const struct udevice_id da7219_ids[] = {
> +       { .compatible = "dlg,da7219" },
> +       { }
> +};
> +
> +U_BOOT_DRIVER(da7219) = {
> +       .name           = "da7219",
> +       .id             = UCLASS_MISC,
> +       .of_match       = da7219_ids,
> +       ACPI_OPS_PTR(&da7219_acpi_ops)
> +};
> --

Regards,
Bin

[PATCH v1 17/43] x86: pinctrl: Add a way to get the pinctrl reg address

[Bin Meng]

On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
>
> At present we can query the offset of a pinctrl register within the p2sb.
> For ACPI we need to get the actual address of the register. Add a function
> to handle this and rename the old one to more accurately reflect its
> purpose.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/intel_pinctrl.h | 16 ++++++++++++++--
>  drivers/gpio/intel_gpio.c            | 15 +++++++++++----
>  drivers/misc/p2sb-uclass.c           | 16 ++++++++--------
>  drivers/pinctrl/intel/pinctrl.c      | 11 +++++++++--
>  include/p2sb.h                       |  9 +++++++++
>  5 files changed, 51 insertions(+), 16 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 18/43] x86: pinctrl: Update comment for intel_pinctrl_get_pad()

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add information about what is returned on error.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/intel_pinctrl.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
> index f39ebde539..982b2514a0 100644
> --- a/arch/x86/include/asm/intel_pinctrl.h
> +++ b/arch/x86/include/asm/intel_pinctrl.h
> @@ -300,6 +300,7 @@ u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
>   * @pad: Pad to check
>   * @devp: Returns pinctrl device containing that pad
>   * @offsetp: Returns offset of pad within that pinctrl device
> + * @return 0 if OK, -ENOTBLK if pad number is invalid

It's weird that ENOTBLK is used for a pinctrl.

>   */
>  int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp);
>
> --

Regards,
Bin

[PATCH v1 19/43] x86: pinctrl: Add multi-ACPI control

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add a Kconfig to control whether pinctrl is represented as a single ACPI
> device or as multiple devices. In the latter case (the default) we should
> return the pin number relative to the pinctrl device.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/pinctrl/intel/Kconfig   | 4 ++++
>  drivers/pinctrl/intel/pinctrl.c | 2 ++
>  2 files changed, 6 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 20/43] x86: pinctrl: Set up itss in the probe() method

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> At present the itss is probed in the ofdata_to_platdata() method. This is
> incorrect since itss is a child of p2sb which itself needs to probe the
> pinctrl device. This means that p2sb is effectively not probed when the
> itss is probed, so we get the wrong register address from p2sb.
>

I wonder how this ever worked?

> Fix this by moving the itss probe to the correct place.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/pinctrl/intel/pinctrl.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Regards,
Bin

[PATCH v1 23/43] x86: Add error checking for csrt table generation

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Generation of this table can fail, so update the function to return an
> error code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v1:
> - Add new patch to add error checking for csrt table generation
>
>  arch/x86/lib/acpi_table.c | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 24/43] x86: apl: Use memory-mapped access for VBT

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Use the new binman memory-mapping function to access the VBT, to simplify
> the code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/apollolake/fsp_s.c      | 19 +++++--------------
>  arch/x86/lib/fsp2/fsp_silicon_init.c |  1 +
>  2 files changed, 6 insertions(+), 14 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 25/43] x86: gpio: Add support for obtaining ACPI info for a GPIO

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Implement the method that converts a GPIO into the form used by ACPI, so
> that GPIOs can be added to ACPI tables.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v1:
> - Use acpi_get_path() to get device path
>
>  drivers/gpio/intel_gpio.c | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
>
> diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c
> index b4d5be97da..6a3a8c4cfa 100644
> --- a/drivers/gpio/intel_gpio.c
> +++ b/drivers/gpio/intel_gpio.c
> @@ -12,6 +12,7 @@
>  #include <pch.h>
>  #include <pci.h>
>  #include <syscon.h>
> +#include <acpi/acpi_device.h>
>  #include <asm/cpu.h>
>  #include <asm/gpio.h>
>  #include <asm/intel_pinctrl.h>
> @@ -19,6 +20,7 @@
>  #include <asm/io.h>
>  #include <asm/pci.h>
>  #include <asm/arch/gpio.h>
> +#include <dm/acpi.h>
>  #include <dt-bindings/gpio/x86-gpio.h>
>
>  static int intel_gpio_direction_input(struct udevice *dev, uint offset)
> @@ -128,6 +130,35 @@ static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
>         return 0;
>  }
>
> +#if CONFIG_IS_ENABLED(ACPIGEN)
> +static int intel_gpio_get_acpi(const struct gpio_desc *desc,
> +                              struct acpi_gpio *gpio)
> +{
> +       struct udevice *pinctrl;
> +       int ret;
> +
> +       if (!dm_gpio_is_valid(desc))
> +               return -ENOENT;
> +       pinctrl = dev_get_parent(desc->dev);
> +
> +       memset(gpio, '\0', sizeof(*gpio));
> +
> +       gpio->type = ACPI_GPIO_TYPE_IO;
> +       gpio->pull = ACPI_GPIO_PULL_DEFAULT;
> +       gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
> +       gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;

Is there a way to figure out these properties from DT, instead of hardcoding?

> +       gpio->pin_count = 1;
> +       gpio->pins[0] = intel_pinctrl_get_acpi_pin(pinctrl, desc->offset);
> +       gpio->pin0_addr = intel_pinctrl_get_config_reg_addr(pinctrl,
> +                                                           desc->offset);
> +       ret = acpi_get_path(pinctrl, gpio->resource, sizeof(gpio->resource));
> +       if (ret)
> +               return log_msg_ret("resource", ret);
> +
> +       return 0;
> +}
> +#endif
> +
>  static int intel_gpio_probe(struct udevice *dev)
>  {
>         return 0;
> @@ -152,6 +183,9 @@ static const struct dm_gpio_ops gpio_intel_ops = {
>         .set_value              = intel_gpio_set_value,
>         .get_function           = intel_gpio_get_function,
>         .xlate                  = intel_gpio_xlate,
> +#if CONFIG_IS_ENABLED(ACPIGEN)
> +       .get_acpi               = intel_gpio_get_acpi,
> +#endif
>  };
>
>  static const struct udevice_id intel_intel_gpio_ids[] = {
> --

Regards,
Bin

[PATCH v1 26/43] i2c: designware_i2c: Add a little more debugging

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add debugging for a few more values and also use log to show return values
> when something goes wrong. This makes it easier to see the root cause.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v1:
> - Add new patch to improve designware_i2c debugging
>
>  drivers/i2c/designware_i2c.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 27/43] i2c: Add log_ret() on error

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add a few of these calls to make it easier to see where an error occurs,
> if CONFIG_LOG_ERROR_RETURN is enabled.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/i2c/i2c-uclass.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 29/43] p2sb: Add a method to hide the bus

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> The P2SB bus needs to be hidden in some cases so that it does not get
> auto-configured by Linux. Add a method for this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/misc/p2sb-uclass.c | 10 ++++++++++
>  include/p2sb.h             | 25 ++++++++++++++++++++++++-
>  2 files changed, 34 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 30/43] x86: apl: Support set_hide() in p2sb driver

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add support for this new method in the driver and in the fsp-s setup.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/apollolake/fsp_s.c  | 26 +++++++++++---------------
>  arch/x86/cpu/intel_common/p2sb.c | 30 ++++++++++++++++++++++++++++++
>  2 files changed, 41 insertions(+), 15 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 31/43] x86: apl: Hide the p2sb on exit from U-Boot

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> This confuses Linux's PCI probing so needs to be hidden when booting
> Linux. Add a remove() method to handle this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/intel_common/p2sb.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 32/43] pmc: Move common registers to the header file

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> These registers need to be accesses from ACPI code, so move them to the
> header file.
>

I don't think these are common offset to every platform.

> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  drivers/power/acpi_pmc/acpi-pmc-uclass.c |  9 ---------
>  include/power/acpi_pmc.h                 | 14 ++++++++++++++
>  2 files changed, 14 insertions(+), 9 deletions(-)
>

Regards,
Bin

[PATCH v1 33/43] x86: irq: Support flags for acpi_gpe

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> This binding currently has a flags cell but it is not used. Make use of it
> to create ACPI tables for interrupts.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/acpi_gpe.c                       | 26 +++++++++++++++++++
>  .../interrupt-controller/x86-irq.h            | 14 ++++++++++
>  2 files changed, 40 insertions(+)
>  create mode 100644 include/dt-bindings/interrupt-controller/x86-irq.h
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 34/43] x86: apl: Fix save/restore of ITSS priorities

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> The FSP-S changes the ITSS priorities. The code that tries to save it
> before running FSP-S and restore it afterwards does not work as U-Boot
> relocates in between the save and restore. This means that the driver
> data saved before relocation is lost and the new driver just sees zeroes.
>
> Fix this by allocating space in the relocated memory for the ITSS data.
> Save it there and access it from the driver after relocation.
>
> This fixes interrupt handling on coral.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/apollolake/fsp_s.c    | 11 +++++------
>  arch/x86/cpu/cpu.c                 | 13 +++++++++++++
>  arch/x86/cpu/intel_common/itss.c   | 25 +++++++++++++++++++++++--
>  arch/x86/include/asm/global_data.h |  1 +
>  arch/x86/include/asm/itss.h        |  2 +-
>  drivers/misc/irq-uclass.c          |  2 +-
>  6 files changed, 44 insertions(+), 10 deletions(-)
>
> diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
> index 3a54297a28..e54b0ac104 100644
> --- a/arch/x86/cpu/apollolake/fsp_s.c
> +++ b/arch/x86/cpu/apollolake/fsp_s.c
> @@ -160,11 +160,6 @@ int arch_fsps_preinit(void)
>         ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
>         if (ret)
>                 return log_msg_ret("no itss", ret);
> -       /*
> -        * Snapshot the current GPIO IRQ polarities. FSP is setting a default
> -        * policy that doesn't honour boards' requirements
> -        */
> -       irq_snapshot_polarities(itss);
>
>         /*
>          * Clear the GPI interrupt status and enable registers. These
> @@ -203,7 +198,11 @@ int arch_fsp_init_r(void)
>         ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
>         if (ret)
>                 return log_msg_ret("no itss", ret);
> -       /* Restore GPIO IRQ polarities back to previous settings */
> +
> +       /*
> +        * Restore GPIO IRQ polarities back to previous settings. This was
> +        * stored in reserve_arch() - see X86_IRQT_ITSS
> +        */
>         irq_restore_polarities(itss);
>
>         /* soc_init() */
> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
> index baa7dae172..9bc243ebc8 100644
> --- a/arch/x86/cpu/cpu.c
> +++ b/arch/x86/cpu/cpu.c
> @@ -25,6 +25,7 @@
>  #include <dm.h>
>  #include <errno.h>
>  #include <init.h>
> +#include <irq.h>
>  #include <log.h>
>  #include <malloc.h>
>  #include <syscon.h>
> @@ -274,6 +275,9 @@ int cpu_init_r(void)
>  #ifndef CONFIG_EFI_STUB
>  int reserve_arch(void)
>  {
> +       struct udevice *itss;
> +       int ret;
> +
>         if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
>                 mrccache_reserve();
>
> @@ -291,6 +295,15 @@ int reserve_arch(void)
>                         fsp_save_s3_stack();
>                 }
>         }
> +       ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
> +       if (!ret) {
> +               /*
> +                * Snapshot the current GPIO IRQ polarities. FSP-S is about to
> +                * run and will set a default policy that doesn't honour boards'
> +                * requirements
> +                */
> +               irq_snapshot_polarities(itss);
> +       }
>
>         return 0;
>  }
> diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c
> index 963afa8f5b..fe84ebe29f 100644
> --- a/arch/x86/cpu/intel_common/itss.c
> +++ b/arch/x86/cpu/intel_common/itss.c
> @@ -65,14 +65,23 @@ static int snapshot_polarities(struct udevice *dev)
>         int i;
>
>         reg_start = start / IRQS_PER_IPC;
> -       reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
> +       reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
>
> +       log_info("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot);
>         for (i = reg_start; i < reg_end; i++) {
>                 uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
>
>                 priv->irq_snapshot[i] = pcr_read32(dev, reg);
> +               log_debug("   - %d, reg %x: irq_snapshot[i] %x\n", i, reg,
> +                         priv->irq_snapshot[i]);
>         }
>
> +       /* Save the snapshot for use after relocation */
> +       gd->start_addr_sp -= sizeof(*priv);
> +       gd->start_addr_sp &= ~0xf;
> +       gd->arch.itss_priv = (void *)gd->start_addr_sp;
> +       memcpy(gd->arch.itss_priv, priv, sizeof(*priv));
> +
>         return 0;
>  }
>
> @@ -91,16 +100,26 @@ static void show_polarities(struct udevice *dev, const char *msg)
>  static int restore_polarities(struct udevice *dev)
>  {
>         struct itss_priv *priv = dev_get_priv(dev);
> +       struct itss_priv *old_priv;
>         const int start = GPIO_IRQ_START;
>         const int end = GPIO_IRQ_END;
>         int reg_start;
>         int reg_end;
>         int i;
>
> +       /* Get the snapshot which was stored by the pre-reloc device */
> +       old_priv = gd->arch.itss_priv;
> +       if (!old_priv)
> +               return log_msg_ret("priv", -EFAULT);
> +       memcpy(priv->irq_snapshot, old_priv->irq_snapshot,
> +              sizeof(priv->irq_snapshot));
> +
>         show_polarities(dev, "Before");
> +       log_info("priv->irq_snapshot %p\n", priv->irq_snapshot);
>
>         reg_start = start / IRQS_PER_IPC;
> -       reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
> +       reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
> +
>
>         for (i = reg_start; i < reg_end; i++) {
>                 u32 mask;
> @@ -125,6 +144,8 @@ static int restore_polarities(struct udevice *dev)
>                 mask &= ~((1U << irq_start) - 1);
>
>                 reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
> +               log_debug("   - %d, reg %x: mask %x, irq_snapshot[i] %x\n",
> +                         i, reg, mask, priv->irq_snapshot[i]);
>                 pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
>         }
>
> diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
> index 0e64c8a46d..5bc251c0dd 100644
> --- a/arch/x86/include/asm/global_data.h
> +++ b/arch/x86/include/asm/global_data.h
> @@ -121,6 +121,7 @@ struct arch_global_data {
>  #ifdef CONFIG_FSP_VERSION2
>         struct fsp_header *fsp_s_hdr;   /* Pointer to FSP-S header */
>  #endif
> +       void *itss_priv;                /* Private ITSS data pointer */
>         ulong acpi_start;               /* Start address of ACPI tables */
>  };
>
> diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h
> index c75d8fe8c2..f7d3240384 100644
> --- a/arch/x86/include/asm/itss.h
> +++ b/arch/x86/include/asm/itss.h
> @@ -16,7 +16,7 @@
>
>  #define ITSS_MAX_IRQ   119
>  #define IRQS_PER_IPC   32
> -#define NUM_IPC_REGS   ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC)
> +#define NUM_IPC_REGS   DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC)
>
>  /* Max PXRC registers in ITSS */
>  #define MAX_PXRC_CONFIG        (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
> diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
> index 98bc79eaba..6b32b451a6 100644
> --- a/drivers/misc/irq-uclass.c
> +++ b/drivers/misc/irq-uclass.c
> @@ -170,7 +170,7 @@ int irq_first_device_type(enum irq_dev_t type, struct udevice **devp)
>
>         ret = uclass_first_device_drvdata(UCLASS_IRQ, type, devp);
>         if (ret)
> -               return log_msg_ret("find", ret);
> +               return ret;

Is this change intended?

>
>         return 0;
>  }

Regards,
Bin

[PATCH v1 35/43] x86: Add debugging to table writing

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Writing tables is currently pretty opaque. Add a bit of debugging to the
> process so we can see what tables are written and where they start/end in
> memory.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/lib/tables.c | 38 ++++++++++++++++++++++++++++----------
>  1 file changed, 28 insertions(+), 10 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 37/43] x86: Store the coreboot table address in global_data

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> At present this information is used to locate and parse the tables but is
> not stored. Store it so that we can display it to the user, e.g. with the
> 'bdinfo' command.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/coreboot/tables.c     | 8 +++++++-
>  arch/x86/cpu/i386/cpu.c            | 7 ++++++-
>  arch/x86/include/asm/global_data.h | 1 +
>  3 files changed, 14 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 38/43] x86: mp: Allow use of mp_run_on_cpus() without MP

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> At present if MP is not enabled (e.g. booting from coreboot) the 'mtrr'
> command does not work correctly. It is not easy to make it work for all
> CPUs, since coreboot has halted them and we would need to start them up
> again, but it is easy enough to make them work on the boot CPU.
>
> Update the code to avoid assuming that the MP init routine has completed,
> so that this can work.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/mp_init.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
> index ef33a38017..c0ae24686e 100644
> --- a/arch/x86/cpu/mp_init.c
> +++ b/arch/x86/cpu/mp_init.c
> @@ -454,7 +454,7 @@ static int get_bsp(struct udevice **devp, int *cpu_countp)
>         if (cpu_countp)
>                 *cpu_countp = ret;
>
> -       return dev->req_seq;
> +       return dev->req_seq >= 0 ? dev->req_seq : 0;
>  }
>
>  static struct mp_callback *read_callback(struct mp_callback **slot)
> @@ -589,9 +589,6 @@ int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg)
>         int num_cpus;
>         int ret;
>
> -       if (!(gd->flags & GD_FLG_SMP_INIT))
> -               return -ENXIO;
> -
>         ret = get_bsp(&dev, &num_cpus);
>         if (ret < 0)
>                 return log_msg_ret("bsp", ret);
> @@ -601,6 +598,13 @@ int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg)
>                 func(arg);
>         }
>
> +       if (!(gd->flags & GD_FLG_SMP_INIT)) {
> +               /* Allow use of this function on the BSP only */
> +               if (cpu_select == MP_SELECT_BSP || !cpu_select)

This assumes 0 is the BSP cpu number?

> +                       return 0;
> +               return -ENXIO;
> +       }
> +
>         /* Allow up to 1 second for all APs to finish */
>         ret = run_ap_work(&lcb, dev, num_cpus, 1000 /* ms */);
>         if (ret)
> --

Regards,
Bin

[PATCH v1 39/43] x86: Update the comment about booting for FSP2

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> The comment here applies only to FSP1, so update it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/start.S | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 40/43] x86: Drop setup_pcat_compatibility()

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> This function does not exist anymore. Drop it from the header file.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/u-boot-x86.h | 2 --
>  1 file changed, 2 deletions(-)
>

The function is in zimage.c

./arch/x86/lib/zimage.c:307:void setup_pcat_compatibility(void)
./arch/x86/lib/zimage.c:308:    __attribute__((weak,
alias("__setup_pcat_compatibility")));
./arch/x86/lib/zimage.c:310:void __setup_pcat_compatibility(void)
./arch/x86/lib/zimage.c:327:    setup_pcat_compatibility();

Regards,
Bin

[PATCH v1 41/43] x86: acpi: Correct the version of the MADT

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> Currently U-Boot implements version 2 but reports version 4. Correct it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/lib/acpi_table.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 42/43] x86: Rename board_final_cleanup() to board_final_init()

[Bin Meng]

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> This function sounds like something that is called when U-Boot is about to
> jump to Linux. In fact it is an init function.
>
> Rename it to reduce confusion.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/coreboot/coreboot.c | 4 ++--
>  arch/x86/cpu/cpu.c               | 8 ++++----
>  arch/x86/cpu/efi/app.c           | 2 +-
>  arch/x86/cpu/quark/quark.c       | 2 +-
>  arch/x86/lib/fsp/fsp_common.c    | 2 +-
>  5 files changed, 9 insertions(+), 9 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v1 43/43] acpi: Enable ACPI table generation by default on x86

[Bin Meng]

Hi Simon,

On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
>
> This should ideally be used by all x86 boards in U-Boot. Enable it by
> default. If some boards don't use it, the cost is small.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/Kconfig b/arch/Kconfig
> index a11f872938..650bc0dbca 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -190,6 +190,7 @@ config X86
>         imply PCH
>         imply RTC_MC146818
>         imply IRQ
> +       imply ACPIGEN

if !QEMU ?

>
>         # Thing to enable for when SPL/TPL are enabled: SPL
>         imply SPL_DM
> --

Regards,
Bin

[PATCH v1 33/43] x86: irq: Support flags for acpi_gpe

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----

> Betreff: [PATCH v1 33/43] x86: irq: Support flags for acpi_gpe
> 
> This binding currently has a flags cell but it is not used. Make use of it
> to create ACPI tables for interrupts.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/cpu/acpi_gpe.c                       | 26 +++++++++++++++++++
>  .../interrupt-controller/x86-irq.h            | 14 ++++++++++
>  2 files changed, 40 insertions(+)
>  create mode 100644 include/dt-bindings/interrupt-controller/x86-irq.h
> 

[snip]

> diff --git a/include/dt-bindings/interrupt-controller/x86-irq.h b/include/dt-bindings/interrupt-controller/x86-irq.h
> new file mode 100644
> index 0000000000..9e0b4612e1
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/x86-irq.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2019 Google LLC
> + *
> + * This provides additional flags used by x86.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H
> +
> +#define X86_IRQ_TYPE_SHARED	(1 << 4)
> +#define X86_IRQ_TYPE_WAKE	(1 << 5)

Nit: BIT(4) and BIT(4) ?

> +
> +#endif
> -- 
> 2.27.0.290.gba653c62da-goog

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 37/43] x86: Store the coreboot table address in global_data

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 37/43] x86: Store the coreboot table address in global_data
> 
> At present this information is used to locate and parse the tables but is
> not stored. Store it so that we can display it to the user, e.g. with the
> 'bdinfo' command.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/cpu/coreboot/tables.c     | 8 +++++++-
>  arch/x86/cpu/i386/cpu.c            | 7 ++++++-
>  arch/x86/include/asm/global_data.h | 1 +
>  3 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
> index a5d31d1dea..1594b4a8b2 100644
> --- a/arch/x86/cpu/coreboot/tables.c
> +++ b/arch/x86/cpu/coreboot/tables.c
> @@ -10,6 +10,8 @@
>  #include <net.h>
>  #include <asm/arch/sysinfo.h>
>  
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  /*
>   * This needs to be in the .data section so that it's copied over during
>   * relocation. By default it's put in the .bss section which is simply filled
> @@ -243,6 +245,10 @@ int get_coreboot_info(struct sysinfo_t *info)
>  	if (addr < 0)
>  		return addr;
>  	ret = cb_parse_header((void *)addr, 0x1000, info);
> +	if (!ret)
> +		return -ENOENT;
> +	gd->arch.coreboot_table = addr;
> +	gd->flags |= GD_FLG_SKIP_LL_INIT;

Why is GD_FLG_SKIP_LL_INIT now set in get_coreboot_info()?

>  
> -	return ret == 1 ? 0 : -ENOENT;
> +	return 0;
>  }
> diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
> index fca3f79b69..8f342dd06e 100644
> --- a/arch/x86/cpu/i386/cpu.c
> +++ b/arch/x86/cpu/i386/cpu.c
> @@ -456,10 +456,15 @@ int x86_cpu_init_f(void)
>  
>  int x86_cpu_reinit_f(void)
>  {
> +	long addr;
> +
>  	setup_identity();
>  	setup_pci_ram_top();
> -	if (locate_coreboot_table() >= 0)
> +	addr = locate_coreboot_table();
> +	if (addr >= 0) {
> +		gd->arch.coreboot_table = addr;
>  		gd->flags |= GD_FLG_SKIP_LL_INIT;
> +	}
>  
>  	return 0;
>  }
> diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
> index 5bc251c0dd..3e4044593c 100644
> --- a/arch/x86/include/asm/global_data.h
> +++ b/arch/x86/include/asm/global_data.h
> @@ -123,6 +123,7 @@ struct arch_global_data {
>  #endif
>  	void *itss_priv;		/* Private ITSS data pointer */
>  	ulong acpi_start;		/* Start address of ACPI tables */
> +	ulong coreboot_table;		/* Address of coreboot table */
>  };
>  
>  #endif
> -- 
> 2.27.0.290.gba653c62da-goog

regards, Wolfgang

[PATCH v1 41/43] x86: acpi: Correct the version of the MADT

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 41/43] x86: acpi: Correct the version of the MADT
> 
> Currently U-Boot implements version 2 but reports version 4. Correct it.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  arch/x86/lib/acpi_table.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
> index b6ba547b6a..6e3276c6f6 100644
> --- a/arch/x86/lib/acpi_table.c
> +++ b/arch/x86/lib/acpi_table.c
> @@ -155,7 +155,7 @@ static void acpi_create_madt(struct acpi_madt *madt)
>  	/* Fill out header fields */
>  	acpi_fill_header(header, "APIC");
>  	header->length = sizeof(struct acpi_madt);
> -	header->revision = 4;
> +	header->revision = 2;

Nit:
Commit 91fe8b79f691 ("acpi: Add a central location for table version number")
has introduced defines for the different MADT revision numbers in
include/acpi/acpi_table.h, e.g. ACPI_MADT_REV_ACPI_3_0 for the value 2.

Could you use this instead of the hardcoded value 2?

>  
>  	madt->lapic_addr = LAPIC_DEFAULT_BASE;
>  	madt->flags = ACPI_MADT_PCAT_COMPAT;
> -- 
> 2.27.0.290.gba653c62da-goog

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 22/43] x86: Add support for building up an NHLT structure

[Wolfgang Wallner]

Hi Simon,

I dont know NHLT well enough to actually review the code, but I did compare
the files in this patch to the version in coreboot. Most of the changes are
obvious (coding style, spelling, ...), but some things are not, see the remarks
below.

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 22/43] x86: Add support for building up an NHLT structure
> 
> The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> audio codecs and connections in a system. Various devices can contribute
> information to produce the table.
> 
> Add functions to allow adding to the structure that is eventually written
> to the ACPI tables. Also add the device-tree bindings.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v1:
> - Add a new patch to support building up an NHLT structure
> 
>  arch/x86/include/asm/acpi_nhlt.h | 314 ++++++++++++++++++++
>  arch/x86/lib/Makefile            |   1 +
>  arch/x86/lib/acpi_nhlt.c         | 482 +++++++++++++++++++++++++++++++
>  3 files changed, 797 insertions(+)
>  create mode 100644 arch/x86/include/asm/acpi_nhlt.h
>  create mode 100644 arch/x86/lib/acpi_nhlt.c
> 
> diff --git a/arch/x86/include/asm/acpi_nhlt.h b/arch/x86/include/asm/acpi_nhlt.h
> new file mode 100644
> index 0000000000..4d2573d5ff
> --- /dev/null
> +++ b/arch/x86/include/asm/acpi_nhlt.h
> @@ -0,0 +1,314 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2020 Google LLC
> + *
> + * Modified from coreboot nhlt.h
> + */
> +
> +#ifndef _NHLT_H_
> +#define _NHLT_H_
> +
> +struct acpi_ctx;
> +struct nhlt;
> +struct nhlt_endpoint;
> +struct nhlt_format;
> +struct nhlt_format_config;
> +
> +/*
> + * Non HD Audio ACPI support. This table is typically used for Intel Smart
> + * Sound Technology DSP. It provides a way to encode opaque settings in
> + * the ACPI tables.
> + *
> + * While the structure fields of the NHLT structs are exposed below
> + * the SoC/chipset code should be the only other user manipulating the
> + * fields directly aside from the library itself.
> + *
> + * The NHLT table consists of endpoints which in turn contain different
> + * supporting stream formats. Each endpoint may contain a device specific
> + * configuration payload as well as each stream format.
> + *
> + * Most code should use the SoC variants of the functions because
> + * there is required logic needed to be performed by the SoC. The SoC
> + * code should be abstracting the inner details of these functions that
> + * specically apply to NHLT objects for that SoC.
> + *
> + * An example sequence:
> + *
> + * nhlt = nhlt_init()
> + * ep = nhlt_add_endpoint()
> + * nhlt_endpoint_append_config(ep)
> + * nhlt_endpoint_add_formats(ep)
> + * nhlt_soc_serialise()
> + */
> +
> +/* Obtain an nhlt object for adding endpoints. Returns NULL on error. */
> +struct nhlt *nhlt_init(void);
> +
> +/* Return the size of the NHLT table including ACPI header. */
> +size_t nhlt_current_size(struct nhlt *nhlt);
> +
> +/*
> + * Helper functions for adding NHLT devices utilizing an nhlt_endp_descriptor
> + * to drive the logic.
> + */
> +
> +struct nhlt_endp_descriptor {
> +	/* NHLT endpoint types. */
> +	int link;
> +	int device;
> +	int direction;
> +	u16 vid;
> +	u16 did;
> +	/* Optional endpoint specific configuration data. */
> +	const void *cfg;
> +	size_t cfg_size;
> +	/* Formats supported for endpoint. */
> +	const struct nhlt_format_config *formats;
> +	size_t num_formats;
> +};
> +
> +/*
> + * Add the number of endpoints described by each descriptor. The virtual bus
> + * id for each descriptor is the default value of 0.
> + * Returns < 0 on error, 0 on success.
> + */
> +int nhlt_add_endpoints(struct nhlt *nhlt,
> +		       const struct nhlt_endp_descriptor *epds,
> +		       size_t num_epds);
> +
> +/*
> + * Add the number of endpoints associated with a single NHLT SSP instance id.
> + * Each endpoint described in the endpoint descriptor array uses the provided
> + * virtual bus id. Returns < 0 on error, 0 on success.
> + */
> +int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id,
> +			   const struct nhlt_endp_descriptor *epds,
> +			   size_t num_epds);
> +
> +/*
> + * Add endpoint to NHLT object. Returns NULL on error.
> + *
> + * generic nhlt_add_endpoint() is called by the SoC code to provide
> + * the specific assumptions/uses for NHLT for that platform. All fields
> + * are the NHLT enumerations found within this header file.
> + */
> +struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type,
> +					int device_type, int dir,
> +					u16 vid, u16 did);
> +
> +/*
> + * Append blob of configuration to the endpoint proper. Returns 0 on
> + * success, < 0 on error. A copy of the configuration is made so any
> + * resources pointed to by config can be freed after the call.
> + */
> +int nhlt_endpoint_append_config(struct nhlt_endpoint *endpoint,
> +				const void *config, size_t config_sz);
> +
> +/* Add a format type to the provided endpoint. Returns NULL on error. */
> +struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endpoint,
> +				    int num_channels, int sample_freq_khz,
> +				    int container_bits_per_sample,
> +				    int valid_bits_per_sample,
> +				    u32 speaker_mask);
> +
> +/*
> + * Append blob of configuration to the format proper. Returns 0 on
> + * success, < 0 on error. A copy of the configuration is made so any
> + * resources pointed to by config can be freed after the call.
> + */
> +int nhlt_format_append_config(struct nhlt_format *format, const void *config,
> +			      size_t config_sz);
> +
> +/*
> + * Add num_formats described by formats to the endpoint. This function
> + * effectively wraps nhlt_add_format() and nhlt_format_config() using the
> + * data found in each nhlt_format_config object. Returns 0 on success, < 0
> + * on error.
> + */
> +int nhlt_endpoint_add_formats(struct nhlt_endpoint *endpoint,
> +			      const struct nhlt_format_config *formats,
> +			      size_t num_formats);
> +
> +/*
> + * Increment the instance id for a given link type. This function is
> + * used for marking a device being completely added to the NHLT object.
> + * Subsequent endpoints added to the nhlt object with the same link type
> + * will use incremented instance id.
> + */
> +void nhlt_next_instance(struct nhlt *nhlt, int link_type);
> +
> +/*
> + * Serialize NHLT object to ACPI table. Take in the beginning address of where
> + * the table will reside and return the address of the next ACPI table. On
> + * error 0 will be returned. The NHLT object is no longer valid after this
> + * function is called.
> + */
> +uintptr_t nhlt_serialise(struct nhlt *nhlt, uintptr_t acpi_addr);

The implementation for this functions seems to be missing in this patch.
In coreboot it looks like this:

uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr)
{
	return nhlt_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL, 0);
}

> +
> +/*
> + * Serialize NHLT object to ACPI table. Take in the beginning address of where
> + * the table will reside oem_id and oem_table_id and return the address of the
> + * next ACPI table. On error 0 will be returned. The NHLT object is no longer
> + * valid after this function is called.
> + */
> +int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt,
> +				 const char *oem_id, const char *oem_table_id,
> +				 u32 oem_revision);
> +
> +int nhlt_setup(struct nhlt *nhlt, ofnode node);
> +
> +/* Link and device types. */
> +enum {
> +	NHLT_LINK_HDA,
> +	NHLT_LINK_DSP,
> +	NHLT_LINK_PDM,
> +	NHLT_LINK_SSP,
> +	NHLT_MAX_LINK_TYPES,
> +};
> +
> +enum {
> +	NHLT_SSP_DEV_BT, /* Bluetooth */
> +	NHLT_SSP_DEV_MODEM,
> +	NHLT_SSP_DEV_FM,
> +	NHLT_SSP_DEV_RESERVED,
> +	NHLT_SSP_DEV_I2S = 4,
> +};
> +
> +enum {
> +	NHLT_PDM_DEV,
> +};
> +
> +/* Endpoint direction. */
> +enum {
> +	NHLT_DIR_RENDER,
> +	NHLT_DIR_CAPTURE,
> +	NHLT_DIR_BIDIRECTIONAL,
> +};
> +
> +/*
> + * Channel mask for an endpoint. While they are prefixed with 'SPEAKER' the
> + * channel masks are also used for capture devices
> + */
> +enum {
> +	SPEAKER_FRONT_LEFT = 1 << 0,

Nit: BIT(0) ?

> +	SPEAKER_FRONT_RIGHT = 1 << 1,
> +	SPEAKER_FRONT_CENTER = 1 << 2,
> +	SPEAKER_LOW_FREQUENCY = 1 << 3,
> +	SPEAKER_BACK_LEFT = 1 << 4,
> +	SPEAKER_BACK_RIGHT = 1 << 5,
> +	SPEAKER_FRONT_LEFT_OF_CENTER = 1 << 6,
> +	SPEAKER_FRONT_RIGHT_OF_CENTER = 1 << 7,
> +	SPEAKER_BACK_CENTER = 1 << 8,
> +	SPEAKER_SIDE_LEFT = 1 << 9,
> +	SPEAKER_SIDE_RIGHT = 1 << 10,
> +	SPEAKER_TOP_CENTER = 1 << 11,
> +	SPEAKER_TOP_FRONT_LEFT = 1 << 12,
> +	SPEAKER_TOP_FRONT_CENTER = 1 << 13,
> +	SPEAKER_TOP_FRONT_RIGHT = 1 << 14,
> +	SPEAKER_TOP_BACK_LEFT = 1 << 15,
> +	SPEAKER_TOP_BACK_CENTER = 1 << 16,
> +	SPEAKER_TOP_BACK_RIGHT = 1 << 17,
> +};
> +
> +/*
> + * Supporting structures. Only SoC/chipset and the library code directly should
> + * be manipulating these structures
> + */
> +struct sub_format {
> +	u32 data1;
> +	u16 data2;
> +	u16 data3;
> +	u8 data4[8];
> +};
> +
> +struct nhlt_specific_config {
> +	u32 size;
> +	void *capabilities;
> +};
> +
> +struct nhlt_waveform {
> +	u16 tag;
> +	u16 num_channels;
> +	u32 samples_per_second;
> +	u32 bytes_per_second;
> +	u16 block_align;
> +	u16 bits_per_sample;
> +	u16 extra_size;
> +	u16 valid_bits_per_sample;
> +	u32 channel_mask;
> +	struct sub_format sub_format;
> +};
> +
> +struct nhlt_format {
> +	struct nhlt_waveform waveform;
> +	struct nhlt_specific_config config;
> +};
> +
> +/*
> + * This struct is used by nhlt_endpoint_add_formats() for easily adding
> + * waveform formats with associated settings file.
> + */
> +struct nhlt_format_config {
> +	int num_channels;
> +	int sample_freq_khz;
> +	int container_bits_per_sample;
> +	int valid_bits_per_sample;
> +	u32 speaker_mask;
> +	const char *settings_file;
> +};
> +
> +/* Arbitrary max number of formats per endpoint. */
> +#define MAX_FORMATS 2
> +struct nhlt_endpoint {
> +	u32 length;
> +	u8 link_type;
> +	u8 instance_id;
> +	u16 vendor_id;
> +	u16 device_id;
> +	u16 revision_id;
> +	u32 subsystem_id;
> +	u8 device_type;
> +	u8 direction;
> +	u8 virtual_bus_id;
> +	struct nhlt_specific_config config;
> +	u8 num_formats;
> +	struct nhlt_format formats[MAX_FORMATS];
> +};
> +
> +#define MAX_ENDPOINTS 8
> +struct nhlt {
> +	u32 subsystem_id;
> +	u8 num_endpoints;
> +	struct nhlt_endpoint endpoints[MAX_ENDPOINTS];
> +	u8 current_instance_id[NHLT_MAX_LINK_TYPES];
> +};
> +
> +struct nhlt_tdm_config {
> +	u8 virtual_slot;
> +	u8 config_type;
> +};
> +
> +enum {
> +	NHLT_TDM_BASIC,
> +	NHLT_TDM_MIC_ARRAY,
> +};
> +
> +struct nhlt_dmic_array_config {
> +	struct nhlt_tdm_config tdm_config;
> +	u8 array_type;
> +};
> +
> +/*
> + * Microphone array definitions may be found here:
> + * https://msdn.microsoft.com/en-us/library/windows/hardware/dn613960%28v=vs.85%29.aspx
> + */
> +enum {
> +	NHLT_MIC_ARRAY_2CH_SMALL = 0xa,
> +	NHLT_MIC_ARRAY_2CH_BIG = 0xb,
> +	NHLT_MIC_ARRAY_4CH_1ST_GEOM = 0xc,
> +	NHLT_MIC_ARRAY_4CH_L_SHAPED = 0xd,
> +	NHLT_MIC_ARRAY_4CH_2ND_GEOM = 0xe,
> +	NHLT_MIC_ARRAY_VENDOR_DEFINED = 0xf,
> +};
> +
> +#endif
> diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
> index 5cd4587480..4f3e9ad6b6 100644
> --- a/arch/x86/lib/Makefile
> +++ b/arch/x86/lib/Makefile
> @@ -23,6 +23,7 @@ obj-y	+= interrupts.o
>  obj-y	+= lpc-uclass.o
>  obj-y	+= mpspec.o
>  obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
> +obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi_nhlt.o
>  obj-y	+= northbridge-uclass.o
>  obj-$(CONFIG_I8259_PIC) += i8259.o
>  obj-$(CONFIG_I8254_TIMER) += i8254.o
> diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c
> new file mode 100644
> index 0000000000..c64dd9c008
> --- /dev/null
> +++ b/arch/x86/lib/acpi_nhlt.c
> @@ -0,0 +1,482 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020 Google LLC
> + *
> + * Modified from coreboot nhlt.c
> + */
> +
> +#define LOG_CATEGORY	LOGC_ACPI
> +
> +#include <common.h>
> +#include <binman.h>
> +#include <dm.h>
> +#include <log.h>
> +#include <malloc.h>
> +#include <tables_csum.h>
> +#include <acpi/acpi_table.h>
> +#include <asm/acpi_nhlt.h>
> +#include <asm/unaligned.h>
> +#include <dm/acpi.h>
> +
> +#define NHLT_RID		1
> +#define NHLT_SSID		1
> +#define WAVEFORMAT_TAG		0xfffe
> +#define DEFAULT_VIRTUAL_BUS_ID	0
> +
> +static const struct sub_format pcm_subformat = {
> +	.data1 = 0x00000001,
> +	.data2 = 0x0000,
> +	.data3 = 0x0010,
> +	.data4 = { 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71 },
> +};
> +
> +struct nhlt *nhlt_init(void)
> +{
> +	struct nhlt *nhlt;
> +
> +	nhlt = malloc(sizeof(*nhlt));
> +
> +	if (!nhlt)
> +		return NULL;
> +
> +	memset(nhlt, 0, sizeof(*nhlt));
> +	nhlt->subsystem_id = NHLT_SSID;
> +
> +	return nhlt;
> +}
> +
> +struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type,
> +					int device_type, int dir,
> +					u16 vid, u16 did)
> +{
> +	struct nhlt_endpoint *endp;
> +
> +	if (link_type < NHLT_LINK_HDA || link_type >= NHLT_MAX_LINK_TYPES)
> +		return NULL;
> +
> +	if (nhlt->num_endpoints >= MAX_ENDPOINTS)
> +		return NULL;
> +
> +	endp = &nhlt->endpoints[nhlt->num_endpoints];
> +
> +	endp->link_type = link_type;
> +	endp->instance_id = nhlt->current_instance_id[link_type];
> +	endp->vendor_id = vid;
> +	endp->device_id = did;
> +	endp->revision_id = NHLT_RID;
> +	endp->subsystem_id = nhlt->subsystem_id;
> +	endp->device_type = device_type;
> +	endp->direction = dir;
> +	endp->virtual_bus_id = DEFAULT_VIRTUAL_BUS_ID;
> +
> +	nhlt->num_endpoints++;
> +
> +	return endp;
> +}
> +
> +static int append_specific_config(struct nhlt_specific_config *spec_cfg,
> +				  const void *config, size_t config_sz)
> +{
> +	size_t new_sz;
> +	void *new_cfg;
> +

In coreboot this function starts with a check of config and config_sz:

if (config == NULL || config_sz == 0)
	return 0;

Why is this check left out in this implementation?

> +	new_sz = spec_cfg->size + config_sz;
> +	new_cfg = malloc(new_sz);
> +	if (!new_cfg)
> +		return -ENOMEM;
> +
> +	/* Append new config */
> +	memcpy(new_cfg, spec_cfg->capabilities, spec_cfg->size);
> +	memcpy(new_cfg + spec_cfg->size, config, config_sz);
> +
> +	free(spec_cfg->capabilities);
> +
> +	/* Update with new config data */
> +	spec_cfg->size = new_sz;
> +	spec_cfg->capabilities = new_cfg;
> +
> +	return 0;
> +}
> +
> +int nhlt_endpoint_append_config(struct nhlt_endpoint *endp, const void *config,
> +				size_t config_sz)
> +{
> +	return append_specific_config(&endp->config, config, config_sz);
> +}
> +
> +struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endp,
> +				    int num_channels, int sample_freq_khz,
> +				    int container_bits_per_sample,
> +				    int valid_bits_per_sample,
> +				    uint32_t speaker_mask)
> +{
> +	struct nhlt_format *fmt;
> +	struct nhlt_waveform *wave;
> +
> +	if (endp->num_formats >= MAX_FORMATS)
> +		return NULL;
> +
> +	fmt = &endp->formats[endp->num_formats];
> +	wave = &fmt->waveform;
> +
> +	wave->tag = WAVEFORMAT_TAG;
> +	wave->num_channels = num_channels;
> +	wave->samples_per_second = sample_freq_khz * 1000;
> +	wave->bits_per_sample = container_bits_per_sample;
> +	wave->extra_size = sizeof(wave->valid_bits_per_sample);
> +	wave->extra_size += sizeof(wave->channel_mask);
> +	wave->extra_size += sizeof(wave->sub_format);
> +	wave->valid_bits_per_sample = valid_bits_per_sample;
> +	wave->channel_mask = speaker_mask;
> +	memcpy(&wave->sub_format, &pcm_subformat, sizeof(wave->sub_format));
> +
> +	/* Calculate the dervied fields */
> +	wave->block_align = wave->num_channels * wave->bits_per_sample / 8;
> +	wave->bytes_per_second = wave->block_align * wave->samples_per_second;
> +
> +	endp->num_formats++;
> +
> +	return fmt;
> +}
> +
> +int nhlt_format_append_config(struct nhlt_format *fmt, const void *config,
> +			      size_t config_sz)
> +{
> +	return append_specific_config(&fmt->config, config, config_sz);
> +}
> +
> +int nhlt_endpoint_add_formats(struct nhlt_endpoint *endp,
> +			      const struct nhlt_format_config *formats,
> +			      size_t num_formats)
> +{
> +	ofnode node;
> +	size_t i;
> +
> +	node = binman_section_find_node("private-files");
> +
> +	for (i = 0; i < num_formats; i++) {
> +		const struct nhlt_format_config *cfg = &formats[i];
> +		struct nhlt_format *fmt;
> +		void *data;
> +		int size;
> +		int ret;
> +
> +		fmt = nhlt_add_format(endp, cfg->num_channels,
> +				      cfg->sample_freq_khz,
> +				      cfg->container_bits_per_sample,
> +				      cfg->valid_bits_per_sample,
> +				      cfg->speaker_mask);
> +		if (!fmt)
> +			return -ENOSPC;
> +
> +		if (!cfg->settings_file)
> +			continue;
> +
> +		ret = binman_entry_map(node, cfg->settings_file, &data, &size);
> +		if (ret) {
> +			log_warning("Failed to find settings file %s\n",
> +				    cfg->settings_file);
> +			return log_msg_ret("settings", ret);
> +		}
> +
> +		ret = nhlt_format_append_config(fmt, data, size);
> +		if (ret)
> +			return log_msg_ret("append", ret);
> +	}
> +
> +	return 0;
> +}
> +
> +void nhlt_next_instance(struct nhlt *nhlt, int link_type)
> +{
> +	if (link_type < NHLT_LINK_HDA || link_type >= NHLT_MAX_LINK_TYPES)
> +		return;
> +
> +	nhlt->current_instance_id[link_type]++;
> +}
> +
> +static size_t calc_specific_config_size(struct nhlt_specific_config *cfg)
> +{
> +	return sizeof(cfg->size) + cfg->size;
> +}
> +
> +static size_t calc_format_size(struct nhlt_format *fmt)
> +{
> +	size_t sz = 0;
> +
> +	/* Wave format first */
> +	sz += sizeof(fmt->waveform.tag);
> +	sz += sizeof(fmt->waveform.num_channels);
> +	sz += sizeof(fmt->waveform.samples_per_second);
> +	sz += sizeof(fmt->waveform.bytes_per_second);
> +	sz += sizeof(fmt->waveform.block_align);
> +	sz += sizeof(fmt->waveform.bits_per_sample);
> +	sz += sizeof(fmt->waveform.extra_size);
> +	sz += sizeof(fmt->waveform.valid_bits_per_sample);
> +	sz += sizeof(fmt->waveform.channel_mask);
> +	sz += sizeof(fmt->waveform.sub_format);
> +
> +	sz += calc_specific_config_size(&fmt->config);
> +
> +	return sz;
> +}
> +
> +static size_t calc_endpoint_size(struct nhlt_endpoint *endp)
> +{
> +	int i;
> +	size_t sz = 0;
> +
> +	sz += sizeof(endp->length) + sizeof(endp->link_type);
> +	sz += sizeof(endp->instance_id) + sizeof(endp->vendor_id);
> +	sz += sizeof(endp->device_id) + sizeof(endp->revision_id);
> +	sz += sizeof(endp->subsystem_id) + sizeof(endp->device_type);
> +	sz += sizeof(endp->direction) + sizeof(endp->virtual_bus_id);
> +	sz += calc_specific_config_size(&endp->config);
> +	sz += sizeof(endp->num_formats);
> +
> +	for (i = 0; i < endp->num_formats; i++)
> +		sz += calc_format_size(&endp->formats[i]);
> +
> +	/* Adjust endpoint length to reflect current configuration */
> +	endp->length = sz;
> +
> +	return sz;
> +}
> +
> +static size_t calc_endpoints_size(struct nhlt *nhlt)
> +{
> +	size_t sz = 0;
> +	int i;
> +
> +	for (i = 0; i < nhlt->num_endpoints; i++)
> +		sz += calc_endpoint_size(&nhlt->endpoints[i]);
> +
> +	return sz;
> +}
> +
> +static size_t calc_size(struct nhlt *nhlt)
> +{
> +	return sizeof(nhlt->num_endpoints) + calc_endpoints_size(nhlt);
> +}
> +
> +size_t nhlt_current_size(struct nhlt *nhlt)
> +{
> +	return calc_size(nhlt) + sizeof(struct acpi_table_header);
> +}
> +
> +static void nhlt_free_resources(struct nhlt *nhlt)
> +{
> +	int i, j;
> +
> +	/* Free all specific configs */
> +	for (i = 0; i < nhlt->num_endpoints; i++) {
> +		struct nhlt_endpoint *endp = &nhlt->endpoints[i];
> +
> +		free(endp->config.capabilities);
> +		for (j = 0; j < endp->num_formats; j++) {
> +			struct nhlt_format *fmt = &endp->formats[j];
> +
> +			free(fmt->config.capabilities);
> +		}
> +	}
> +
> +	/* Free nhlt object proper */
> +	free(nhlt);
> +}
> +
> +struct cursor {
> +	u8 *buf;
> +};
> +
> +static void ser8(struct cursor *cur, uint val)
> +{
> +	*cur->buf = val;
> +	cur->buf += sizeof(val);
> +}
> +
> +static void ser16(struct cursor *cur, uint val)
> +{
> +	put_unaligned_le16(val, cur->buf);
> +	cur->buf += sizeof(val);
> +}
> +
> +static void ser32(struct cursor *cur, uint val)
> +{
> +	put_unaligned_le32(val, cur->buf);
> +	cur->buf += sizeof(val);
> +}
> +
> +static void serblob(struct cursor *cur, void *from, size_t sz)
> +{
> +	memcpy(cur->buf, from, sz);
> +	cur->buf += sz;
> +}
> +
> +static void serialise_specific_config(struct nhlt_specific_config *cfg,
> +				      struct cursor *cur)
> +{
> +	ser32(cur, cfg->size);
> +	serblob(cur, cfg->capabilities, cfg->size);
> +}
> +
> +static void serialise_waveform(struct nhlt_waveform *wave, struct cursor *cur)
> +{
> +	ser16(cur, wave->tag);
> +	ser16(cur, wave->num_channels);
> +	ser32(cur, wave->samples_per_second);
> +	ser32(cur, wave->bytes_per_second);
> +	ser16(cur, wave->block_align);
> +	ser16(cur, wave->bits_per_sample);
> +	ser16(cur, wave->extra_size);
> +	ser16(cur, wave->valid_bits_per_sample);
> +	ser32(cur, wave->channel_mask);
> +	ser32(cur, wave->sub_format.data1);
> +	ser16(cur, wave->sub_format.data2);
> +	ser16(cur, wave->sub_format.data3);
> +	serblob(cur, wave->sub_format.data4, sizeof(wave->sub_format.data4));
> +}
> +
> +static void serialise_format(struct nhlt_format *fmt, struct cursor *cur)
> +{
> +	serialise_waveform(&fmt->waveform, cur);
> +	serialise_specific_config(&fmt->config, cur);
> +}
> +
> +static void serialise_endpoint(struct nhlt_endpoint *endp, struct cursor *cur)
> +{
> +	int i;
> +
> +	ser32(cur, endp->length);
> +	ser8(cur, endp->link_type);
> +	ser8(cur, endp->instance_id);
> +	ser16(cur, endp->vendor_id);
> +	ser16(cur, endp->device_id);
> +	ser16(cur, endp->revision_id);
> +	ser32(cur, endp->subsystem_id);
> +	ser8(cur, endp->device_type);
> +	ser8(cur, endp->direction);
> +	ser8(cur, endp->virtual_bus_id);
> +	serialise_specific_config(&endp->config, cur);
> +	ser8(cur, endp->num_formats);
> +
> +	for (i = 0; i < endp->num_formats; i++)
> +		serialise_format(&endp->formats[i], cur);
> +}
> +
> +static void nhlt_serialise_endpoints(struct nhlt *nhlt, struct cursor *cur)
> +{
> +	int i;
> +
> +	ser8(cur, nhlt->num_endpoints);
> +
> +	for (i = 0; i < nhlt->num_endpoints; i++)
> +		serialise_endpoint(&nhlt->endpoints[i], cur);
> +}
> +
> +int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt,
> +				 const char *oem_id, const char *oem_table_id,
> +				 uint32_t oem_revision)
> +{
> +	struct cursor cur;
> +	struct acpi_table_header *header;
> +	size_t sz;
> +	size_t oem_id_len;
> +	size_t oem_table_id_len;
> +	int ret;
> +
> +	log_info("ACPI:    * NHLT\n");
> +	sz = nhlt_current_size(nhlt);
> +
> +	/* Create header */
> +	header = (void *)ctx->current;
> +	memset(header, '\0', sizeof(struct acpi_table_header));
> +	acpi_fill_header(header, "NHLT");
> +	header->length = sz;
> +	header->revision = acpi_get_table_revision(ACPITAB_NHLT);
> +
> +	if (oem_id) {
> +		oem_id_len = min((int)strlen(oem_id), 6);
> +		memcpy(header->oem_id, oem_id, oem_id_len);
> +	}
> +	if (oem_table_id) {
> +		oem_table_id_len = min((int)strlen(oem_table_id), 8);
> +		memcpy(header->oem_table_id, oem_table_id, oem_table_id_len);
> +	}
> +	header->oem_revision = oem_revision;
> +
> +	cur.buf = (void *)(header + 1);
> +	nhlt_serialise_endpoints(nhlt, &cur);
> +
> +	header->checksum = table_compute_checksum(header, sz);
> +	nhlt_free_resources(nhlt);
> +
> +	ret = acpi_add_table(ctx, ctx->current);
> +	if (ret)
> +		return log_msg_ret("add", ret);
> +	acpi_inc_align(ctx, sz);
> +
> +	return 0;
> +}
> +
> +static int _nhlt_add_single_endpoint(struct nhlt *nhlt, int virtual_bus_id,
> +				     const struct nhlt_endp_descriptor *epd)
> +{
> +	struct nhlt_endpoint *endp;
> +	int ret;
> +
> +	endp = nhlt_add_endpoint(nhlt, epd->link, epd->device, epd->direction,
> +				 epd->vid, epd->did);
> +	if (!endp)
> +		return -EINVAL;
> +
> +	endp->virtual_bus_id = virtual_bus_id;
> +
> +	ret = nhlt_endpoint_append_config(endp, epd->cfg, epd->cfg_size);
> +	if (ret)
> +		return ret;
> +
> +	ret = nhlt_endpoint_add_formats(endp, epd->formats, epd->num_formats);
> +	if (ret)
> +		return log_msg_ret("formats", ret);
> +
> +	return 0;
> +}
> +
> +static int _nhlt_add_endpoints(struct nhlt *nhlt, int virtual_bus_id,
> +			       const struct nhlt_endp_descriptor *epds,
> +			       size_t num_epds)
> +{
> +	size_t i;
> +	int ret;
> +
> +	for (i = 0; i < num_epds; i++) {
> +		ret = _nhlt_add_single_endpoint(nhlt, virtual_bus_id, &epds[i]);
> +		if (ret)
> +			return log_ret(ret);
> +	}
> +
> +	return 0;
> +}
> +
> +int nhlt_add_endpoints(struct nhlt *nhlt,
> +		       const struct nhlt_endp_descriptor *epds, size_t num_epds)
> +{
> +	int ret;
> +
> +	ret = _nhlt_add_endpoints(nhlt, DEFAULT_VIRTUAL_BUS_ID, epds, num_epds);
> +
> +	return ret;
> +}
> +
> +int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id,
> +			   const struct nhlt_endp_descriptor *epds,
> +			   size_t num_epds)
> +{
> +	int ret;
> +
> +	ret = _nhlt_add_endpoints(nhlt, virtual_bus_id, epds, num_epds);
> +	if (!ret)
> +		nhlt_next_instance(nhlt, NHLT_LINK_SSP);
> +
> +	return ret;
> +}
> -- 
> 2.27.0.290.gba653c62da-goog

regards, Wolfgang

[PATCH v1 19/43] x86: pinctrl: Add multi-ACPI control

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 19/43] x86: pinctrl: Add multi-ACPI control
> 
> Add a Kconfig to control whether pinctrl is represented as a single ACPI
> device or as multiple devices. In the latter case (the default) we should
> return the pin number relative to the pinctrl device.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  drivers/pinctrl/intel/Kconfig   | 4 ++++
>  drivers/pinctrl/intel/pinctrl.c | 2 ++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
> index e62a2e0349..05a314af88 100644
> --- a/drivers/pinctrl/intel/Kconfig
> +++ b/drivers/pinctrl/intel/Kconfig
> @@ -15,6 +15,10 @@ config INTEL_PINCTRL_IOSTANDBY
>  	bool
>  	default y
>  
> +config INTEL_PINCTRL_MULTI_ACPI_DEVICES
> +	bool
> +	default y

Nit: A description of what this option does would be helpful

> +
>  config PINCTRL_INTEL_APL
>  	bool "Support Intel Apollo Lake (APL)"
>  	help
> diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c
> index bf3989bf32..32ca303b27 100644
> --- a/drivers/pinctrl/intel/pinctrl.c
> +++ b/drivers/pinctrl/intel/pinctrl.c
> @@ -427,6 +427,8 @@ int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset)
>  	const struct pad_community *comm = priv->comm;
>  	int group;
>  
> +	if (IS_ENABLED(CONFIG_INTEL_PINCTRL_MULTI_ACPI_DEVICES))
> +		return offset;
>  	group = pinctrl_group_index(comm, offset);
>  
>  	/* If pad base is not set then use GPIO number as ACPI pin number */
> -- 
> 2.27.0.290.gba653c62da-goog

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 23/43] x86: Add error checking for csrt table generation

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: [PATCH v1 23/43] x86: Add error checking for csrt table generation
> 
> Generation of this table can fail, so update the function to return an
> error code.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v1:
> - Add new patch to add error checking for csrt table generation
> 
>  arch/x86/lib/acpi_table.c | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)

Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

[PATCH v1 18/43] x86: pinctrl: Update comment for intel_pinctrl_get_pad()

[Simon Glass]

Hi Bin,

On Tue, 30 Jun 2020 at 00:43, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Add information about what is returned on error.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  arch/x86/include/asm/intel_pinctrl.h | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
> > index f39ebde539..982b2514a0 100644
> > --- a/arch/x86/include/asm/intel_pinctrl.h
> > +++ b/arch/x86/include/asm/intel_pinctrl.h
> > @@ -300,6 +300,7 @@ u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
> >   * @pad: Pad to check
> >   * @devp: Returns pinctrl device containing that pad
> >   * @offsetp: Returns offset of pad within that pinctrl device
> > + * @return 0 if OK, -ENOTBLK if pad number is invalid
>
> It's weird that ENOTBLK is used for a pinctrl.
>

Yes. I want it to be very distinctive since it is passed through many
functions. Can you suggest a better value?

Regards,
Simon

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Simon Glass]

Hi Bin,

On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > audio codecs and connections in a system. Various devices can contribute
> > information to produce the table.
> >
> > Add core support for this, based on a structure which is built up through
> > calls to the driver.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  drivers/core/acpi.c | 15 +++++++++++++++
> >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> >  2 files changed, 41 insertions(+)
> >
> > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > index ea304a3067..a5053fec6f 100644
> > --- a/drivers/core/acpi.c
> > +++ b/drivers/core/acpi.c
> > @@ -31,6 +31,7 @@ enum method_t {
> >         METHOD_WRITE_TABLES,
> >         METHOD_FILL_SSDT,
> >         METHOD_INJECT_DSDT,
> > +       METHOD_SETUP_NHLT,
>
> Do we really need to promote this to be an ACPI core method? Can we
> reuse the SSDT/DSDT one?

I don't think so. Those two are for a particular purpose. In fact NHLT
is generated while doing SSDT I think. The idea is that drivers that
want to contribute to NHLT can do so. But we cannot use the SSDT
mechanism since each driver contributes only a part of the info, and
we need something else to bring it all together.

Regards,
Simon

[PATCH v1 20/43] x86: pinctrl: Set up itss in the probe() method

[Simon Glass]

Hi Bin,

On Tue, 30 Jun 2020 at 00:43, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present the itss is probed in the ofdata_to_platdata() method. This is
> > incorrect since itss is a child of p2sb which itself needs to probe the
> > pinctrl device. This means that p2sb is effectively not probed when the
> > itss is probed, so we get the wrong register address from p2sb.
> >
>
> I wonder how this ever worked?
>

I think it worked before the change to separate ofdata_to_platdata()
and probe() properly, and also if the p2sb has already been probed for
a different reason.

> > Fix this by moving the itss probe to the correct place.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  drivers/pinctrl/intel/pinctrl.c | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>
> Regards,
> Bin

Regards,
Simon

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Bin Meng]

Hi Simon,

On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Bin,
>
> On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > audio codecs and connections in a system. Various devices can contribute
> > > information to produce the table.
> > >
> > > Add core support for this, based on a structure which is built up through
> > > calls to the driver.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > >  drivers/core/acpi.c | 15 +++++++++++++++
> > >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> > >  2 files changed, 41 insertions(+)
> > >
> > > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > > index ea304a3067..a5053fec6f 100644
> > > --- a/drivers/core/acpi.c
> > > +++ b/drivers/core/acpi.c
> > > @@ -31,6 +31,7 @@ enum method_t {
> > >         METHOD_WRITE_TABLES,
> > >         METHOD_FILL_SSDT,
> > >         METHOD_INJECT_DSDT,
> > > +       METHOD_SETUP_NHLT,
> >
> > Do we really need to promote this to be an ACPI core method? Can we
> > reuse the SSDT/DSDT one?
>
> I don't think so. Those two are for a particular purpose. In fact NHLT
> is generated while doing SSDT I think. The idea is that drivers that
> want to contribute to NHLT can do so. But we cannot use the SSDT
> mechanism since each driver contributes only a part of the info, and
> we need something else to bring it all together.

Will there be only one device that sets up the NHLT info?

Regards,
Bin

[PATCH v1 18/43] x86: pinctrl: Update comment for intel_pinctrl_get_pad()

[Bin Meng]

Hi Simon,

On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Bin,
>
> On Tue, 30 Jun 2020 at 00:43, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Add information about what is returned on error.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > >  arch/x86/include/asm/intel_pinctrl.h | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
> > > index f39ebde539..982b2514a0 100644
> > > --- a/arch/x86/include/asm/intel_pinctrl.h
> > > +++ b/arch/x86/include/asm/intel_pinctrl.h
> > > @@ -300,6 +300,7 @@ u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
> > >   * @pad: Pad to check
> > >   * @devp: Returns pinctrl device containing that pad
> > >   * @offsetp: Returns offset of pad within that pinctrl device
> > > + * @return 0 if OK, -ENOTBLK if pad number is invalid
> >
> > It's weird that ENOTBLK is used for a pinctrl.
> >
>
> Yes. I want it to be very distinctive since it is passed through many
> functions. Can you suggest a better value?

How about -EINVAL?

Regards,
Bin

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Simon Glass]

Hi Bin,

On Thu, 2 Jul 2020 at 18:54, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > > audio codecs and connections in a system. Various devices can contribute
> > > > information to produce the table.
> > > >
> > > > Add core support for this, based on a structure which is built up through
> > > > calls to the driver.
> > > >
> > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > ---
> > > >
> > > >  drivers/core/acpi.c | 15 +++++++++++++++
> > > >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> > > >  2 files changed, 41 insertions(+)
> > > >
> > > > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > > > index ea304a3067..a5053fec6f 100644
> > > > --- a/drivers/core/acpi.c
> > > > +++ b/drivers/core/acpi.c
> > > > @@ -31,6 +31,7 @@ enum method_t {
> > > >         METHOD_WRITE_TABLES,
> > > >         METHOD_FILL_SSDT,
> > > >         METHOD_INJECT_DSDT,
> > > > +       METHOD_SETUP_NHLT,
> > >
> > > Do we really need to promote this to be an ACPI core method? Can we
> > > reuse the SSDT/DSDT one?
> >
> > I don't think so. Those two are for a particular purpose. In fact NHLT
> > is generated while doing SSDT I think. The idea is that drivers that
> > want to contribute to NHLT can do so. But we cannot use the SSDT
> > mechanism since each driver contributes only a part of the info, and
> > we need something else to bring it all together.
>
> Will there be only one device that sets up the NHLT info?

WIth coral it is two devices. I'm not sure of the maximum, but I
suppose it depends on the audio codecs present.

Regards,
Simon

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Bin Meng]

Hi Simon,

On Fri, Jul 3, 2020 at 11:50 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Bin,
>
> On Thu, 2 Jul 2020 at 18:54, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Hi Bin,
> > >
> > > On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > >
> > > > Hi Simon,
> > > >
> > > > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > > > >
> > > > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > > > audio codecs and connections in a system. Various devices can contribute
> > > > > information to produce the table.
> > > > >
> > > > > Add core support for this, based on a structure which is built up through
> > > > > calls to the driver.
> > > > >
> > > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > > ---
> > > > >
> > > > >  drivers/core/acpi.c | 15 +++++++++++++++
> > > > >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> > > > >  2 files changed, 41 insertions(+)
> > > > >
> > > > > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > > > > index ea304a3067..a5053fec6f 100644
> > > > > --- a/drivers/core/acpi.c
> > > > > +++ b/drivers/core/acpi.c
> > > > > @@ -31,6 +31,7 @@ enum method_t {
> > > > >         METHOD_WRITE_TABLES,
> > > > >         METHOD_FILL_SSDT,
> > > > >         METHOD_INJECT_DSDT,
> > > > > +       METHOD_SETUP_NHLT,
> > > >
> > > > Do we really need to promote this to be an ACPI core method? Can we
> > > > reuse the SSDT/DSDT one?
> > >
> > > I don't think so. Those two are for a particular purpose. In fact NHLT
> > > is generated while doing SSDT I think. The idea is that drivers that
> > > want to contribute to NHLT can do so. But we cannot use the SSDT
> > > mechanism since each driver contributes only a part of the info, and
> > > we need something else to bring it all together.
> >
> > Will there be only one device that sets up the NHLT info?
>
> WIth coral it is two devices. I'm not sure of the maximum, but I
> suppose it depends on the audio codecs present.

Could we make this method to be provided by the codec device, instead
of a generic ACPI core method?

Regards,
Bin

[PATCH v1 26/43] i2c: designware_i2c: Add a little more debugging

[Heiko Schocher]

Hello Simon,

Am 15.06.2020 um 05:57 schrieb Simon Glass:
> Add debugging for a few more values and also use log to show return values
> when something goes wrong. This makes it easier to see the root cause.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
> Changes in v1:
> - Add new patch to improve designware_i2c debugging
> 
>   drivers/i2c/designware_i2c.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)

Reviewed-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: hs at denx.de

[PATCH v1 28/43] i2c: designware_i2c: Support ACPI table generation

[Heiko Schocher]

Hello Simon,

Am 15.06.2020 um 05:57 schrieb Simon Glass:
> Update the PCI driver to generate ACPI information so that Linux has the
> full information about each I2C bus.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> 
> ---
> 
> Changes in v1:
> - Capitalise ACPI_OPS_PTR
> 
>   drivers/i2c/designware_i2c.c     |  25 ++++++++
>   drivers/i2c/designware_i2c.h     |  15 +++++
>   drivers/i2c/designware_i2c_pci.c | 104 ++++++++++++++++++++++++++++++-
>   3 files changed, 143 insertions(+), 1 deletion(-)

Reviewed-by: Heiko Schocher <hs@denx.de>

Some nitpicks...

> diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
> index 44a1f33398..630938743f 100644
> --- a/drivers/i2c/designware_i2c.c
> +++ b/drivers/i2c/designware_i2c.c
> @@ -333,6 +333,31 @@ static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
>   	/* Restore back i2c now speed set */
>   	if (ena == IC_ENABLE_0B)
>   		dw_i2c_enable(i2c_base, true);
> +	if (priv)
> +		priv->config = config;

Please add an empty line here.

> +	return 0;
> +}
> +
> +int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
> +			    struct dw_i2c_speed_config *config)
> +{
> +	struct dw_i2c *priv = dev_get_priv(dev);
> +	ulong rate;
> +	int ret;
> +
> +#if CONFIG_IS_ENABLED(CLK)
> +	rate = clk_get_rate(&priv->clk);
> +	if (IS_ERR_VALUE(rate))
> +		return log_msg_ret("clk", -EINVAL);
> +#else
> +	rate = IC_CLK;
> +#endif
> +
> +	ret = calc_bus_speed(priv, priv->regs, speed_hz, rate, config);
> +	if (ret)
> +		printf("%s: ret=%d\n", __func__, ret);
> +	if (ret)
> +		return log_msg_ret("calc_bus_speed", ret);
>   
>   	return 0;
>   }

[...]
> diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
> index bd34ec0b47..d5108e9064 100644
> --- a/drivers/i2c/designware_i2c_pci.c
> +++ b/drivers/i2c/designware_i2c_pci.c
> @@ -9,7 +9,12 @@
>   #include <dm.h>
>   #include <log.h>
>   #include <spl.h>
> +#include <acpi/acpigen.h>
> +#include <acpi/acpi_device.h>
>   #include <asm/lpss.h>
> +#include <dm/acpi.h>
> +#include <dm/device-internal.h>
> +#include <dm/uclass-internal.h>
>   #include "designware_i2c.h"
>   
>   enum {
> @@ -87,6 +92,8 @@ static int designware_i2c_pci_bind(struct udevice *dev)
>   {
>   	char name[20];
>   
> +	if (dev_of_valid(dev))
> +		return 0;

here too.

>   	/*
>   	 * Create a unique device name for PCI type devices
>   	 * ToDo:
> @@ -100,13 +107,107 @@ static int designware_i2c_pci_bind(struct udevice *dev)
>   	 * be possible. We cannot use static data in drivers since they may be
>   	 * used in SPL or before relocation.
>   	 */
> -	dev->req_seq = gd->arch.dw_i2c_num_cards++;
> +	dev->req_seq = uclass_find_next_free_req_seq(UCLASS_I2C);
>   	sprintf(name, "i2c_designware#%u", dev->req_seq);
>   	device_set_name(dev, name);
>   
>   	return 0;
>   }
>   
> +/*
> + * Write ACPI object to describe speed configuration.
> + *
> + * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
> + *
> + * SSCN: I2C_SPEED_STANDARD
> + * FMCN: I2C_SPEED_FAST
> + * FPCN: I2C_SPEED_FAST_PLUS
> + * HSCN: I2C_SPEED_HIGH
> + */
> +static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
> +					   struct dw_i2c_speed_config *config)
> +{
> +	switch (config->speed_mode) {
> +	case IC_SPEED_MODE_HIGH:
> +		acpigen_write_name(ctx, "HSCN");
> +		break;
> +	case IC_SPEED_MODE_FAST_PLUS:
> +		acpigen_write_name(ctx, "FPCN");
> +		break;
> +	case IC_SPEED_MODE_FAST:
> +		acpigen_write_name(ctx, "FMCN");
> +		break;
> +	case IC_SPEED_MODE_STANDARD:
> +	default:
> +		acpigen_write_name(ctx, "SSCN");
> +	}
> +
> +	/* Package () { scl_lcnt, scl_hcnt, sda_hold } */
> +	acpigen_write_package(ctx, 3);
> +	acpigen_write_word(ctx, config->scl_hcnt);
> +	acpigen_write_word(ctx, config->scl_lcnt);
> +	acpigen_write_dword(ctx, config->sda_hold);
> +	acpigen_pop_len(ctx);
> +}
> +
> +/*
> + * Generate I2C timing information into the SSDT for the OS driver to consume,
> + * optionally applying override values provided by the caller.
> + */
> +static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
> +				 struct acpi_ctx *ctx)
> +{
> +	struct dw_i2c_speed_config config;
> +	char path[ACPI_PATH_MAX];
> +	u32 speeds[4];
> +	int size, i;
> +	int ret;
> +
> +	/* If no device-tree node, ignore this since we assume it isn't used */
> +	if (!dev_of_valid(dev))
> +		return 0;

and here.

> +	ret = acpi_device_path(dev, path, sizeof(path));
> +	if (ret)
> +		return log_msg_ret("path", ret);
> +
> +	size = dev_read_size(dev, "i2c,speeds");
> +	if (size < 0)
> +		return log_msg_ret("i2c,speeds", -EINVAL);

and here.

> +	size /= sizeof(u32);
> +	if (size > ARRAY_SIZE(speeds))
> +		return log_msg_ret("array", -E2BIG);
> +
> +	ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size);
> +	if (ret)
> +		return log_msg_ret("read", -E2BIG);
> +
> +	if (0) {

Please remove dead code and drop the if.


> +		acpigen_write_scope(ctx, path);
> +		for (i = 0; i < size; i++) {
> +			ret = dw_i2c_gen_speed_config(dev, speeds[i], &config);
> +			if (ret)
> +				return log_msg_ret("config", ret);
> +			dw_i2c_acpi_write_speed_config(ctx, &config);
> +		}
> +	} else {
> +		uint speed;
> +
> +		speed = dev_read_u32_default(dev, "clock-frequency", 100000);
> +		acpigen_write_scope(ctx, path);
> +		ret = dw_i2c_gen_speed_config(dev, speed, &config);
> +		if (ret)
> +			return log_msg_ret("config", ret);
> +		dw_i2c_acpi_write_speed_config(ctx, &config);
> +	}
> +	acpigen_pop_len(ctx);
> +
> +	return 0;
> +}
> +
> +struct acpi_ops dw_i2c_acpi_ops = {
> +	.fill_ssdt	= dw_i2c_acpi_fill_ssdt,
> +};
> +
>   static const struct udevice_id designware_i2c_pci_ids[] = {
>   	{ .compatible = "snps,designware-i2c-pci" },
>   	{ .compatible = "intel,apl-i2c", .data = INTEL_APL },
> @@ -124,6 +225,7 @@ U_BOOT_DRIVER(i2c_designware_pci) = {
>   	.remove = designware_i2c_remove,
>   	.flags = DM_FLAG_OS_PREPARE,
>   	.ops	= &designware_i2c_ops,
> +	ACPI_OPS_PTR(&dw_i2c_acpi_ops)
>   };
>   
>   static struct pci_device_id designware_pci_supported[] = {
> 

Thanks!

bye,
Heiko
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: hs at denx.de

[PATCH v1 27/43] i2c: Add log_ret() on error

[Heiko Schocher]

Hello Simon,

Am 15.06.2020 um 05:57 schrieb Simon Glass:
> Add a few of these calls to make it easier to see where an error occurs,
> if CONFIG_LOG_ERROR_RETURN is enabled.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>   drivers/i2c/i2c-uclass.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: hs at denx.de

[PATCH v1 18/43] x86: pinctrl: Update comment for intel_pinctrl_get_pad()

[Simon Glass]

Hi Bin,

On Thu, 2 Jul 2020 at 18:59, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 30 Jun 2020 at 00:43, Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > Add information about what is returned on error.
> > > >
> > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > ---
> > > >
> > > >  arch/x86/include/asm/intel_pinctrl.h | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
> > > > index f39ebde539..982b2514a0 100644
> > > > --- a/arch/x86/include/asm/intel_pinctrl.h
> > > > +++ b/arch/x86/include/asm/intel_pinctrl.h
> > > > @@ -300,6 +300,7 @@ u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
> > > >   * @pad: Pad to check
> > > >   * @devp: Returns pinctrl device containing that pad
> > > >   * @offsetp: Returns offset of pad within that pinctrl device
> > > > + * @return 0 if OK, -ENOTBLK if pad number is invalid
> > >
> > > It's weird that ENOTBLK is used for a pinctrl.
> > >
> >
> > Yes. I want it to be very distinctive since it is passed through many
> > functions. Can you suggest a better value?
>
> How about -EINVAL?

That is not distinctive though. Lots of things produce that error and
it is mostly reserved for bad arguments in ofdata_to_platdata methods.

Regards,
Simon

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Simon Glass]

Hi Bin,

On Thu, 2 Jul 2020 at 22:33, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Fri, Jul 3, 2020 at 11:50 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Bin,
> >
> > On Thu, 2 Jul 2020 at 18:54, Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > >
> > > > > Hi Simon,
> > > > >
> > > > > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > >
> > > > > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > > > > audio codecs and connections in a system. Various devices can contribute
> > > > > > information to produce the table.
> > > > > >
> > > > > > Add core support for this, based on a structure which is built up through
> > > > > > calls to the driver.
> > > > > >
> > > > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > > > ---
> > > > > >
> > > > > >  drivers/core/acpi.c | 15 +++++++++++++++
> > > > > >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> > > > > >  2 files changed, 41 insertions(+)
> > > > > >
> > > > > > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > > > > > index ea304a3067..a5053fec6f 100644
> > > > > > --- a/drivers/core/acpi.c
> > > > > > +++ b/drivers/core/acpi.c
> > > > > > @@ -31,6 +31,7 @@ enum method_t {
> > > > > >         METHOD_WRITE_TABLES,
> > > > > >         METHOD_FILL_SSDT,
> > > > > >         METHOD_INJECT_DSDT,
> > > > > > +       METHOD_SETUP_NHLT,
> > > > >
> > > > > Do we really need to promote this to be an ACPI core method? Can we
> > > > > reuse the SSDT/DSDT one?
> > > >
> > > > I don't think so. Those two are for a particular purpose. In fact NHLT
> > > > is generated while doing SSDT I think. The idea is that drivers that
> > > > want to contribute to NHLT can do so. But we cannot use the SSDT
> > > > mechanism since each driver contributes only a part of the info, and
> > > > we need something else to bring it all together.
> > >
> > > Will there be only one device that sets up the NHLT info?
> >
> > WIth coral it is two devices. I'm not sure of the maximum, but I
> > suppose it depends on the audio codecs present.
>
> Could we make this method to be provided by the codec device, instead
> of a generic ACPI core method?

The codec device does implement this. See the drivers where they
actually implement the NHLT method.

This is definitely an ACPI-specific thing, so I think we need core
support for iterating through drivers that want to provide this info.

Regards,
Simon

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Bin Meng]

Hi Simon,

On Tue, Jul 7, 2020 at 3:22 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Bin,
>
> On Thu, 2 Jul 2020 at 22:33, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Fri, Jul 3, 2020 at 11:50 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Hi Bin,
> > >
> > > On Thu, 2 Jul 2020 at 18:54, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > >
> > > > Hi Simon,
> > > >
> > > > On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
> > > > >
> > > > > Hi Bin,
> > > > >
> > > > > On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > >
> > > > > > Hi Simon,
> > > > > >
> > > > > > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > > >
> > > > > > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > > > > > audio codecs and connections in a system. Various devices can contribute
> > > > > > > information to produce the table.
> > > > > > >
> > > > > > > Add core support for this, based on a structure which is built up through
> > > > > > > calls to the driver.
> > > > > > >
> > > > > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > > > > ---
> > > > > > >
> > > > > > >  drivers/core/acpi.c | 15 +++++++++++++++
> > > > > > >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> > > > > > >  2 files changed, 41 insertions(+)
> > > > > > >
> > > > > > > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > > > > > > index ea304a3067..a5053fec6f 100644
> > > > > > > --- a/drivers/core/acpi.c
> > > > > > > +++ b/drivers/core/acpi.c
> > > > > > > @@ -31,6 +31,7 @@ enum method_t {
> > > > > > >         METHOD_WRITE_TABLES,
> > > > > > >         METHOD_FILL_SSDT,
> > > > > > >         METHOD_INJECT_DSDT,
> > > > > > > +       METHOD_SETUP_NHLT,
> > > > > >
> > > > > > Do we really need to promote this to be an ACPI core method? Can we
> > > > > > reuse the SSDT/DSDT one?
> > > > >
> > > > > I don't think so. Those two are for a particular purpose. In fact NHLT
> > > > > is generated while doing SSDT I think. The idea is that drivers that
> > > > > want to contribute to NHLT can do so. But we cannot use the SSDT
> > > > > mechanism since each driver contributes only a part of the info, and
> > > > > we need something else to bring it all together.
> > > >
> > > > Will there be only one device that sets up the NHLT info?
> > >
> > > WIth coral it is two devices. I'm not sure of the maximum, but I
> > > suppose it depends on the audio codecs present.
> >
> > Could we make this method to be provided by the codec device, instead
> > of a generic ACPI core method?
>
> The codec device does implement this. See the drivers where they
> actually implement the NHLT method.
>
> This is definitely an ACPI-specific thing, so I think we need core
> support for iterating through drivers that want to provide this info.

My concern is that this is not generic enough to promote this to ACPI core.

I wanted to have something like this:

Create a codec uclass driver, and in the code uclass driver, create an
op that is used to set up the NHLT infor if ACPI_GEN is on.

Regards,
Bin

[PATCH v1 02/43] binman: Refactor binman_entry_find() to allow other nodes

[Simon Glass]

Hi Bin,

On Mon, 29 Jun 2020 at 20:33, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present we can only read from a top-level binman node entry. Refactor
> > this function to produce a second local function which supports reading
> > from any node.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  lib/binman.c | 18 ++++++++++++------
> >  1 file changed, 12 insertions(+), 6 deletions(-)
> >
> > diff --git a/lib/binman.c b/lib/binman.c
> > index dc3a880882..79d01230dd 100644
> > --- a/lib/binman.c
> > +++ b/lib/binman.c
> > @@ -29,25 +29,31 @@ struct binman_info {
> >
> >  static struct binman_info *binman;
> >
> > -int binman_entry_find(const char *name, struct binman_entry *entry)
> > +int binman_entry_find_(ofnode node, const char *name, struct binman_entry *entry)
>
> This one should be static. We really should agree on a naming
> convention for such internal APIs. I would prefer adding _internal
> suffix, or using __ prefix

Well I think internal is too long and I like a trailing underscore.

The trailing double underscore is reserved for the compiler.

Another option is to drop the prefix, so:

find_entry(...)

Regards,
Simon

[PATCH v1 08/43] acpi: Export functions to write sized values

[Simon Glass]

Hi Bin,

On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present only acpigen_write_integer() is exported for use by other code.
> > But in some cases it is useful to call the specific function depending on
> > the size of the value.
> >
> > Export these functions and add a test.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  include/acpi/acpigen.h | 46 ++++++++++++++++++++++++++++++++++++++++++
> >  test/dm/acpigen.c      | 45 ++++++++++++++++++++++++++++++++++++++++-
> >  2 files changed, 90 insertions(+), 1 deletion(-)
> >
>
> Since the acpigen_write_integer() patch has not been applied, could
> you please squash this patch into:
>
> [v3,15/35] acpi: Support writing an integer
> http://patchwork.ozlabs.org/project/uboot/patch/20200614025523.40183-5-sjg at chromium.org/

Oh, I've already resent that series. I tend to work one at a time.
Feel free to squash if you like but I think this merits a different
patch.

Regards,
SImon

[PATCH v1 11/43] acpi: mmc: Generate ACPI info for the PCI SD Card

[Simon Glass]

Hi Bin,

On Mon, 29 Jun 2020 at 23:58, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Write required information into the SSDT to describe the SD card
> > card-detect pin. Since the required GPIO properties are not present in
> > the device-tree binding, set them manually for now.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v1:
> > - Capitalise ACPI_OPS_PTR
> >
> >  configs/sandbox_defconfig |  2 +
> >  drivers/mmc/pci_mmc.c     | 78 ++++++++++++++++++++++++++++++++++++++-
> >  2 files changed, 79 insertions(+), 1 deletion(-)
> >
> > diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
> > index 982075c568..cb6b4b0ee7 100644
> > --- a/configs/sandbox_defconfig
> > +++ b/configs/sandbox_defconfig
> > @@ -143,7 +143,9 @@ CONFIG_P2SB=y
> >  CONFIG_PWRSEQ=y
> >  CONFIG_SPL_PWRSEQ=y
> >  CONFIG_I2C_EEPROM=y
> > +CONFIG_MMC_PCI=y
> >  CONFIG_MMC_SANDBOX=y
> > +CONFIG_MMC_SDHCI=y
> >  CONFIG_MTD=y
> >  CONFIG_SPI_FLASH_SANDBOX=y
> >  CONFIG_SPI_FLASH_ATMEL=y
> > diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
> > index 404264a697..0c45e1b893 100644
> > --- a/drivers/mmc/pci_mmc.c
> > +++ b/drivers/mmc/pci_mmc.c
> > @@ -7,10 +7,15 @@
> >  #include <common.h>
> >  #include <dm.h>
> >  #include <errno.h>
> > +#include <log.h>
> >  #include <malloc.h>
> >  #include <mapmem.h>
> >  #include <sdhci.h>
> > -#include <asm/pci.h>
> > +#include <acpi/acpigen.h>
> > +#include <acpi/acpi_device.h>
> > +#include <acpi/acpi_dp.h>
> > +#include <asm-generic/gpio.h>
> > +#include <dm/acpi.h>
> >
> >  struct pci_mmc_plat {
> >         struct mmc_config cfg;
> > @@ -20,6 +25,7 @@ struct pci_mmc_plat {
> >  struct pci_mmc_priv {
> >         struct sdhci_host host;
> >         void *base;
> > +       struct gpio_desc cd_gpio;
> >  };
> >
> >  static int pci_mmc_probe(struct udevice *dev)
> > @@ -44,6 +50,15 @@ static int pci_mmc_probe(struct udevice *dev)
> >         return sdhci_probe(dev);
> >  }
> >
> > +static int pci_mmc_ofdata_to_platdata(struct udevice *dev)
> > +{
> > +       struct pci_mmc_priv *priv = dev_get_priv(dev);
> > +
> > +       gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
> > +
> > +       return 0;
> > +}
> > +
> >  static int pci_mmc_bind(struct udevice *dev)
> >  {
> >         struct pci_mmc_plat *plat = dev_get_platdata(dev);
> > @@ -51,14 +66,75 @@ static int pci_mmc_bind(struct udevice *dev)
> >         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
> >  }
> >
> > +static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev,
> > +                                 struct acpi_ctx *ctx)
> > +{
> > +       struct pci_mmc_priv *priv = dev_get_priv(dev);
> > +       char path[ACPI_PATH_MAX];
> > +       struct acpi_gpio gpio;
> > +       struct acpi_dp *dp;
> > +       int ret;
> > +
> > +       if (!dev_of_valid(dev))
> > +               return 0;
> > +
> > +       ret = gpio_get_acpi(&priv->cd_gpio, &gpio);
> > +       if (ret)
> > +               return log_msg_ret("gpio", ret);
> > +       gpio.type = ACPI_GPIO_TYPE_INTERRUPT;
> > +       gpio.pull = ACPI_GPIO_PULL_NONE;
> > +       gpio.irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
> > +       gpio.irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
> > +       gpio.irq.shared = ACPI_IRQ_SHARED;
> > +       gpio.irq.wake = ACPI_IRQ_WAKE;
>
> The above are all hardcoded. Is there is way to figure out these from
> DT GPIO properties?

It would require either adding some more ACPI DT properties or
enhancing U-Boot's interrupt uclass, probably both. Definitely
something we can do in the future but I feel I am boiling enough seas
at present :-)

Regards,
Simon

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Simon Glass]

Hi Bin,

On Mon, 6 Jul 2020 at 18:22, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Tue, Jul 7, 2020 at 3:22 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Bin,
> >
> > On Thu, 2 Jul 2020 at 22:33, Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Fri, Jul 3, 2020 at 11:50 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > On Thu, 2 Jul 2020 at 18:54, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > >
> > > > > Hi Simon,
> > > > >
> > > > > On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > >
> > > > > > Hi Bin,
> > > > > >
> > > > > > On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > > >
> > > > > > > Hi Simon,
> > > > > > >
> > > > > > > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > > > >
> > > > > > > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > > > > > > audio codecs and connections in a system. Various devices can contribute
> > > > > > > > information to produce the table.
> > > > > > > >
> > > > > > > > Add core support for this, based on a structure which is built up through
> > > > > > > > calls to the driver.
> > > > > > > >
> > > > > > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > > > > > ---
> > > > > > > >
> > > > > > > >  drivers/core/acpi.c | 15 +++++++++++++++
> > > > > > > >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> > > > > > > >  2 files changed, 41 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > > > > > > > index ea304a3067..a5053fec6f 100644
> > > > > > > > --- a/drivers/core/acpi.c
> > > > > > > > +++ b/drivers/core/acpi.c
> > > > > > > > @@ -31,6 +31,7 @@ enum method_t {
> > > > > > > >         METHOD_WRITE_TABLES,
> > > > > > > >         METHOD_FILL_SSDT,
> > > > > > > >         METHOD_INJECT_DSDT,
> > > > > > > > +       METHOD_SETUP_NHLT,
> > > > > > >
> > > > > > > Do we really need to promote this to be an ACPI core method? Can we
> > > > > > > reuse the SSDT/DSDT one?
> > > > > >
> > > > > > I don't think so. Those two are for a particular purpose. In fact NHLT
> > > > > > is generated while doing SSDT I think. The idea is that drivers that
> > > > > > want to contribute to NHLT can do so. But we cannot use the SSDT
> > > > > > mechanism since each driver contributes only a part of the info, and
> > > > > > we need something else to bring it all together.
> > > > >
> > > > > Will there be only one device that sets up the NHLT info?
> > > >
> > > > WIth coral it is two devices. I'm not sure of the maximum, but I
> > > > suppose it depends on the audio codecs present.
> > >
> > > Could we make this method to be provided by the codec device, instead
> > > of a generic ACPI core method?
> >
> > The codec device does implement this. See the drivers where they
> > actually implement the NHLT method.
> >
> > This is definitely an ACPI-specific thing, so I think we need core
> > support for iterating through drivers that want to provide this info.
>
> My concern is that this is not generic enough to promote this to ACPI core.
>
> I wanted to have something like this:
>
> Create a codec uclass driver, and in the code uclass driver, create an
> op that is used to set up the NHLT infor if ACPI_GEN is on.

We already have UCLASS_SOUND so could add it to sound_ops. But that
seems weird to me since this is not an operation to play a sound. We
do this with GIPOs and IRQs but in that case the operation returns
some data. Here we are asking the driver to add some data to a table.
I'm just not sure it makes sense.

What do you think?

Regards,
SImon

[PATCH v1 12/43] x86: Add bindings for NHLT

[Simon Glass]

Hi Bin,

On Mon, 29 Jun 2020 at 23:58, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table
> > (NHLT).
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  include/dt-bindings/sound/nhlt.h | 23 +++++++++++++++++++++++
> >  1 file changed, 23 insertions(+)
> >  create mode 100644 include/dt-bindings/sound/nhlt.h
> >
> > diff --git a/include/dt-bindings/sound/nhlt.h b/include/dt-bindings/sound/nhlt.h
> > new file mode 100644
> > index 0000000000..c33f874966
> > --- /dev/null
> > +++ b/include/dt-bindings/sound/nhlt.h
> > @@ -0,0 +1,23 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright 2019 Google LLC
> > + */
> > +
> > +#ifndef _DT_BINDINGS_SOUND_NHLT_H
> > +#define _DT_BINDINGS_SOUND_NHLT_H
> > +
> > +#define NHLT_VID       0x8086
> > +#define NHLT_DID_DMIC  0xae20
> > +#define NHLT_DID_BT    0xae30
> > +#define NHLT_DID_SSP   0xae34
>
> These look like PCI vendor ID (0x8086 for Intel) and device IDs. If
> they are device IDs, how could they be fixed?

The value of the 8086 one is the same. But according to the spec these
are virtual devices. I am not sure that the values have anything to do
with PCI.  The spec doesn't even mention PCI and the PCI ID database
does not list the DID values.

So I think we should leave these as is unless we get new information.

Regards,
SImon

[PATCH v1 15/43] sound: Add an ACPI driver for Dialog Semicondutor da7219

[Simon Glass]

Hi Bin,

On Tue, 30 Jun 2020 at 00:06, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > This chip is used on coral and we need to generate ACPI tables for sound
> > to make it work. Add a driver that does just this (i.e. at present does
> > not actually support playing sound).
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v1:
> > - Use acpi,ddn instead of acpi,desc
> > - Add a check for invalid node
> > - Add NHLT support
> > - Capitalise ACPI_OPS_PTR
> > - Rebase to master
> >
> >  configs/sandbox_defconfig                 |   1 +
> >  doc/device-tree-bindings/sound/da7219.txt | 113 +++++++++++++
> >  drivers/sound/Kconfig                     |   9 ++
> >  drivers/sound/Makefile                    |   1 +
> >  drivers/sound/da7219.c                    | 189 ++++++++++++++++++++++
> >  5 files changed, 313 insertions(+)
> >  create mode 100644 doc/device-tree-bindings/sound/da7219.txt
> >  create mode 100644 drivers/sound/da7219.c
> >
> > diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
> > index cb6b4b0ee7..6368e278f2 100644
> > --- a/configs/sandbox_defconfig
> > +++ b/configs/sandbox_defconfig
> > @@ -202,6 +202,7 @@ CONFIG_SANDBOX_SERIAL=y
> >  CONFIG_SMEM=y
> >  CONFIG_SANDBOX_SMEM=y
> >  CONFIG_SOUND=y
> > +CONFIG_SOUND_DA7219=y
> >  CONFIG_SOUND_SANDBOX=y
> >  CONFIG_SANDBOX_SPI=y
> >  CONFIG_SPMI=y
> > diff --git a/doc/device-tree-bindings/sound/da7219.txt b/doc/device-tree-bindings/sound/da7219.txt
> > new file mode 100644
> > index 0000000000..5fd8a9f1e7
> > --- /dev/null
> > +++ b/doc/device-tree-bindings/sound/da7219.txt
> > @@ -0,0 +1,113 @@
> > +Dialog Semiconductor DA7219 Audio Codec bindings
> > +
> > +DA7219 is an audio codec with advanced accessory detect features.
> > +
> > +======
> > +
> > +Required properties:
> > +- compatible : Should be "dlg,da7219"
> > +- reg: Specifies the I2C slave address
> > +
> > +- interrupts : IRQ line info for DA7219.
> > +  (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
> > +   further information relating to interrupt properties)
> > +
> > +- VDD-supply: VDD power supply for the device
> > +- VDDMIC-supply: VDDMIC power supply for the device
> > +- VDDIO-supply: VDDIO power supply for the device
> > +  (See Documentation/devicetree/bindings/regulator/regulator.txt for further
> > +   information relating to regulators)
> > +
> > +Optional properties:
> > +- interrupt-names : Name associated with interrupt line. Should be "wakeup" if
> > +  interrupt is to be used to wake system, otherwise "irq" should be used.
> > +- wakeup-source: Flag to indicate this device can wake system (suspend/resume).
> > +
> > +- #clock-cells :  Should be set to '<0>', only one clock source provided;
> > +- clock-output-names : Name given for DAI clocks output;
> > +
> > +- clocks : phandle and clock specifier for codec MCLK.
> > +- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
> > +
> > +- dlg,micbias-lvl : Voltage (mV) for Mic Bias
> > +       [<1600>, <1800>, <2000>, <2200>, <2400>, <2600>]
> > +- dlg,mic-amp-in-sel : Mic input source type
> > +       ["diff", "se_p", "se_n"]
> > +- dlg,mclk-name : String name of MCLK for ACPI
> > +
> > +Deprecated properties:
> > +- dlg,ldo-lvl : Required internal LDO voltage (mV) level for digital engine
> > +  (LDO unavailable in production HW so property no longer required).
> > +
> > +======
> > +
> > +Child node - 'da7219_aad':
> > +
> > +Optional properties:
> > +- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
> > +       [<2800>, <2900>]
> > +- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
> > +- dlg,btn-cfg : Periodic button press measurements for 4-pole jack (ms)
> > +       [<2>, <5>, <10>, <50>, <100>, <200>, <500>]
> > +- dlg,mic-det-thr : Impedance threshold for mic detection measurement (Ohms)
> > +       [<200>, <500>, <750>, <1000>]
> > +- dlg,jack-ins-deb : Debounce time for jack insertion (ms)
> > +       [<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>]
> > +- dlg,jack-det-rate: Jack type detection latency (3/4 pole)
> > +       ["32ms_64ms", "64ms_128ms", "128ms_256ms", "256ms_512ms"]
> > +- dlg,jack-rem-deb : Debounce time for jack removal (ms)
> > +       [<1>, <5>, <10>, <20>]
> > +- dlg,a-d-btn-thr : Impedance threshold between buttons A and D
> > +       [0x0 - 0xFF]
> > +- dlg,d-b-btn-thr : Impedance threshold between buttons D and B
> > +       [0x0 - 0xFF]
> > +- dlg,b-c-btn-thr : Impedance threshold between buttons B and C
> > +       [0x0 - 0xFF]
> > +- dlg,c-mic-btn-thr : Impedance threshold between button C and Mic
> > +       [0x0 - 0xFF]
> > +- dlg,btn-avg : Number of 8-bit readings for averaged button measurement
> > +       [<1>, <2>, <4>, <8>]
> > +- dlg,adc-1bit-rpt : Repeat count for 1-bit button measurement
> > +       [<1>, <2>, <4>, <8>]
> > +
> > +======
> > +
> > +Example:
> > +
> > +       codec: da7219 at 1a {
> > +               compatible = "dlg,da7219";
> > +               reg = <0x1a>;
> > +
> > +               interrupt-parent = <&gpio6>;
> > +               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
> > +
> > +               VDD-supply = <&reg_audio>;
> > +               VDDMIC-supply = <&reg_audio>;
> > +               VDDIO-supply = <&reg_audio>;
> > +
> > +               #clock-cells = <0>;
> > +               clock-output-names = "dai-clks";
> > +
> > +               clocks = <&clks 201>;
> > +               clock-names = "mclk";
> > +
> > +               dlg,ldo-lvl = <1200>;
> > +               dlg,micbias-lvl = <2600>;
> > +               dlg,mic-amp-in-sel = "diff";
> > +
> > +               da7219_aad {
> > +                       dlg,btn-cfg = <50>;
> > +                       dlg,mic-det-thr = <500>;
> > +                       dlg,jack-ins-deb = <20>;
> > +                       dlg,jack-det-rate = "32ms_64ms";
> > +                       dlg,jack-rem-deb = <1>;
> > +
> > +                       dlg,a-d-btn-thr = <0xa>;
> > +                       dlg,d-b-btn-thr = <0x16>;
> > +                       dlg,b-c-btn-thr = <0x21>;
> > +                       dlg,c-mic-btn-thr = <0x3E>;
> > +
> > +                       dlg,btn-avg = <4>;
> > +                       dlg,adc-1bit-rpt = <1>;
> > +               };
> > +       };
> > diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
> > index 4ebc719be2..7f214b97be 100644
> > --- a/drivers/sound/Kconfig
> > +++ b/drivers/sound/Kconfig
> > @@ -40,6 +40,15 @@ config I2S_SAMSUNG
> >           option provides an implementation for sound_init() and
> >           sound_play().
> >
> > +config SOUND_DA7219
> > +       bool "Dialog Semiconductor audio codec"
> > +       depends on SOUND
> > +       help
> > +         The DA7219 is an ultra-low-power audio codec with Advanced Accessory
> > +         Detection (AAD). This driver only supports generation of ACPI tables.
> > +         It does not support sound output or any of the other codec
> > +         features.
> > +
> >  config SOUND_I8254
> >         bool "Intel i8254 timer / beeper"
> >         depends on SOUND
> > diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
> > index 73ed7fe53c..8c3933ad15 100644
> > --- a/drivers/sound/Makefile
> > +++ b/drivers/sound/Makefile
> > @@ -7,6 +7,7 @@ obj-$(CONFIG_SOUND)     += sound.o
> >  obj-$(CONFIG_SOUND)    += codec-uclass.o
> >  obj-$(CONFIG_SOUND)    += i2s-uclass.o
> >  obj-$(CONFIG_SOUND)    += sound-uclass.o
> > +obj-$(CONFIG_SOUND_DA7219)     += da7219.o
> >  obj-$(CONFIG_I2S_SAMSUNG)      += samsung-i2s.o
> >  obj-$(CONFIG_SOUND_SANDBOX)    += sandbox.o
> >  obj-$(CONFIG_I2S_ROCKCHIP)     += rockchip_i2s.o rockchip_sound.o
> > diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c
> > new file mode 100644
> > index 0000000000..454e2591ed
> > --- /dev/null
> > +++ b/drivers/sound/da7219.c
> > @@ -0,0 +1,189 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * ACPI driver for DA7219 codec
> > + *
> > + * Copyright 2019 Google LLC
> > + * Parts taken from coreboot
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <i2c.h>
> > +#include <irq.h>
> > +#include <log.h>
> > +#include <acpi/acpigen.h>
> > +#include <acpi/acpi_device.h>
> > +#include <acpi/acpi_dp.h>
> > +#ifdef CONFIG_X86
> > +#include <asm/acpi_nhlt.h>
> > +#endif
> > +#include <asm-generic/gpio.h>
> > +#include <dt-bindings/sound/nhlt.h>
> > +#include <dm/acpi.h>
> > +
> > +#define DA7219_ACPI_HID                "DLGS7219"
> > +
> > +static int da7219_acpi_fill_ssdt(const struct udevice *dev,
> > +                                struct acpi_ctx *ctx)
> > +{
> > +       char scope[ACPI_PATH_MAX];
> > +       char name[ACPI_NAME_MAX];
> > +       struct acpi_dp *dsd, *aad;
> > +       ofnode node;
> > +       u32 val;
> > +       int ret;
> > +
> > +       ret = acpi_device_scope(dev, scope, sizeof(scope));
> > +       if (ret)
> > +               return log_msg_ret("scope", ret);
> > +       ret = acpi_get_name(dev, name);
> > +       if (ret)
> > +               return log_msg_ret("name", ret);
> > +
> > +       /* Device */
> > +       acpigen_write_scope(ctx, scope);
> > +       acpigen_write_device(ctx, name);
> > +       acpigen_write_name_string(ctx, "_HID", DA7219_ACPI_HID);
> > +       acpigen_write_name_integer(ctx, "_UID", 1);
> > +       acpigen_write_name_string(ctx, "_DDN",
> > +                                 dev_read_string(dev, "acpi,ddn"));
> > +       acpigen_write_name_integer(ctx, "_S0W", 4);
> > +       acpigen_write_sta(ctx, acpi_device_status(dev));
> > +
> > +       /* Resources */
> > +       acpigen_write_name(ctx, "_CRS");
> > +       acpigen_write_resourcetemplate_header(ctx);
> > +       ret = acpi_device_write_i2c_dev(ctx, dev);
> > +       if (ret)
> > +               return log_msg_ret("i2c", ret);
> > +
> > +       /* Use either Interrupt() or GpioInt() */
> > +       ret = acpi_device_write_interrupt_or_gpio(ctx, (struct udevice *)dev,
> > +                                                 "req-gpios");
> > +       if (ret)
> > +               return log_msg_ret("irq_gpio", ret);
> > +       acpigen_write_resourcetemplate_footer(ctx);
> > +
> > +       /* AAD Child Device Properties */
> > +       aad = acpi_dp_new_table("DAAD");
> > +       if (!aad)
> > +               return log_msg_ret("aad", -ENOMEM);
> > +
> > +       node = ofnode_find_subnode(dev_ofnode(dev), "da7219_aad");
> > +       if (!ofnode_valid(node))
> > +               return log_msg_ret("da7219_aad", -EINVAL);
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,btn-cfg");
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,mic-det-thr");
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,jack-ins-deb");
> > +       acpi_dp_ofnode_copy_str(node, aad, "dlg,jack-det-rate");
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,jack-rem-deb");
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,a-d-btn-thr");
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,d-b-btn-thr");
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,b-c-btn-thr");
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,c-mic-btn-thr");
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,btn-avg");
> > +       acpi_dp_ofnode_copy_int(node, aad, "dlg,adc-1bit-rpt");
> > +       if (!ofnode_read_u32(node, "dlg,micbias-pulse-lvl", &val)) {
> > +               acpi_dp_ofnode_copy_int(node, aad, "dlg,micbias-pulse-lvl");
> > +               acpi_dp_ofnode_copy_int(node, aad, "dlg,micbias-pulse-time");
> > +       }
> > +
> > +       /* DA7219 Properties */
> > +       dsd = acpi_dp_new_table("_DSD");
> > +       if (!dsd)
> > +               return log_msg_ret("dsd", -ENOMEM);
> > +       acpi_dp_dev_copy_int(dev, dsd, "dlg,micbias-lvl");
> > +       acpi_dp_dev_copy_str(dev, dsd, "dlg,mic-amp-in-sel");
> > +       acpi_dp_dev_copy_str(dev, dsd, "dlg,mclk-name");
> > +       acpi_dp_add_child(dsd, "da7219_aad", aad);
> > +
> > +       /* Write Device Property Hierarchy */
> > +       acpi_dp_write(ctx, dsd);
> > +
> > +       acpigen_pop_len(ctx); /* Device */
> > +       acpigen_pop_len(ctx); /* Scope */
> > +
> > +       return 0;
> > +}
> > +
> > +#ifdef CONFIG_X86
>
> Is the following not applied to non-x86 board?

As far as I know this is only supported on X86. This is an Intel
standard, starting with Skylake. I will add a comment.

>
> > +static const struct nhlt_format_config da7219_formats[] = {
> > +       /* 48 KHz 24-bits per sample. */
> > +       {
> > +               .num_channels = 2,
> > +               .sample_freq_khz = 48,
> > +               .container_bits_per_sample = 32,
> > +               .valid_bits_per_sample = 24,
> > +               .settings_file = "dialog-2ch-48khz-24b.dat",
> > +       },
> > +};
> > +
> > +static const struct nhlt_tdm_config tdm_config = {
> > +       .virtual_slot = 0,
> > +       .config_type = NHLT_TDM_BASIC,
> > +};
> > +
> > +static const struct nhlt_endp_descriptor da7219_descriptors[] = {
> > +       /* Render Endpoint */
> > +       {
> > +               .link = NHLT_LINK_SSP,
> > +               .device = NHLT_SSP_DEV_I2S,
> > +               .direction = NHLT_DIR_RENDER,
> > +               .vid = NHLT_VID,
> > +               .did = NHLT_DID_SSP,
> > +               .cfg = &tdm_config,
> > +               .cfg_size = sizeof(tdm_config),
> > +               .formats = da7219_formats,
> > +               .num_formats = ARRAY_SIZE(da7219_formats),
> > +       },
> > +       /* Capture Endpoint */
> > +       {
> > +               .link = NHLT_LINK_SSP,
> > +               .device = NHLT_SSP_DEV_I2S,
> > +               .direction = NHLT_DIR_CAPTURE,
> > +               .vid = NHLT_VID,
> > +               .did = NHLT_DID_SSP,
> > +               .cfg = &tdm_config,
> > +               .cfg_size = sizeof(tdm_config),
> > +               .formats = da7219_formats,
> > +               .num_formats = ARRAY_SIZE(da7219_formats),
> > +       },
> > +};
> > +
> > +static int da7219_acpi_setup_nhlt(const struct udevice *dev,
> > +                                 struct acpi_ctx *ctx)
> > +{
> > +       u32 hwlink;
> > +       int ret;
> > +
> > +       if (dev_read_u32(dev, "acpi,audio-link", &hwlink))
> > +               return log_msg_ret("link", -EINVAL);
> > +
> > +       /* Virtual bus id of SSP links are the hardware port ids proper. */
> > +       ret = nhlt_add_ssp_endpoints(ctx->nhlt, hwlink, da7219_descriptors,
>
> Where is this nhlt_add_ssp_endpoints() defined?

In a later patch. I will move it earlier.

>
> > +                                    ARRAY_SIZE(da7219_descriptors));
> > +       if (ret)
> > +               return log_msg_ret("add", ret);
> > +
> > +       return 0;
> > +}
> > +#endif
> > +
> > +struct acpi_ops da7219_acpi_ops = {
> > +       .fill_ssdt      = da7219_acpi_fill_ssdt,
> > +#ifdef CONFIG_X86
> > +       .setup_nhlt     = da7219_acpi_setup_nhlt,
> > +#endif
> > +};
> > +
> > +static const struct udevice_id da7219_ids[] = {
> > +       { .compatible = "dlg,da7219" },
> > +       { }
> > +};
> > +
> > +U_BOOT_DRIVER(da7219) = {
> > +       .name           = "da7219",
> > +       .id             = UCLASS_MISC,
> > +       .of_match       = da7219_ids,
> > +       ACPI_OPS_PTR(&da7219_acpi_ops)
> > +};
> > --
>

Regards,
SImon

[PATCH v1 22/43] x86: Add support for building up an NHLT structure

[Simon Glass]

Hi Wolfgang,

On Thu, 2 Jul 2020 at 02:11, Wolfgang Wallner
<wolfgang.wallner@br-automation.com> wrote:
>
> Hi Simon,
>
> I dont know NHLT well enough to actually review the code, but I did compare
> the files in this patch to the version in coreboot. Most of the changes are
> obvious (coding style, spelling, ...), but some things are not, see the remarks
> below.
>
> -----"Simon Glass" <sjg@chromium.org> schrieb: -----
> > Betreff: [PATCH v1 22/43] x86: Add support for building up an NHLT structure
> >
> > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > audio codecs and connections in a system. Various devices can contribute
> > information to produce the table.
> >
> > Add functions to allow adding to the structure that is eventually written
> > to the ACPI tables. Also add the device-tree bindings.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v1:
> > - Add a new patch to support building up an NHLT structure
> >
> >  arch/x86/include/asm/acpi_nhlt.h | 314 ++++++++++++++++++++
> >  arch/x86/lib/Makefile            |   1 +
> >  arch/x86/lib/acpi_nhlt.c         | 482 +++++++++++++++++++++++++++++++
> >  3 files changed, 797 insertions(+)
> >  create mode 100644 arch/x86/include/asm/acpi_nhlt.h
> >  create mode 100644 arch/x86/lib/acpi_nhlt.c
> >
> > diff --git a/arch/x86/include/asm/acpi_nhlt.h b/arch/x86/include/asm/acpi_nhlt.h
> > new file mode 100644
> > index 0000000000..4d2573d5ff
> > --- /dev/null
> > +++ b/arch/x86/include/asm/acpi_nhlt.h
> > @@ -0,0 +1,314 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2020 Google LLC
> > + *
> > + * Modified from coreboot nhlt.h
> > + */
> > +
> > +#ifndef _NHLT_H_
> > +#define _NHLT_H_
> > +
> > +struct acpi_ctx;
> > +struct nhlt;
> > +struct nhlt_endpoint;
> > +struct nhlt_format;
> > +struct nhlt_format_config;
> > +
> > +/*
> > + * Non HD Audio ACPI support. This table is typically used for Intel Smart
> > + * Sound Technology DSP. It provides a way to encode opaque settings in
> > + * the ACPI tables.
> > + *
> > + * While the structure fields of the NHLT structs are exposed below
> > + * the SoC/chipset code should be the only other user manipulating the
> > + * fields directly aside from the library itself.
> > + *
> > + * The NHLT table consists of endpoints which in turn contain different
> > + * supporting stream formats. Each endpoint may contain a device specific
> > + * configuration payload as well as each stream format.
> > + *
> > + * Most code should use the SoC variants of the functions because
> > + * there is required logic needed to be performed by the SoC. The SoC
> > + * code should be abstracting the inner details of these functions that
> > + * specically apply to NHLT objects for that SoC.
> > + *
> > + * An example sequence:
> > + *
> > + * nhlt = nhlt_init()
> > + * ep = nhlt_add_endpoint()
> > + * nhlt_endpoint_append_config(ep)
> > + * nhlt_endpoint_add_formats(ep)
> > + * nhlt_soc_serialise()
> > + */
> > +
> > +/* Obtain an nhlt object for adding endpoints. Returns NULL on error. */
> > +struct nhlt *nhlt_init(void);
> > +
> > +/* Return the size of the NHLT table including ACPI header. */
> > +size_t nhlt_current_size(struct nhlt *nhlt);
> > +
> > +/*
> > + * Helper functions for adding NHLT devices utilizing an nhlt_endp_descriptor
> > + * to drive the logic.
> > + */
> > +
> > +struct nhlt_endp_descriptor {
> > +     /* NHLT endpoint types. */
> > +     int link;
> > +     int device;
> > +     int direction;
> > +     u16 vid;
> > +     u16 did;
> > +     /* Optional endpoint specific configuration data. */
> > +     const void *cfg;
> > +     size_t cfg_size;
> > +     /* Formats supported for endpoint. */
> > +     const struct nhlt_format_config *formats;
> > +     size_t num_formats;
> > +};
> > +
> > +/*
> > + * Add the number of endpoints described by each descriptor. The virtual bus
> > + * id for each descriptor is the default value of 0.
> > + * Returns < 0 on error, 0 on success.
> > + */
> > +int nhlt_add_endpoints(struct nhlt *nhlt,
> > +                    const struct nhlt_endp_descriptor *epds,
> > +                    size_t num_epds);
> > +
> > +/*
> > + * Add the number of endpoints associated with a single NHLT SSP instance id.
> > + * Each endpoint described in the endpoint descriptor array uses the provided
> > + * virtual bus id. Returns < 0 on error, 0 on success.
> > + */
> > +int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id,
> > +                        const struct nhlt_endp_descriptor *epds,
> > +                        size_t num_epds);
> > +
> > +/*
> > + * Add endpoint to NHLT object. Returns NULL on error.
> > + *
> > + * generic nhlt_add_endpoint() is called by the SoC code to provide
> > + * the specific assumptions/uses for NHLT for that platform. All fields
> > + * are the NHLT enumerations found within this header file.
> > + */
> > +struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type,
> > +                                     int device_type, int dir,
> > +                                     u16 vid, u16 did);
> > +
> > +/*
> > + * Append blob of configuration to the endpoint proper. Returns 0 on
> > + * success, < 0 on error. A copy of the configuration is made so any
> > + * resources pointed to by config can be freed after the call.
> > + */
> > +int nhlt_endpoint_append_config(struct nhlt_endpoint *endpoint,
> > +                             const void *config, size_t config_sz);
> > +
> > +/* Add a format type to the provided endpoint. Returns NULL on error. */
> > +struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endpoint,
> > +                                 int num_channels, int sample_freq_khz,
> > +                                 int container_bits_per_sample,
> > +                                 int valid_bits_per_sample,
> > +                                 u32 speaker_mask);
> > +
> > +/*
> > + * Append blob of configuration to the format proper. Returns 0 on
> > + * success, < 0 on error. A copy of the configuration is made so any
> > + * resources pointed to by config can be freed after the call.
> > + */
> > +int nhlt_format_append_config(struct nhlt_format *format, const void *config,
> > +                           size_t config_sz);
> > +
> > +/*
> > + * Add num_formats described by formats to the endpoint. This function
> > + * effectively wraps nhlt_add_format() and nhlt_format_config() using the
> > + * data found in each nhlt_format_config object. Returns 0 on success, < 0
> > + * on error.
> > + */
> > +int nhlt_endpoint_add_formats(struct nhlt_endpoint *endpoint,
> > +                           const struct nhlt_format_config *formats,
> > +                           size_t num_formats);
> > +
> > +/*
> > + * Increment the instance id for a given link type. This function is
> > + * used for marking a device being completely added to the NHLT object.
> > + * Subsequent endpoints added to the nhlt object with the same link type
> > + * will use incremented instance id.
> > + */
> > +void nhlt_next_instance(struct nhlt *nhlt, int link_type);
> > +
> > +/*
> > + * Serialize NHLT object to ACPI table. Take in the beginning address of where
> > + * the table will reside and return the address of the next ACPI table. On
> > + * error 0 will be returned. The NHLT object is no longer valid after this
> > + * function is called.
> > + */
> > +uintptr_t nhlt_serialise(struct nhlt *nhlt, uintptr_t acpi_addr);
>
> The implementation for this functions seems to be missing in this patch.
> In coreboot it looks like this:
>
> uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr)
> {
>         return nhlt_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL, 0);
> }

Yes we don't need this at present. If we do we would likely put this
in the device tree. Since coreboot doesn't have a proper device tree
it uses code to call override functions to get the data, which IMO
makes it quite hard to work out the config for a particular board

[..]

> > +/*
> > + * Channel mask for an endpoint. While they are prefixed with 'SPEAKER' the
> > + * channel masks are also used for capture devices
> > + */
> > +enum {
> > +     SPEAKER_FRONT_LEFT = 1 << 0,
>
> Nit: BIT(0) ?

Yes will fix thanks.

[..]

> > +static int append_specific_config(struct nhlt_specific_config *spec_cfg,
> > +                               const void *config, size_t config_sz)
> > +{
> > +     size_t new_sz;
> > +     void *new_cfg;
> > +
>
> In coreboot this function starts with a check of config and config_sz:
>
> if (config == NULL || config_sz == 0)
>         return 0;
>
> Why is this check left out in this implementation?

We don't allow the config to be NULL since that is pointless. Same
with the size.

>
> > +     new_sz = spec_cfg->size + config_sz;
> > +     new_cfg = malloc(new_sz);
> > +     if (!new_cfg)
> > +             return -ENOMEM;

Regards,
SImon

[PATCH v1 25/43] x86: gpio: Add support for obtaining ACPI info for a GPIO

[Simon Glass]

Hi Bin,

On Tue, 30 Jun 2020 at 01:47, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Implement the method that converts a GPIO into the form used by ACPI, so
> > that GPIOs can be added to ACPI tables.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v1:
> > - Use acpi_get_path() to get device path
> >
> >  drivers/gpio/intel_gpio.c | 34 ++++++++++++++++++++++++++++++++++
> >  1 file changed, 34 insertions(+)
> >
> > diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c
> > index b4d5be97da..6a3a8c4cfa 100644
> > --- a/drivers/gpio/intel_gpio.c
> > +++ b/drivers/gpio/intel_gpio.c
> > @@ -12,6 +12,7 @@
> >  #include <pch.h>
> >  #include <pci.h>
> >  #include <syscon.h>
> > +#include <acpi/acpi_device.h>
> >  #include <asm/cpu.h>
> >  #include <asm/gpio.h>
> >  #include <asm/intel_pinctrl.h>
> > @@ -19,6 +20,7 @@
> >  #include <asm/io.h>
> >  #include <asm/pci.h>
> >  #include <asm/arch/gpio.h>
> > +#include <dm/acpi.h>
> >  #include <dt-bindings/gpio/x86-gpio.h>
> >
> >  static int intel_gpio_direction_input(struct udevice *dev, uint offset)
> > @@ -128,6 +130,35 @@ static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
> >         return 0;
> >  }
> >
> > +#if CONFIG_IS_ENABLED(ACPIGEN)
> > +static int intel_gpio_get_acpi(const struct gpio_desc *desc,
> > +                              struct acpi_gpio *gpio)
> > +{
> > +       struct udevice *pinctrl;
> > +       int ret;
> > +
> > +       if (!dm_gpio_is_valid(desc))
> > +               return -ENOENT;
> > +       pinctrl = dev_get_parent(desc->dev);
> > +
> > +       memset(gpio, '\0', sizeof(*gpio));
> > +
> > +       gpio->type = ACPI_GPIO_TYPE_IO;
> > +       gpio->pull = ACPI_GPIO_PULL_DEFAULT;
> > +       gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
> > +       gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
>
> Is there a way to figure out these properties from DT, instead of hardcoding?

The answer is similar to your previous comment. But also, each pinctrl
driver has its own settings and limitations. If we want to support
different config for the pinctrl we would likely add it to the DT
binding for the pinctrl driver. So far I haven't seen a need but it
might happen with a future arch.

[..]

Regards,
Simon

[PATCH v1 28/43] i2c: designware_i2c: Support ACPI table generation

[Simon Glass]

Hi Wolfgang,

On Thu, 25 Jun 2020 at 06:46, Wolfgang Wallner
<wolfgang.wallner@br-automation.com> wrote:
>
> Hi Simon,
>
> -----"Simon Glass" <sjg@chromium.org> schrieb: -----
> > Betreff: [PATCH v1 28/43] i2c: designware_i2c: Support ACPI table generation
> >
> > Update the PCI driver to generate ACPI information so that Linux has the
> > full information about each I2C bus.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> >
> > ---
> >
> > Changes in v1:
> > - Capitalise ACPI_OPS_PTR
> >
> >  drivers/i2c/designware_i2c.c     |  25 ++++++++
> >  drivers/i2c/designware_i2c.h     |  15 +++++
> >  drivers/i2c/designware_i2c_pci.c | 104 ++++++++++++++++++++++++++++++-
> >  3 files changed, 143 insertions(+), 1 deletion(-)
> >

[.]

> > +/*
> > + * Write ACPI object to describe speed configuration.
> > + *
> > + * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
> > + *
> > + * SSCN: I2C_SPEED_STANDARD
> > + * FMCN: I2C_SPEED_FAST
> > + * FPCN: I2C_SPEED_FAST_PLUS
> > + * HSCN: I2C_SPEED_HIGH
> > + */
> > +static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
> > +                                        struct dw_i2c_speed_config *config)
> > +{
> > +     switch (config->speed_mode) {
> > +     case IC_SPEED_MODE_HIGH:
> > +             acpigen_write_name(ctx, "HSCN");
> > +             break;
> > +     case IC_SPEED_MODE_FAST_PLUS:
> > +             acpigen_write_name(ctx, "FPCN");
> > +             break;
> > +     case IC_SPEED_MODE_FAST:
> > +             acpigen_write_name(ctx, "FMCN");
> > +             break;
> > +     case IC_SPEED_MODE_STANDARD:
> > +     default:
> > +             acpigen_write_name(ctx, "SSCN");
> > +     }
> > +
> > +     /* Package () { scl_lcnt, scl_hcnt, sda_hold } */
> > +     acpigen_write_package(ctx, 3);
> > +     acpigen_write_word(ctx, config->scl_hcnt);
> > +     acpigen_write_word(ctx, config->scl_lcnt);
> > +     acpigen_write_dword(ctx, config->sda_hold);
> > +     acpigen_pop_len(ctx);
> > +}
>
> This function is rather generic, and probably the same for any I2C controller.
> Is the intention to implement it for Designware as a first step and move it to
> a generic place if the need arises, or should it stay here?

So far I have only not seen Intel SoCs use anything other than
designware I2C. If that happens then the encoding may well be the same
and we could end up with some common code. But I am not sure at
present. The kernel I2C driver that reads this is designware ony, from
what I can tell.

Regards,
Simon

[PATCH v1 32/43] pmc: Move common registers to the header file

[Simon Glass]

Hi Bin,

On Tue, 30 Jun 2020 at 02:27, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > These registers need to be accesses from ACPI code, so move them to the
> > header file.
> >
>
> I don't think these are common offset to every platform.

That's right, but they are common to the boards that use this uclass
and driver - I am only moving them.

If we end up supporting more SoCs we may need a way to specify this in
the DT or through a driver, but for now, I'm just moving from the
uclass to the header.

Regards,
Simon

[PATCH v1 33/43] x86: irq: Support flags for acpi_gpe

[Simon Glass]

Hi Wolfgang,

On Wed, 1 Jul 2020 at 09:15, Wolfgang Wallner
<wolfgang.wallner@br-automation.com> wrote:
>
> Hi Simon,
>
> -----"Simon Glass" <sjg@chromium.org> schrieb: -----
>
> > Betreff: [PATCH v1 33/43] x86: irq: Support flags for acpi_gpe
> >
> > This binding currently has a flags cell but it is not used. Make use of it
> > to create ACPI tables for interrupts.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  arch/x86/cpu/acpi_gpe.c                       | 26 +++++++++++++++++++
> >  .../interrupt-controller/x86-irq.h            | 14 ++++++++++
> >  2 files changed, 40 insertions(+)
> >  create mode 100644 include/dt-bindings/interrupt-controller/x86-irq.h
> >
>
> [snip]
>
> > diff --git a/include/dt-bindings/interrupt-controller/x86-irq.h b/include/dt-bindings/interrupt-controller/x86-irq.h
> > new file mode 100644
> > index 0000000000..9e0b4612e1
> > --- /dev/null
> > +++ b/include/dt-bindings/interrupt-controller/x86-irq.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright 2019 Google LLC
> > + *
> > + * This provides additional flags used by x86.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H
> > +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H
> > +
> > +#define X86_IRQ_TYPE_SHARED  (1 << 4)
> > +#define X86_IRQ_TYPE_WAKE    (1 << 5)
>
> Nit: BIT(4) and BIT(4) ?

I can't use those in devicetree bindings unfortunately.

Regards,
SImon

[PATCH v1 34/43] x86: apl: Fix save/restore of ITSS priorities

[Simon Glass]

Hi Bin,

On Tue, 30 Jun 2020 at 02:27, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > The FSP-S changes the ITSS priorities. The code that tries to save it
> > before running FSP-S and restore it afterwards does not work as U-Boot
> > relocates in between the save and restore. This means that the driver
> > data saved before relocation is lost and the new driver just sees zeroes.
> >
> > Fix this by allocating space in the relocated memory for the ITSS data.
> > Save it there and access it from the driver after relocation.
> >
> > This fixes interrupt handling on coral.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  arch/x86/cpu/apollolake/fsp_s.c    | 11 +++++------
> >  arch/x86/cpu/cpu.c                 | 13 +++++++++++++
> >  arch/x86/cpu/intel_common/itss.c   | 25 +++++++++++++++++++++++--
> >  arch/x86/include/asm/global_data.h |  1 +
> >  arch/x86/include/asm/itss.h        |  2 +-
> >  drivers/misc/irq-uclass.c          |  2 +-
> >  6 files changed, 44 insertions(+), 10 deletions(-)
> >
[..]

> > diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
> > index 98bc79eaba..6b32b451a6 100644
> > --- a/drivers/misc/irq-uclass.c
> > +++ b/drivers/misc/irq-uclass.c
> > @@ -170,7 +170,7 @@ int irq_first_device_type(enum irq_dev_t type, struct udevice **devp)
> >
> >         ret = uclass_first_device_drvdata(UCLASS_IRQ, type, devp);
> >         if (ret)
> > -               return log_msg_ret("find", ret);
> > +               return ret;
>
> Is this change intended?

Yes but I forgot to mention it in the commit message. Will add it.

Regards,
Simon

[PATCH v1 37/43] x86: Store the coreboot table address in global_data

[Simon Glass]

Hi Wolfgang,

On Wed, 1 Jul 2020 at 09:16, Wolfgang Wallner
<wolfgang.wallner@br-automation.com> wrote:
>
> Hi Simon,
>
> -----"Simon Glass" <sjg@chromium.org> schrieb: -----
> > Betreff: [PATCH v1 37/43] x86: Store the coreboot table address in global_data
> >
> > At present this information is used to locate and parse the tables but is
> > not stored. Store it so that we can display it to the user, e.g. with the
> > 'bdinfo' command.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  arch/x86/cpu/coreboot/tables.c     | 8 +++++++-
> >  arch/x86/cpu/i386/cpu.c            | 7 ++++++-
> >  arch/x86/include/asm/global_data.h | 1 +
> >  3 files changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
> > index a5d31d1dea..1594b4a8b2 100644
> > --- a/arch/x86/cpu/coreboot/tables.c
> > +++ b/arch/x86/cpu/coreboot/tables.c
> > @@ -10,6 +10,8 @@
> >  #include <net.h>
> >  #include <asm/arch/sysinfo.h>
> >
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> >  /*
> >   * This needs to be in the .data section so that it's copied over during
> >   * relocation. By default it's put in the .bss section which is simply filled
> > @@ -243,6 +245,10 @@ int get_coreboot_info(struct sysinfo_t *info)
> >       if (addr < 0)
> >               return addr;
> >       ret = cb_parse_header((void *)addr, 0x1000, info);
> > +     if (!ret)
> > +             return -ENOENT;
> > +     gd->arch.coreboot_table = addr;
> > +     gd->flags |= GD_FLG_SKIP_LL_INIT;
>
> Why is GD_FLG_SKIP_LL_INIT now set in get_coreboot_info()?

I found that we need to set it both when running the actual coreboot
build and when running a bare-metal board. So this is the best place
to do it.

Regards,
Simon

[PATCH v1 38/43] x86: mp: Allow use of mp_run_on_cpus() without MP

[Simon Glass]

Hi Bin,

On Tue, 30 Jun 2020 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present if MP is not enabled (e.g. booting from coreboot) the 'mtrr'
> > command does not work correctly. It is not easy to make it work for all
> > CPUs, since coreboot has halted them and we would need to start them up
> > again, but it is easy enough to make them work on the boot CPU.
> >
> > Update the code to avoid assuming that the MP init routine has completed,
> > so that this can work.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  arch/x86/cpu/mp_init.c | 12 ++++++++----
> >  1 file changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
> > index ef33a38017..c0ae24686e 100644
> > --- a/arch/x86/cpu/mp_init.c
> > +++ b/arch/x86/cpu/mp_init.c
> > @@ -454,7 +454,7 @@ static int get_bsp(struct udevice **devp, int *cpu_countp)
> >         if (cpu_countp)
> >                 *cpu_countp = ret;
> >
> > -       return dev->req_seq;
> > +       return dev->req_seq >= 0 ? dev->req_seq : 0;
> >  }
> >
> >  static struct mp_callback *read_callback(struct mp_callback **slot)
> > @@ -589,9 +589,6 @@ int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg)
> >         int num_cpus;
> >         int ret;
> >
> > -       if (!(gd->flags & GD_FLG_SMP_INIT))
> > -               return -ENXIO;
> > -
> >         ret = get_bsp(&dev, &num_cpus);
> >         if (ret < 0)
> >                 return log_msg_ret("bsp", ret);
> > @@ -601,6 +598,13 @@ int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg)
> >                 func(arg);
> >         }
> >
> > +       if (!(gd->flags & GD_FLG_SMP_INIT)) {
> > +               /* Allow use of this function on the BSP only */
> > +               if (cpu_select == MP_SELECT_BSP || !cpu_select)
>
> This assumes 0 is the BSP cpu number?

We until i SMP is inited, then it is assumed to be CPU 0, yes.

I ended up pulling this fix into the MTRR series as I had to fix the
minnowmax bug.

Regards,
Simon

[PATCH v1 40/43] x86: Drop setup_pcat_compatibility()

[Simon Glass]

Hi Bin,

On Tue, 30 Jun 2020 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > This function does not exist anymore. Drop it from the header file.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  arch/x86/include/asm/u-boot-x86.h | 2 --
> >  1 file changed, 2 deletions(-)
> >
>
> The function is in zimage.c
>
> ./arch/x86/lib/zimage.c:307:void setup_pcat_compatibility(void)
> ./arch/x86/lib/zimage.c:308:    __attribute__((weak,
> alias("__setup_pcat_compatibility")));
> ./arch/x86/lib/zimage.c:310:void __setup_pcat_compatibility(void)
> ./arch/x86/lib/zimage.c:327:    setup_pcat_compatibility();

Ooops I meant to remove it from there also. Will do.

Regards,
SImon

[PATCH v1 02/43] binman: Refactor binman_entry_find() to allow other nodes

[Bin Meng]

+Tom,

On Wed, Jul 8, 2020 at 10:23 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Bin,
>
> On Mon, 29 Jun 2020 at 20:33, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > At present we can only read from a top-level binman node entry. Refactor
> > > this function to produce a second local function which supports reading
> > > from any node.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > >  lib/binman.c | 18 ++++++++++++------
> > >  1 file changed, 12 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/lib/binman.c b/lib/binman.c
> > > index dc3a880882..79d01230dd 100644
> > > --- a/lib/binman.c
> > > +++ b/lib/binman.c
> > > @@ -29,25 +29,31 @@ struct binman_info {
> > >
> > >  static struct binman_info *binman;
> > >
> > > -int binman_entry_find(const char *name, struct binman_entry *entry)
> > > +int binman_entry_find_(ofnode node, const char *name, struct binman_entry *entry)
> >
> > This one should be static. We really should agree on a naming
> > convention for such internal APIs. I would prefer adding _internal
> > suffix, or using __ prefix
>
> Well I think internal is too long and I like a trailing underscore.
>

The trailing underscore is easy to be misread.

> The trailing double underscore is reserved for the compiler.
>

What I prefer is the leading double underscore which I think is allowed.

> Another option is to drop the prefix, so:
>
> find_entry(...)

Regards,
Bin

[PATCH v1 22/43] x86: Add support for building up an NHLT structure

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: Re: [PATCH v1 22/43] x86: Add support for building up an NHLT structure
> 
> Hi Wolfgang,
> 
> On Thu, 2 Jul 2020 at 02:11, Wolfgang Wallner
> <wolfgang.wallner@br-automation.com> wrote:
> >
> > Hi Simon,
> >
> > I dont know NHLT well enough to actually review the code, but I did compare
> > the files in this patch to the version in coreboot. Most of the changes are
> > obvious (coding style, spelling, ...), but some things are not, see the remarks
> > below.
> >
> > -----"Simon Glass" <sjg@chromium.org> schrieb: -----
> > > Betreff: [PATCH v1 22/43] x86: Add support for building up an NHLT structure
> > >
> > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > audio codecs and connections in a system. Various devices can contribute
> > > information to produce the table.
> > >
> > > Add functions to allow adding to the structure that is eventually written
> > > to the ACPI tables. Also add the device-tree bindings.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > > Changes in v1:
> > > - Add a new patch to support building up an NHLT structure
> > >
> > >  arch/x86/include/asm/acpi_nhlt.h | 314 ++++++++++++++++++++
> > >  arch/x86/lib/Makefile            |   1 +
> > >  arch/x86/lib/acpi_nhlt.c         | 482 +++++++++++++++++++++++++++++++
> > >  3 files changed, 797 insertions(+)
> > >  create mode 100644 arch/x86/include/asm/acpi_nhlt.h
> > >  create mode 100644 arch/x86/lib/acpi_nhlt.c
> > >
> > > diff --git a/arch/x86/include/asm/acpi_nhlt.h b/arch/x86/include/asm/acpi_nhlt.h
> > > new file mode 100644
> > > index 0000000000..4d2573d5ff
> > > --- /dev/null
> > > +++ b/arch/x86/include/asm/acpi_nhlt.h

[snip]

> > > +
> > > +/*
> > > + * Serialize NHLT object to ACPI table. Take in the beginning address of where
> > > + * the table will reside and return the address of the next ACPI table. On
> > > + * error 0 will be returned. The NHLT object is no longer valid after this
> > > + * function is called.
> > > + */
> > > +uintptr_t nhlt_serialise(struct nhlt *nhlt, uintptr_t acpi_addr);
> >
> > The implementation for this functions seems to be missing in this patch.
> > In coreboot it looks like this:
> >
> > uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr)
> > {
> >         return nhlt_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL, 0);
> > }
> 
> Yes we don't need this at present. If we do we would likely put this
> in the device tree. Since coreboot doesn't have a proper device tree
> it uses code to call override functions to get the data, which IMO
> makes it quite hard to work out the config for a particular board

If we don't need the implementation of nhlt_serialise(), shouldn't we then
also drop its declaration in the header file?

> 
> [..]
> 

regards, Wolfgang

[PATCH v1 25/43] x86: gpio: Add support for obtaining ACPI info for a GPIO

[Wolfgang Wallner]

Hi Simon, Bin,

-----"Simon Glass" <sjg@chromium.org> schrieb: -----
> Betreff: Re: [PATCH v1 25/43] x86: gpio: Add support for obtaining ACPI info for a GPIO
> 
> Hi Bin,
> 
> On Tue, 30 Jun 2020 at 01:47, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Implement the method that converts a GPIO into the form used by ACPI, so
> > > that GPIOs can be added to ACPI tables.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > > Changes in v1:
> > > - Use acpi_get_path() to get device path
> > >
> > >  drivers/gpio/intel_gpio.c | 34 ++++++++++++++++++++++++++++++++++
> > >  1 file changed, 34 insertions(+)
> > >
> > > diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c
> > > index b4d5be97da..6a3a8c4cfa 100644
> > > --- a/drivers/gpio/intel_gpio.c
> > > +++ b/drivers/gpio/intel_gpio.c
> > > @@ -12,6 +12,7 @@
> > >  #include <pch.h>
> > >  #include <pci.h>
> > >  #include <syscon.h>
> > > +#include <acpi/acpi_device.h>
> > >  #include <asm/cpu.h>
> > >  #include <asm/gpio.h>
> > >  #include <asm/intel_pinctrl.h>
> > > @@ -19,6 +20,7 @@
> > >  #include <asm/io.h>
> > >  #include <asm/pci.h>
> > >  #include <asm/arch/gpio.h>
> > > +#include <dm/acpi.h>
> > >  #include <dt-bindings/gpio/x86-gpio.h>
> > >
> > >  static int intel_gpio_direction_input(struct udevice *dev, uint offset)
> > > @@ -128,6 +130,35 @@ static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
> > >         return 0;
> > >  }
> > >
> > > +#if CONFIG_IS_ENABLED(ACPIGEN)
> > > +static int intel_gpio_get_acpi(const struct gpio_desc *desc,
> > > +                              struct acpi_gpio *gpio)
> > > +{
> > > +       struct udevice *pinctrl;
> > > +       int ret;
> > > +
> > > +       if (!dm_gpio_is_valid(desc))
> > > +               return -ENOENT;
> > > +       pinctrl = dev_get_parent(desc->dev);
> > > +
> > > +       memset(gpio, '\0', sizeof(*gpio));
> > > +
> > > +       gpio->type = ACPI_GPIO_TYPE_IO;
> > > +       gpio->pull = ACPI_GPIO_PULL_DEFAULT;
> > > +       gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
> > > +       gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
> >
> > Is there a way to figure out these properties from DT, instead of hardcoding?
> 
> The answer is similar to your previous comment. But also, each pinctrl
> driver has its own settings and limitations. If we want to support
> different config for the pinctrl we would likely add it to the DT
> binding for the pinctrl driver. So far I haven't seen a need but it
> might happen with a future arch.

Could gpio->pull and gpio->polarity be set depending on desc->flags?

What is the reason for setting gpio->io_restrict to
ACPI_GPIO_IO_RESTRICT_OUTPUT?

> [..]

regards, Wolfgang

[PATCH v1 02/43] binman: Refactor binman_entry_find() to allow other nodes

[Tom Rini]

On Wed, Jul 08, 2020 at 12:07:24PM +0800, Bin Meng wrote:
> +Tom,
> 
> On Wed, Jul 8, 2020 at 10:23 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 29 Jun 2020 at 20:33, Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > At present we can only read from a top-level binman node entry. Refactor
> > > > this function to produce a second local function which supports reading
> > > > from any node.
> > > >
> > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > ---
> > > >
> > > >  lib/binman.c | 18 ++++++++++++------
> > > >  1 file changed, 12 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/lib/binman.c b/lib/binman.c
> > > > index dc3a880882..79d01230dd 100644
> > > > --- a/lib/binman.c
> > > > +++ b/lib/binman.c
> > > > @@ -29,25 +29,31 @@ struct binman_info {
> > > >
> > > >  static struct binman_info *binman;
> > > >
> > > > -int binman_entry_find(const char *name, struct binman_entry *entry)
> > > > +int binman_entry_find_(ofnode node, const char *name, struct binman_entry *entry)
> > >
> > > This one should be static. We really should agree on a naming
> > > convention for such internal APIs. I would prefer adding _internal
> > > suffix, or using __ prefix
> >
> > Well I think internal is too long and I like a trailing underscore.
> >
> 
> The trailing underscore is easy to be misread.
> 
> > The trailing double underscore is reserved for the compiler.
> >
> 
> What I prefer is the leading double underscore which I think is allowed.
> 
> > Another option is to drop the prefix, so:
> >
> > find_entry(...)

I don't like using _ as a suffix.  Double leading underscore is what we
use elsewhere, so I think that's my preference as well.

-- 
Tom
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[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Simon Glass]

Hi Bin,

On Tue, 7 Jul 2020 at 21:25, Simon Glass <sjg@chromium.org> wrote:
>
> Hi Bin,
>
> On Mon, 6 Jul 2020 at 18:22, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Tue, Jul 7, 2020 at 3:22 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Hi Bin,
> > >
> > > On Thu, 2 Jul 2020 at 22:33, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > >
> > > > Hi Simon,
> > > >
> > > > On Fri, Jul 3, 2020 at 11:50 AM Simon Glass <sjg@chromium.org> wrote:
> > > > >
> > > > > Hi Bin,
> > > > >
> > > > > On Thu, 2 Jul 2020 at 18:54, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > >
> > > > > > Hi Simon,
> > > > > >
> > > > > > On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > > >
> > > > > > > Hi Bin,
> > > > > > >
> > > > > > > On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > > > >
> > > > > > > > Hi Simon,
> > > > > > > >
> > > > > > > > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > > > > >
> > > > > > > > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > > > > > > > audio codecs and connections in a system. Various devices can contribute
> > > > > > > > > information to produce the table.
> > > > > > > > >
> > > > > > > > > Add core support for this, based on a structure which is built up through
> > > > > > > > > calls to the driver.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > > > > > > ---
> > > > > > > > >
> > > > > > > > >  drivers/core/acpi.c | 15 +++++++++++++++
> > > > > > > > >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> > > > > > > > >  2 files changed, 41 insertions(+)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > > > > > > > > index ea304a3067..a5053fec6f 100644
> > > > > > > > > --- a/drivers/core/acpi.c
> > > > > > > > > +++ b/drivers/core/acpi.c
> > > > > > > > > @@ -31,6 +31,7 @@ enum method_t {
> > > > > > > > >         METHOD_WRITE_TABLES,
> > > > > > > > >         METHOD_FILL_SSDT,
> > > > > > > > >         METHOD_INJECT_DSDT,
> > > > > > > > > +       METHOD_SETUP_NHLT,
> > > > > > > >
> > > > > > > > Do we really need to promote this to be an ACPI core method? Can we
> > > > > > > > reuse the SSDT/DSDT one?
> > > > > > >
> > > > > > > I don't think so. Those two are for a particular purpose. In fact NHLT
> > > > > > > is generated while doing SSDT I think. The idea is that drivers that
> > > > > > > want to contribute to NHLT can do so. But we cannot use the SSDT
> > > > > > > mechanism since each driver contributes only a part of the info, and
> > > > > > > we need something else to bring it all together.
> > > > > >
> > > > > > Will there be only one device that sets up the NHLT info?
> > > > >
> > > > > WIth coral it is two devices. I'm not sure of the maximum, but I
> > > > > suppose it depends on the audio codecs present.
> > > >
> > > > Could we make this method to be provided by the codec device, instead
> > > > of a generic ACPI core method?
> > >
> > > The codec device does implement this. See the drivers where they
> > > actually implement the NHLT method.
> > >
> > > This is definitely an ACPI-specific thing, so I think we need core
> > > support for iterating through drivers that want to provide this info.
> >
> > My concern is that this is not generic enough to promote this to ACPI core.
> >
> > I wanted to have something like this:
> >
> > Create a codec uclass driver, and in the code uclass driver, create an
> > op that is used to set up the NHLT infor if ACPI_GEN is on.
>
> We already have UCLASS_SOUND so could add it to sound_ops. But that
> seems weird to me since this is not an operation to play a sound. We
> do this with GIPOs and IRQs but in that case the operation returns
> some data. Here we are asking the driver to add some data to a table.
> I'm just not sure it makes sense.
>
> What do you think?

Let me know what you think about this as I'd like to finish this series.

Regards,
SImon

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Bin Meng]

Hi Simon,

On Mon, Jul 13, 2020 at 3:37 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Bin,
>
> On Tue, 7 Jul 2020 at 21:25, Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 6 Jul 2020 at 18:22, Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Tue, Jul 7, 2020 at 3:22 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > On Thu, 2 Jul 2020 at 22:33, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > >
> > > > > Hi Simon,
> > > > >
> > > > > On Fri, Jul 3, 2020 at 11:50 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > >
> > > > > > Hi Bin,
> > > > > >
> > > > > > On Thu, 2 Jul 2020 at 18:54, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > > >
> > > > > > > Hi Simon,
> > > > > > >
> > > > > > > On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > > > >
> > > > > > > > Hi Bin,
> > > > > > > >
> > > > > > > > On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > > > > >
> > > > > > > > > Hi Simon,
> > > > > > > > >
> > > > > > > > > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > > > > > >
> > > > > > > > > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > > > > > > > > audio codecs and connections in a system. Various devices can contribute
> > > > > > > > > > information to produce the table.
> > > > > > > > > >
> > > > > > > > > > Add core support for this, based on a structure which is built up through
> > > > > > > > > > calls to the driver.
> > > > > > > > > >
> > > > > > > > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > > > > > > > ---
> > > > > > > > > >
> > > > > > > > > >  drivers/core/acpi.c | 15 +++++++++++++++
> > > > > > > > > >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> > > > > > > > > >  2 files changed, 41 insertions(+)
> > > > > > > > > >
> > > > > > > > > > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > > > > > > > > > index ea304a3067..a5053fec6f 100644
> > > > > > > > > > --- a/drivers/core/acpi.c
> > > > > > > > > > +++ b/drivers/core/acpi.c
> > > > > > > > > > @@ -31,6 +31,7 @@ enum method_t {
> > > > > > > > > >         METHOD_WRITE_TABLES,
> > > > > > > > > >         METHOD_FILL_SSDT,
> > > > > > > > > >         METHOD_INJECT_DSDT,
> > > > > > > > > > +       METHOD_SETUP_NHLT,
> > > > > > > > >
> > > > > > > > > Do we really need to promote this to be an ACPI core method? Can we
> > > > > > > > > reuse the SSDT/DSDT one?
> > > > > > > >
> > > > > > > > I don't think so. Those two are for a particular purpose. In fact NHLT
> > > > > > > > is generated while doing SSDT I think. The idea is that drivers that
> > > > > > > > want to contribute to NHLT can do so. But we cannot use the SSDT
> > > > > > > > mechanism since each driver contributes only a part of the info, and
> > > > > > > > we need something else to bring it all together.
> > > > > > >
> > > > > > > Will there be only one device that sets up the NHLT info?
> > > > > >
> > > > > > WIth coral it is two devices. I'm not sure of the maximum, but I
> > > > > > suppose it depends on the audio codecs present.
> > > > >
> > > > > Could we make this method to be provided by the codec device, instead
> > > > > of a generic ACPI core method?
> > > >
> > > > The codec device does implement this. See the drivers where they
> > > > actually implement the NHLT method.
> > > >
> > > > This is definitely an ACPI-specific thing, so I think we need core
> > > > support for iterating through drivers that want to provide this info.
> > >
> > > My concern is that this is not generic enough to promote this to ACPI core.
> > >
> > > I wanted to have something like this:
> > >
> > > Create a codec uclass driver, and in the code uclass driver, create an
> > > op that is used to set up the NHLT infor if ACPI_GEN is on.
> >
> > We already have UCLASS_SOUND so could add it to sound_ops. But that
> > seems weird to me since this is not an operation to play a sound. We
> > do this with GIPOs and IRQs but in that case the operation returns
> > some data. Here we are asking the driver to add some data to a table.
> > I'm just not sure it makes sense.
> >
> > What do you think?
>
> Let me know what you think about this as I'd like to finish this series.

I haven't looked into the details of NHLT but I trust your
consideration so let's leave this as it is.

Regards,
Bin

[PATCH v1 07/43] dm: acpi: Add support for the NHLT table

[Simon Glass]

Hi Bin,

On Mon, 13 Jul 2020 at 00:10, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jul 13, 2020 at 3:37 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 7 Jul 2020 at 21:25, Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Hi Bin,
> > >
> > > On Mon, 6 Jul 2020 at 18:22, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > >
> > > > Hi Simon,
> > > >
> > > > On Tue, Jul 7, 2020 at 3:22 AM Simon Glass <sjg@chromium.org> wrote:
> > > > >
> > > > > Hi Bin,
> > > > >
> > > > > On Thu, 2 Jul 2020 at 22:33, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > >
> > > > > > Hi Simon,
> > > > > >
> > > > > > On Fri, Jul 3, 2020 at 11:50 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > > >
> > > > > > > Hi Bin,
> > > > > > >
> > > > > > > On Thu, 2 Jul 2020 at 18:54, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > > > >
> > > > > > > > Hi Simon,
> > > > > > > >
> > > > > > > > On Fri, Jul 3, 2020 at 8:46 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > > > > >
> > > > > > > > > Hi Bin,
> > > > > > > > >
> > > > > > > > > On Mon, 29 Jun 2020 at 20:49, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > > > > > > > >
> > > > > > > > > > Hi Simon,
> > > > > > > > > >
> > > > > > > > > > On Mon, Jun 15, 2020 at 11:57 AM Simon Glass <sjg@chromium.org> wrote:
> > > > > > > > > > >
> > > > > > > > > > > The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
> > > > > > > > > > > audio codecs and connections in a system. Various devices can contribute
> > > > > > > > > > > information to produce the table.
> > > > > > > > > > >
> > > > > > > > > > > Add core support for this, based on a structure which is built up through
> > > > > > > > > > > calls to the driver.
> > > > > > > > > > >
> > > > > > > > > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > > > > > > > > ---
> > > > > > > > > > >
> > > > > > > > > > >  drivers/core/acpi.c | 15 +++++++++++++++
> > > > > > > > > > >  include/dm/acpi.h   | 26 ++++++++++++++++++++++++++
> > > > > > > > > > >  2 files changed, 41 insertions(+)
> > > > > > > > > > >
> > > > > > > > > > > diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c
> > > > > > > > > > > index ea304a3067..a5053fec6f 100644
> > > > > > > > > > > --- a/drivers/core/acpi.c
> > > > > > > > > > > +++ b/drivers/core/acpi.c
> > > > > > > > > > > @@ -31,6 +31,7 @@ enum method_t {
> > > > > > > > > > >         METHOD_WRITE_TABLES,
> > > > > > > > > > >         METHOD_FILL_SSDT,
> > > > > > > > > > >         METHOD_INJECT_DSDT,
> > > > > > > > > > > +       METHOD_SETUP_NHLT,
> > > > > > > > > >
> > > > > > > > > > Do we really need to promote this to be an ACPI core method? Can we
> > > > > > > > > > reuse the SSDT/DSDT one?
> > > > > > > > >
> > > > > > > > > I don't think so. Those two are for a particular purpose. In fact NHLT
> > > > > > > > > is generated while doing SSDT I think. The idea is that drivers that
> > > > > > > > > want to contribute to NHLT can do so. But we cannot use the SSDT
> > > > > > > > > mechanism since each driver contributes only a part of the info, and
> > > > > > > > > we need something else to bring it all together.
> > > > > > > >
> > > > > > > > Will there be only one device that sets up the NHLT info?
> > > > > > >
> > > > > > > WIth coral it is two devices. I'm not sure of the maximum, but I
> > > > > > > suppose it depends on the audio codecs present.
> > > > > >
> > > > > > Could we make this method to be provided by the codec device, instead
> > > > > > of a generic ACPI core method?
> > > > >
> > > > > The codec device does implement this. See the drivers where they
> > > > > actually implement the NHLT method.
> > > > >
> > > > > This is definitely an ACPI-specific thing, so I think we need core
> > > > > support for iterating through drivers that want to provide this info.
> > > >
> > > > My concern is that this is not generic enough to promote this to ACPI core.
> > > >
> > > > I wanted to have something like this:
> > > >
> > > > Create a codec uclass driver, and in the code uclass driver, create an
> > > > op that is used to set up the NHLT infor if ACPI_GEN is on.
> > >
> > > We already have UCLASS_SOUND so could add it to sound_ops. But that
> > > seems weird to me since this is not an operation to play a sound. We
> > > do this with GIPOs and IRQs but in that case the operation returns
> > > some data. Here we are asking the driver to add some data to a table.
> > > I'm just not sure it makes sense.
> > >
> > > What do you think?
> >
> > Let me know what you think about this as I'd like to finish this series.
>
> I haven't looked into the details of NHLT but I trust your
> consideration so let's leave this as it is.

I think both approaches require bending in some direction due to the
fact that the data structure is 'built up' during the calls, but not
added to ACPI until all calls are done.

I'll try a little series to switch it the other way so we can compare it.

Regards,
Simon

[PATCH v1 25/43] x86: gpio: Add support for obtaining ACPI info for a GPIO

[Simon Glass]

Hi Wolfgang,

On Wed, 8 Jul 2020 at 05:06, Wolfgang Wallner
<wolfgang.wallner@br-automation.com> wrote:
>
> Hi Simon, Bin,
>
> -----"Simon Glass" <sjg@chromium.org> schrieb: -----
> > Betreff: Re: [PATCH v1 25/43] x86: gpio: Add support for obtaining ACPI info for a GPIO
> >
> > Hi Bin,
> >
> > On Tue, 30 Jun 2020 at 01:47, Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Mon, Jun 15, 2020 at 11:58 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > Implement the method that converts a GPIO into the form used by ACPI, so
> > > > that GPIOs can be added to ACPI tables.
> > > >
> > > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > > ---
> > > >
> > > > Changes in v1:
> > > > - Use acpi_get_path() to get device path
> > > >
> > > >  drivers/gpio/intel_gpio.c | 34 ++++++++++++++++++++++++++++++++++
> > > >  1 file changed, 34 insertions(+)
> > > >
> > > > diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c
> > > > index b4d5be97da..6a3a8c4cfa 100644
> > > > --- a/drivers/gpio/intel_gpio.c
> > > > +++ b/drivers/gpio/intel_gpio.c
> > > > @@ -12,6 +12,7 @@
> > > >  #include <pch.h>
> > > >  #include <pci.h>
> > > >  #include <syscon.h>
> > > > +#include <acpi/acpi_device.h>
> > > >  #include <asm/cpu.h>
> > > >  #include <asm/gpio.h>
> > > >  #include <asm/intel_pinctrl.h>
> > > > @@ -19,6 +20,7 @@
> > > >  #include <asm/io.h>
> > > >  #include <asm/pci.h>
> > > >  #include <asm/arch/gpio.h>
> > > > +#include <dm/acpi.h>
> > > >  #include <dt-bindings/gpio/x86-gpio.h>
> > > >
> > > >  static int intel_gpio_direction_input(struct udevice *dev, uint offset)
> > > > @@ -128,6 +130,35 @@ static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
> > > >         return 0;
> > > >  }
> > > >
> > > > +#if CONFIG_IS_ENABLED(ACPIGEN)
> > > > +static int intel_gpio_get_acpi(const struct gpio_desc *desc,
> > > > +                              struct acpi_gpio *gpio)
> > > > +{
> > > > +       struct udevice *pinctrl;
> > > > +       int ret;
> > > > +
> > > > +       if (!dm_gpio_is_valid(desc))
> > > > +               return -ENOENT;
> > > > +       pinctrl = dev_get_parent(desc->dev);
> > > > +
> > > > +       memset(gpio, '\0', sizeof(*gpio));
> > > > +
> > > > +       gpio->type = ACPI_GPIO_TYPE_IO;
> > > > +       gpio->pull = ACPI_GPIO_PULL_DEFAULT;
> > > > +       gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
> > > > +       gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
> > >
> > > Is there a way to figure out these properties from DT, instead of hardcoding?
> >
> > The answer is similar to your previous comment. But also, each pinctrl
> > driver has its own settings and limitations. If we want to support
> > different config for the pinctrl we would likely add it to the DT
> > binding for the pinctrl driver. So far I haven't seen a need but it
> > might happen with a future arch.
>
> Could gpio->pull and gpio->polarity be set depending on desc->flags?

To some extent, except that we don't have an equivalent to
ACPI_GPIO_PULL_DEFAULT.

>
> What is the reason for setting gpio->io_restrict to
> ACPI_GPIO_IO_RESTRICT_OUTPUT?

At present we only support outputs.

>
> > [..]
>
> regards, Wolfgang

Regards,
SImon