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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OS0PR01MB5922.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4f64c447-f721-4ff7-b39f-08da33d9434c X-MS-Exchange-CrossTenant-originalarrivaltime: 12 May 2022 05:35:45.5399 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4NsIP1rcZdTjafsblgqmL+6mA58x2KZItgY6D6qJNIsHNLEuwHhdHrmYoaCcZvZhgrcNHqywnNIgyU5Hvbw6TjNJDt4Wkc2fPazEs6MGw94= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYYPR01MB6779 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Prabhakar, Thanks for the patch. > Prabhakar Mahadev Lad > Subject: [PATCH v3 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain t= o > handle GPIO interrupt >=20 > Add IRQ domian to RZ/G2L pinctrl driver to handle GPIO interrupt. >=20 > GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be used = as > IRQ lines at given time. Selection of pins as IRQ lines is handled by IA5= 5 > (which is the IRQC block) which sits in between the GPIO and GIC. Do we need to update bindings with interrupt-cells on [1] like [2] as it ac= t as parent for GPIO interrupts? [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tre= e/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml?h=3D= next-20220511 [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tre= e/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml?h=3Dnext-20= 220511#n81 Cheers, Biju >=20 > Signed-off-by: Lad Prabhakar > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 202 ++++++++++++++++++++++++ > 1 file changed, 202 insertions(+) >=20 > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index a48cac55152c..af2c739cdbaa 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -9,8 +9,10 @@ > #include > #include > #include > +#include > #include > #include > +#include > #include #include > #include @@ -89,6 > +91,7 @@ > #define PIN(n) (0x0800 + 0x10 + (n)) > #define IOLH(n) (0x1000 + (n) * 8) > #define IEN(n) (0x1800 + (n) * 8) > +#define ISEL(n) (0x2c80 + (n) * 8) > #define PWPR (0x3014) > #define SD_CH(n) (0x3000 + (n) * 4) > #define QSPI (0x3008) > @@ -112,6 +115,10 @@ > #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + > 0x10) > #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) >=20 > +#define RZG2L_TINT_MAX_INTERRUPT 32 > +#define RZG2L_TINT_IRQ_START_INDEX 9 > +#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) > + > struct rzg2l_dedicated_configs { > const char *name; > u32 config; > @@ -137,6 +144,9 @@ struct rzg2l_pinctrl { >=20 > struct gpio_chip gpio_chip; > struct pinctrl_gpio_range gpio_range; > + DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); > + spinlock_t bitmap_lock; > + unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; >=20 > spinlock_t lock; > }; > @@ -883,6 +893,8 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, > unsigned int offset) >=20 > static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) > { > + unsigned int virq; > + > pinctrl_gpio_free(chip->base + offset); >=20 > /* > @@ -890,6 +902,10 @@ static void rzg2l_gpio_free(struct gpio_chip *chip, > unsigned int offset) > * drive the GPIO pin as an output. > */ > rzg2l_gpio_direction_input(chip, offset); > + > + virq =3D irq_find_mapping(chip->irq.domain, offset); > + if (virq) > + irq_dispose_mapping(virq); > } >=20 > static const char * const rzg2l_gpio_names[] =3D { @@ -1104,14 +1120,190= @@ > static struct { > } > }; >=20 > +static int rzg2l_gpio_get_gpioint(unsigned int virq) { > + unsigned int gpioint; > + unsigned int i; > + u32 port, bit; > + > + port =3D virq / 8; > + bit =3D virq % 8; > + > + if (port >=3D ARRAY_SIZE(rzg2l_gpio_configs) || > + bit >=3D RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) > + return -EINVAL; > + > + gpioint =3D bit; > + for (i =3D 0; i < port; i++) > + gpioint +=3D RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); > + > + return gpioint; > +} > + > +static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsign= ed > int virq, > + unsigned int nr_irqs) > +{ > + struct irq_data *d; > + > + d =3D irq_domain_get_irq_data(domain, virq); > + if (d) { > + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); > + struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct > rzg2l_pinctrl, gpio_chip); > + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); > + unsigned long flags; > + unsigned int i; > + > + for (i =3D 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { > + if (pctrl->hwirq[i] =3D=3D hwirq) { > + spin_lock_irqsave(&pctrl->bitmap_lock, flags); > + bitmap_release_region(pctrl->tint_slot, i, > get_order(1)); > + spin_unlock_irqrestore(&pctrl->bitmap_lock, > flags); > + pctrl->hwirq[i] =3D 0; > + break; > + } > + } > + } > + irq_domain_free_irqs_common(domain, virq, nr_irqs); } > + > +static void rzg2l_gpio_irq_disable(struct irq_data *d) { > + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); > + struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct rzg2l_pinctrl, > gpio_chip); > + unsigned int hwirq =3D irqd_to_hwirq(d); > + unsigned long flags; > + void __iomem *addr; > + u32 port; > + u8 bit; > + > + port =3D RZG2L_PIN_ID_TO_PORT(hwirq); > + bit =3D RZG2L_PIN_ID_TO_PIN(hwirq); > + > + addr =3D pctrl->base + ISEL(port); > + if (bit >=3D 4) { > + bit -=3D 4; > + addr +=3D 4; > + } > + > + spin_lock_irqsave(&pctrl->lock, flags); > + writel(readl(addr) & ~BIT(bit * 8), addr); > + spin_unlock_irqrestore(&pctrl->lock, flags); > + > + irq_chip_disable_parent(d); > +} > + > +static void rzg2l_gpio_irq_enable(struct irq_data *d) { > + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); > + struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct rzg2l_pinctrl, > gpio_chip); > + unsigned int hwirq =3D irqd_to_hwirq(d); > + unsigned long flags; > + void __iomem *addr; > + u32 port; > + u8 bit; > + > + port =3D RZG2L_PIN_ID_TO_PORT(hwirq); > + bit =3D RZG2L_PIN_ID_TO_PIN(hwirq); > + > + addr =3D pctrl->base + ISEL(port); > + if (bit >=3D 4) { > + bit -=3D 4; > + addr +=3D 4; > + } > + > + spin_lock_irqsave(&pctrl->lock, flags); > + writel(readl(addr) | BIT(bit * 8), addr); > + spin_unlock_irqrestore(&pctrl->lock, flags); > + > + irq_chip_enable_parent(d); > +} > + > +static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int > +type) { > + return irq_chip_set_type_parent(d, type); } > + > +static void rzg2l_gpio_irqc_eoi(struct irq_data *d) { > + irq_chip_eoi_parent(d); > +} > + > +static struct irq_chip rzg2l_gpio_irqchip =3D { > + .name =3D "rzg2l-gpio", > + .irq_disable =3D rzg2l_gpio_irq_disable, > + .irq_enable =3D rzg2l_gpio_irq_enable, > + .irq_mask =3D irq_chip_mask_parent, > + .irq_unmask =3D irq_chip_unmask_parent, > + .irq_set_type =3D rzg2l_gpio_irq_set_type, > + .irq_eoi =3D rzg2l_gpio_irqc_eoi, > +}; > + > +static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, > + unsigned int child, > + unsigned int child_type, > + unsigned int *parent, > + unsigned int *parent_type) > +{ > + struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(gc); > + unsigned long flags; > + int gpioint, irq; > + > + gpioint =3D rzg2l_gpio_get_gpioint(child); > + if (gpioint < 0) > + return gpioint; > + > + spin_lock_irqsave(&pctrl->bitmap_lock, flags); > + irq =3D bitmap_find_free_region(pctrl->tint_slot, > RZG2L_TINT_MAX_INTERRUPT, get_order(1)); > + spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); > + if (irq < 0) > + return -ENOSPC; > + pctrl->hwirq[irq] =3D child; > + irq +=3D RZG2L_TINT_IRQ_START_INDEX; > + > + /* All these interrupts are level high in the CPU */ > + *parent_type =3D IRQ_TYPE_LEVEL_HIGH; > + *parent =3D RZG2L_PACK_HWIRQ(gpioint, irq); > + return 0; > +} > + > +static void *rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, > + unsigned int parent_hwirq, > + unsigned int parent_type) > +{ > + struct irq_fwspec *fwspec; > + > + fwspec =3D kzalloc(sizeof(*fwspec), GFP_KERNEL); > + if (!fwspec) > + return NULL; > + > + fwspec->fwnode =3D chip->irq.parent_domain->fwnode; > + fwspec->param_count =3D 2; > + fwspec->param[0] =3D parent_hwirq; > + fwspec->param[1] =3D parent_type; > + > + return fwspec; > +} > + > static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) { > struct device_node *np =3D pctrl->dev->of_node; > struct gpio_chip *chip =3D &pctrl->gpio_chip; > const char *name =3D dev_name(pctrl->dev); > + struct irq_domain *parent_domain; > struct of_phandle_args of_args; > + struct device_node *parent_np; > + struct gpio_irq_chip *girq; > int ret; >=20 > + parent_np =3D of_irq_find_parent(np); > + if (!parent_np) > + return -ENXIO; > + > + parent_domain =3D irq_find_host(parent_np); > + of_node_put(parent_np); > + if (!parent_domain) > + return -EPROBE_DEFER; > + > ret =3D of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, > &of_args); > if (ret) { > dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); @@ - > 1138,6 +1330,15 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl > *pctrl) > chip->base =3D -1; > chip->ngpio =3D of_args.args[2]; >=20 > + girq =3D &chip->irq; > + girq->chip =3D &rzg2l_gpio_irqchip; > + girq->fwnode =3D of_node_to_fwnode(np); > + girq->parent_domain =3D parent_domain; > + girq->child_to_parent_hwirq =3D rzg2l_gpio_child_to_parent_hwirq; > + girq->populate_parent_alloc_arg =3D rzg2l_gpio_populate_parent_fwspec; > + girq->child_irq_domain_ops.free =3D rzg2l_gpio_irq_domain_free; > + girq->ngirq =3D RZG2L_TINT_MAX_INTERRUPT; > + > pctrl->gpio_range.id =3D 0; > pctrl->gpio_range.pin_base =3D 0; > pctrl->gpio_range.base =3D 0; > @@ -1253,6 +1454,7 @@ static int rzg2l_pinctrl_probe(struct platform_devi= ce > *pdev) > } >=20 > spin_lock_init(&pctrl->lock); > + spin_lock_init(&pctrl->bitmap_lock); >=20 > platform_set_drvdata(pdev, pctrl); >=20 > -- > 2.25.1