RE: [PATCH v7 2/2] pwm: Add support for RZ/G2L GPT

[Biju Das <biju.das.jz@bp.renesas.com>]

Hi Geert,

> Subject: Re: [PATCH v7 2/2] pwm: Add support for RZ/G2L GPT
> 
> Hi Biju,
> 
> On Wed, Sep 28, 2022 at 7:34 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > On Wed, Sep 21, 2022 at 03:57:41PM +0100, Biju Das wrote:
> > > > RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-
> bit
> > > > timer (GPT32E). It supports the following functions
> > > >  * 32 bits × 8 channels
> > > >  * Up-counting or down-counting (saw waves) or up/down-counting
> > > >    (triangle waves) for each counter.
> > > >  * Clock sources independently selectable for each channel
> > > >  * Two I/O pins per channel
> > > >  * Two output compare/input capture registers per channel
> > > >  * For the two output compare/input capture registers of each
> > > channel,
> > > >    four registers are provided as buffer registers and are
> capable
> > > of
> > > >    operating as comparison registers when buffering is not in
> use.
> > > >  * In output compare operation, buffer switching can be at
> crests or
> > > >    troughs, enabling the generation of laterally asymmetric PWM
> > > waveforms.
> > > >  * Registers for setting up frame cycles in each channel (with
> > > capability
> > > >    for generating interrupts at overflow or underflow)
> > > >  * Generation of dead times in PWM operation
> > > >  * Synchronous starting, stopping and clearing counters for
> > > arbitrary
> > > >    channels
> > > >  * Starting, stopping, clearing and up/down counters in response
> > > > to
> > > input
> > > >    level comparison
> > > >  * Starting, clearing, stopping and up/down counters in response
> > > > to
> > > a
> > > >    maximum of four external triggers
> > > >  * Output pin disable function by dead time error and detected
> > > >    short-circuits between output pins
> > > >  * A/D converter start triggers can be generated (GPT32E0 to
> > > GPT32E3)
> > > >  * Enables the noise filter for input capture and external
> trigger
> > > >    operation
> > > >
> > > > This patch adds basic pwm support for RZ/G2L GPT driver by
> > > > creating separate logical channels for each IOs.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> > > > --- /dev/null
> > > > +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> > > > +   if (rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR) & RZG2L_GTCR_CST)
> > > > +           rzg2l_gpt->pwm_enabled_by_bootloader = true;
> > > > +   else
> > > > +           devm_clk_put(&pdev->dev, rzg2l_gpt->clk);
> > >
> > > So in either case I would expect you to want to hold on to the
> clock
> > > pointer here and use that in the runtime PM callbacks.
> >
> > But the api used here is "devm_clk_get_enabled".
> > This will enable the clocks and holds the reference (for pwm enabled
> > by bootloader case) as it avoids turning "off"
> > the clock during later part of the boot process (it prevents clock
> off
> > by clk_disable_unused())
> 
> The clock will still be stopped if the driver is unloaded, or if the
> device is unbound manually, right? Or am I missing something?

Yes, it is turned off during unloading.

root@smarc-rzg2l:~# devmem2 0x11010540
/dev/mem opened.
Memory mapped at address 0xffff81d93000.
Read at address  0x11010540 (0xffff81d93540): 0x00000001
root@smarc-rzg2l:~# lsmod
Module                  Size  Used by
rzg2l_mtu3_cnt         16384  0
counter                28672  1 rzg2l_mtu3_cnt
crct10dif_ce           20480  1
snd_soc_simple_card    20480  0
snd_soc_simple_card_utils    24576  1 snd_soc_simple_card
panfrost               69632  0
drm_shmem_helper       28672  1 panfrost
renesas_usbhs          65536  0
gpu_sched              40960  1 panfrost
drm                   561152  4 gpu_sched,drm_shmem_helper,panfrost
rcar_canfd             36864  0
renesas_rpc_if         20480  0
snd_soc_wm8978         45056  1
snd_soc_rz_ssi         24576  1
rzg2l_adc              24576  0
can_dev                40960  1 rcar_canfd
rzg2l_poeg             20480  0
rzg2l_mtu3             16384  1 rzg2l_mtu3_cnt
pwm_rzg2l_gpt          16384  1 rzg2l_poeg
ipv6                  458752  18
root@smarc-rzg2l:~# rmmod rzg2l_poeg
root@smarc-rzg2l:~# rmmod pwm_rzg2l_gpt
root@smarc-rzg2l:~# devmem2 0x11010540
/dev/mem opened.
Memory mapped at address 0xffffa6e6d000.
Read at address  0x11010540 (0xffffa6e6d540): 0x00000000

Cheers,
Biju