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Tue, 12 Jan 2021 10:34:10 +0000 Received: from OSBPR01MB4582.jpnprd01.prod.outlook.com ([fe80::3d2f:3902:f15b:b01f]) by OSBPR01MB4582.jpnprd01.prod.outlook.com ([fe80::3d2f:3902:f15b:b01f%5]) with mapi id 15.20.3742.012; Tue, 12 Jan 2021 10:34:10 +0000 From: "misono.tomohiro@fujitsu.com" To: 'Mark Rutland' List-Id: CC: "linux-arm-kernel@lists.infradead.org" , "soc@kernel.org" , "olof@lixom.net" , "catalin.marinas@arm.com" , "will@kernel.org" , "arnd@arndb.de" Subject: RE: [RFC PATCH 00/10] Add Fujitsu A64FX soc entry/hardware barrier driver Thread-Topic: [RFC PATCH 00/10] Add Fujitsu A64FX soc entry/hardware barrier driver Thread-Index: AQHW5aq63O/w5e6x+kOClsfWvFvpM6odr2EAgAYVV2A= Date: Tue, 12 Jan 2021 10:32:53 +0000 Deferred-Delivery: Tue, 12 Jan 2021 10:33:53 +0000 Message-ID: References: <20210108105241.1757799-1-misono.tomohiro@jp.fujitsu.com> <20210108125410.GA84941@C02TD0UTHF1T.local> In-Reply-To: <20210108125410.GA84941@C02TD0UTHF1T.local> Accept-Language: ja-JP, en-US Content-Language: ja-JP X-MS-Has-Attach: X-MS-TNEF-Correlator: x-shieldmailcheckermailid: 9333fa91eaa64170bd7e6644cc66241e x-securitypolicycheck: OK by SHieldMailChecker v2.6.3 authentication-results: arm.com; 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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: fujitsu.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OSBPR01MB4582.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f9fe578-40a3-4eba-2b21-08d8b6e598dd X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Jan 2021 10:34:10.0083 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a19f121d-81e1-4858-a9d8-736e267fd4c7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JriwseaBnMCSD3vBxRQH2JoKn8k6QrbfvOR/fUT0NILyzGSDoT1lLdWFp07U3GmkyphuS4qSiqrRm+5ZRYcy/PXgdvDSGzckLngJ4jNUydU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSAPR01MB4692 > On Fri, Jan 08, 2021 at 07:52:31PM +0900, Misono Tomohiro wrote: > > (Resend as cover letter title was missing in the first time. Sorry for = noise) > > > > Hello, >=20 > Hi, >=20 > > This series adds Fujitsu A64FX SoC entry in drivers/soc and hardware > > barrier driver for it. > > > > [Driver Description] > > A64FX CPU has several functions for HPC workload and hardware barrier > > is one of them. It is a mechanism to realize fast synchronization by > > PEs belonging to the same L3 cache domain by using implementation > > defined hardware registers. > > For more details, see A64FX HPC extension specification in > > https://github.com/fujitsu/A64FX > > > > The driver mainly offers a set of ioctls to manipulate related registe= rs. > > Patch 1-9 implements driver code and patch 10 finally adds kconfig, > > Makefile and MAINTAINER entry for the driver. >=20 > I have a number of concerns here, and at a high level, I do not think > that this is something Linux can reasonably support in its current form. > Sorry if this comes across as harsh; I appreciate the work that has gone > into this, and the effort to try to upstream support is great -- my > concerns are with the overal picture. >=20 > As a general rule, we avoid the use of IMPLEMENTATION DEFINED features > in Linux, as they pose a number of correctness/safety challenges and > come with a potentially significan long term maintenance burden that is > generally not justified by the features themselves. For example, such > features are not usable under virtualization (where a hypervisor may set > HCR_EL2.TIDCP, or fail to context-switch state that it is unaware of). >=20 > Secondly, the intended usage model appears to expose this to EL0 for > direct access, and the code seems to depend on threads being pinned, but > AFAICT this is not enforced and there is no provision for > context-switch, thread migration, or interaction with ptrace. I fear > this is going to be very fragile in practice, and that extending that > support in future will require much more complexity than is currently > apparent, with potentially invasive changes to arch code. >=20 > Thirdly, this requires userspace software to be intimately familiar with > the HW platform that it is running on (both in terms of using IMP-DEF > instructions and needing to know the physical layout), rather than being > generic and portable, which I don't believe is something that we wish to > encourage. I also think this is unlikely to be supported by generic > software because of the lack of portability, and consequently I struggle > to beleive that this will see significant usage. >=20 > Further, as an IMP-DEF feature, it's not clear how much of this will > carry forward into future designs, and where things may change. It's > extremely difficult to determine whether any of the ABI decisions (e.g. > the sysfs layout) are sufficient, or what level of changes would be > necessary in userspace code if there are physical topology changes or > changes to the strucutre of the system register interfaces. >=20 > Overall, I think this needs much more justification in terms of > practical usage, safety/correctness, and long term maintenance, and with > that I think the longer term goal would be to use this to justify an > architectural feature along similar lines rather than to support any > IMPLEMENTATION DEFINED variants upstream in Linux. >=20 > > Also, C library and test program for this driver is available on: > > https://github.com/fujitsu/hardware_barrier >=20 > Hmm... I see some code in that repo which looks suspiciously like code > from the Linux kernel tree, but licensed differently, which is > concerning. >=20 > Specifically, the asm block in internal.h (which the SPDX headers says > is licensed as LGPL-3.0-only) looks like a copy of code from > arch/arm64/include/asm/sysreg.h (which is licensed as GPL-2.0-only per > its SPDX header). >=20 > If that code was copied, I don't believe that relicensing is permitted. > I would advise that someone with legal training considers the provenance > of that code and what is permitted. Sorry, I must have lacked the attention where the code comes from when I wr= ote the code. I have removed that part to write assemby directly: https://github.com/fujitsu/hardware_barrier/blob/develop/src/internal.h https://github.com/fujitsu/hardware_barrier/blob/develop/src/hwblib.c#L215 Regards, Tomohiro From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E898C433DB for ; Tue, 12 Jan 2021 10:36:23 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2BD4F222B3 for ; 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Tue, 12 Jan 2021 10:34:10 +0000 From: "misono.tomohiro@fujitsu.com" To: 'Mark Rutland' Subject: RE: [RFC PATCH 00/10] Add Fujitsu A64FX soc entry/hardware barrier driver Thread-Topic: [RFC PATCH 00/10] Add Fujitsu A64FX soc entry/hardware barrier driver Thread-Index: AQHW5aq63O/w5e6x+kOClsfWvFvpM6odr2EAgAYVV2A= Date: Tue, 12 Jan 2021 10:32:53 +0000 Deferred-Delivery: Tue, 12 Jan 2021 10:33:53 +0000 Message-ID: References: <20210108105241.1757799-1-misono.tomohiro@jp.fujitsu.com> <20210108125410.GA84941@C02TD0UTHF1T.local> In-Reply-To: <20210108125410.GA84941@C02TD0UTHF1T.local> Accept-Language: ja-JP, en-US Content-Language: ja-JP X-MS-Has-Attach: X-MS-TNEF-Correlator: x-shieldmailcheckermailid: 9333fa91eaa64170bd7e6644cc66241e x-securitypolicycheck: OK by SHieldMailChecker v2.6.3 authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=fujitsu.com; x-originating-ip: [218.44.52.179] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2f9fe578-40a3-4eba-2b21-08d8b6e598dd x-ms-traffictypediagnostic: OSAPR01MB4692: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Message-ID: <20210112103253.ax_d0Qb_Z2mVI6Gz4EdtpWWcoQt2mGZT1SlwutlZXWQ@z> > On Fri, Jan 08, 2021 at 07:52:31PM +0900, Misono Tomohiro wrote: > > (Resend as cover letter title was missing in the first time. Sorry for noise) > > > > Hello, > > Hi, > > > This series adds Fujitsu A64FX SoC entry in drivers/soc and hardware > > barrier driver for it. > > > > [Driver Description] > > A64FX CPU has several functions for HPC workload and hardware barrier > > is one of them. It is a mechanism to realize fast synchronization by > > PEs belonging to the same L3 cache domain by using implementation > > defined hardware registers. > > For more details, see A64FX HPC extension specification in > > https://github.com/fujitsu/A64FX > > > > The driver mainly offers a set of ioctls to manipulate related registers. > > Patch 1-9 implements driver code and patch 10 finally adds kconfig, > > Makefile and MAINTAINER entry for the driver. > > I have a number of concerns here, and at a high level, I do not think > that this is something Linux can reasonably support in its current form. > Sorry if this comes across as harsh; I appreciate the work that has gone > into this, and the effort to try to upstream support is great -- my > concerns are with the overal picture. > > As a general rule, we avoid the use of IMPLEMENTATION DEFINED features > in Linux, as they pose a number of correctness/safety challenges and > come with a potentially significan long term maintenance burden that is > generally not justified by the features themselves. For example, such > features are not usable under virtualization (where a hypervisor may set > HCR_EL2.TIDCP, or fail to context-switch state that it is unaware of). > > Secondly, the intended usage model appears to expose this to EL0 for > direct access, and the code seems to depend on threads being pinned, but > AFAICT this is not enforced and there is no provision for > context-switch, thread migration, or interaction with ptrace. I fear > this is going to be very fragile in practice, and that extending that > support in future will require much more complexity than is currently > apparent, with potentially invasive changes to arch code. > > Thirdly, this requires userspace software to be intimately familiar with > the HW platform that it is running on (both in terms of using IMP-DEF > instructions and needing to know the physical layout), rather than being > generic and portable, which I don't believe is something that we wish to > encourage. I also think this is unlikely to be supported by generic > software because of the lack of portability, and consequently I struggle > to beleive that this will see significant usage. > > Further, as an IMP-DEF feature, it's not clear how much of this will > carry forward into future designs, and where things may change. It's > extremely difficult to determine whether any of the ABI decisions (e.g. > the sysfs layout) are sufficient, or what level of changes would be > necessary in userspace code if there are physical topology changes or > changes to the strucutre of the system register interfaces. > > Overall, I think this needs much more justification in terms of > practical usage, safety/correctness, and long term maintenance, and with > that I think the longer term goal would be to use this to justify an > architectural feature along similar lines rather than to support any > IMPLEMENTATION DEFINED variants upstream in Linux. > > > Also, C library and test program for this driver is available on: > > https://github.com/fujitsu/hardware_barrier > > Hmm... I see some code in that repo which looks suspiciously like code > from the Linux kernel tree, but licensed differently, which is > concerning. > > Specifically, the asm block in internal.h (which the SPDX headers says > is licensed as LGPL-3.0-only) looks like a copy of code from > arch/arm64/include/asm/sysreg.h (which is licensed as GPL-2.0-only per > its SPDX header). > > If that code was copied, I don't believe that relicensing is permitted. > I would advise that someone with legal training considers the provenance > of that code and what is permitted. Sorry, I must have lacked the attention where the code comes from when I wrote the code. I have removed that part to write assemby directly: https://github.com/fujitsu/hardware_barrier/blob/develop/src/internal.h https://github.com/fujitsu/hardware_barrier/blob/develop/src/hwblib.c#L215 Regards, Tomohiro _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel