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Tue, 1 Jun 2021 06:56:33 +0000 From: Nava kishore Manne To: Greg KH CC: "robh+dt@kernel.org" , Michal Simek , "mdf@kernel.org" , "trix@redhat.com" , "arnd@arndb.de" , Rajan Vaja , Amit Sunil Dhamne , Tejas Patel , "zou_wei@huawei.com" , Sai Krishna Potthuri , Ravi Patel , "iwamatsu@nigauri.org" , Jiaying Liang , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-fpga@vger.kernel.org" , git , "chinnikishore369@gmail.com" , Appana Durga Kedareswara Rao Subject: RE: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver Thread-Topic: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver Thread-Index: AQHXTU+iaNo/Lx6wC0mUnqfp+5BQFarsD00AgBK10GA= Date: Tue, 1 Jun 2021 06:56:32 +0000 Message-ID: References: <20210520080954.1393-1-nava.manne@xilinx.com> <20210520080954.1393-5-nava.manne@xilinx.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: linuxfoundation.org; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR02MB7336.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cd1df2c3-007c-422c-3aff-08d924ca6417 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Jun 2021 06:56:32.8255 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SrWJBXGjUP8eTS14rugwaDCF0beEfoNfjRhmG05meMzjUyC/YfhDRH5yyXovByoZHendN2vnyA1G/sgJ8Cb/VQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR02MB7304 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Greg, Thanks for providing the review comments. Please find my response inline. > -----Original Message----- > From: Greg KH > Sent: Thursday, May 20, 2021 2:19 PM > To: Nava kishore Manne > Cc: robh+dt@kernel.org; Michal Simek ; > mdf@kernel.org; trix@redhat.com; arnd@arndb.de; Rajan Vaja > ; Amit Sunil Dhamne ; > Tejas Patel ; zou_wei@huawei.com; Sai Krishna > Potthuri ; Ravi Patel ; > iwamatsu@nigauri.org; Jiaying Liang ; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; linux-fpga@vger.kernel.org; git ; > chinnikishore369@gmail.com; Appana Durga Kedareswara Rao > > Subject: Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager dr= iver >=20 > On Thu, May 20, 2021 at 01:39:54PM +0530, Nava kishore Manne wrote: > > Add support for Xilinx Versal FPGA manager. > > > > PDI source type can be DDR, OCM, QSPI flash etc.. > > But driver allocates memory always from DDR, Since driver supports > > only DDR source type. > > > > Signed-off-by: Appana Durga Kedareswara rao > > > > Signed-off-by: Nava kishore Manne > > Reviewed-by: Moritz Fischer > > --- > > Changes for v2: > > -Updated the Fpga Mgr registrations call's > > to 5.11 > > -Fixed some minor coding issues as suggested by > > Moritz. > > Changes for v3: > > -Rewritten the Versal fpga Kconfig contents. > > Changes for v4: > > -Rebased the changes on linux-next. > > No functional changes. > > Changes for v5: > > -None. > > Changes for v6: > > -None. > > > > drivers/fpga/Kconfig | 9 +++ > > drivers/fpga/Makefile | 1 + > > drivers/fpga/versal-fpga.c | 117 > > +++++++++++++++++++++++++++++++++++++ > > 3 files changed, 127 insertions(+) > > create mode 100644 drivers/fpga/versal-fpga.c > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > 33e15058d0dc..92c20b92357a 100644 > > --- a/drivers/fpga/Kconfig > > +++ b/drivers/fpga/Kconfig > > @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA > > to configure the programmable logic(PL) through PS > > on ZynqMP SoC. > > > > +config FPGA_MGR_VERSAL_FPGA > > + tristate "Xilinx Versal FPGA" > > + depends on ARCH_ZYNQMP || COMPILE_TEST > > + help > > + Select this option to enable FPGA manager driver support for > > + Xilinx Versal SoC. This driver uses the firmware interface to > > + configure the programmable logic(PL). > > + > > + To compile this as a module, choose M here. > > endif # FPGA > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > 18dc9885883a..0bff783d1b61 100644 > > --- a/drivers/fpga/Makefile > > +++ b/drivers/fpga/Makefile > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) +=3D > ts73xx-fpga.o > > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) +=3D xilinx-spi.o > > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) +=3D zynq-fpga.o > > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) +=3D zynqmp-fpga.o > > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) +=3D versal-fpga.o > > obj-$(CONFIG_ALTERA_PR_IP_CORE) +=3D altera-pr-ip-core.o > > obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) +=3D altera-pr-ip-core-plat.o > > > > diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c > > new file mode 100644 index 000000000000..5744e44f981d > > --- /dev/null > > +++ b/drivers/fpga/versal-fpga.c > > @@ -0,0 +1,117 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2019-2021 Xilinx, Inc. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/** > > + * struct versal_fpga_priv - Private data structure > > + * @dev: Device data structure > > + */ > > +struct versal_fpga_priv { > > + struct device *dev; > > +}; >=20 > Don't you have this pointer already? What device is this exactly and why > does it differ from the structure it currently lives in? >=20 Agree, this struct is not needed. Will fix this issue in v7. > > + > > +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, > > + struct fpga_image_info *info, > > + const char *buf, size_t size) { > > + return 0; > > +} >=20 > If you don't need this, why include it? >=20 Agree this empty API is not needed. It's a limitation with the framework and this needs to fixed in the fpga_ma= nager core. Will address this generic issue in a different series. =20 > > + > > +static int versal_fpga_ops_write(struct fpga_manager *mgr, > > + const char *buf, size_t size) > > +{ > > + struct versal_fpga_priv *priv; > > + dma_addr_t dma_addr =3D 0; > > + char *kbuf; > > + int ret; > > + > > + priv =3D mgr->priv; > > + > > + kbuf =3D dma_alloc_coherent(priv->dev, size, &dma_addr, > GFP_KERNEL); > > + if (!kbuf) > > + return -ENOMEM; > > + > > + memcpy(kbuf, buf, size); > > + > > + wmb(); /* ensure all writes are done before initiate FW call */ >=20 > What "writes"? The memcpy above? Are you _SURE_ that really is correct > here? This feels wrong. >=20 Will fix in v7. > > + > > + ret =3D zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr); >=20 > If this needs some sort of barrier, shouldn't it be in this call? >=20 Will fix in v7. > > + > > + dma_free_coherent(priv->dev, size, kbuf, dma_addr); > > + > > + return ret; > > +} > > + > > +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr, > > + struct fpga_image_info *info) > > +{ > > + return 0; > > +} >=20 > Again, why have it if it does nothing? >=20 Same as above. > > + > > +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager > > +*mgr) { > > + return FPGA_MGR_STATE_UNKNOWN; > > +} >=20 > Again, is this needed? If so, then the fpga_manager core needs to be fix= ed > up :) > Same as above. > > +static const struct fpga_manager_ops versal_fpga_ops =3D { > > + .state =3D versal_fpga_ops_state, > > + .write_init =3D versal_fpga_ops_write_init, > > + .write =3D versal_fpga_ops_write, > > + .write_complete =3D versal_fpga_ops_write_complete, }; > > + > > +static int versal_fpga_probe(struct platform_device *pdev) { > > + struct device *dev =3D &pdev->dev; > > + struct versal_fpga_priv *priv; > > + struct fpga_manager *mgr; > > + int ret; > > + > > + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > > + if (!priv) > > + return -ENOMEM; > > + > > + priv->dev =3D dev; >=20 > You save a pointer to a reference counted structure, without incrementing > the reference count. What could go wrong? :) >=20 > You are getting lucky here, but as stated above, why do you need this > pointer? >=20 Will fix in v7. Regards, Navakishore. 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Tue, 1 Jun 2021 06:56:33 +0000 From: Nava kishore Manne To: Greg KH CC: "robh+dt@kernel.org" , Michal Simek , "mdf@kernel.org" , "trix@redhat.com" , "arnd@arndb.de" , Rajan Vaja , Amit Sunil Dhamne , Tejas Patel , "zou_wei@huawei.com" , Sai Krishna Potthuri , Ravi Patel , "iwamatsu@nigauri.org" , Jiaying Liang , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-fpga@vger.kernel.org" , git , "chinnikishore369@gmail.com" , Appana Durga Kedareswara Rao Subject: RE: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver Thread-Topic: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver Thread-Index: AQHXTU+iaNo/Lx6wC0mUnqfp+5BQFarsD00AgBK10GA= Date: Tue, 1 Jun 2021 06:56:32 +0000 Message-ID: References: <20210520080954.1393-1-nava.manne@xilinx.com> <20210520080954.1393-5-nava.manne@xilinx.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: linuxfoundation.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Greg, Thanks for providing the review comments. Please find my response inline. > -----Original Message----- > From: Greg KH > Sent: Thursday, May 20, 2021 2:19 PM > To: Nava kishore Manne > Cc: robh+dt@kernel.org; Michal Simek ; > mdf@kernel.org; trix@redhat.com; arnd@arndb.de; Rajan Vaja > ; Amit Sunil Dhamne ; > Tejas Patel ; zou_wei@huawei.com; Sai Krishna > Potthuri ; Ravi Patel ; > iwamatsu@nigauri.org; Jiaying Liang ; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; linux-fpga@vger.kernel.org; git ; > chinnikishore369@gmail.com; Appana Durga Kedareswara Rao > > Subject: Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver > > On Thu, May 20, 2021 at 01:39:54PM +0530, Nava kishore Manne wrote: > > Add support for Xilinx Versal FPGA manager. > > > > PDI source type can be DDR, OCM, QSPI flash etc.. > > But driver allocates memory always from DDR, Since driver supports > > only DDR source type. > > > > Signed-off-by: Appana Durga Kedareswara rao > > > > Signed-off-by: Nava kishore Manne > > Reviewed-by: Moritz Fischer > > --- > > Changes for v2: > > -Updated the Fpga Mgr registrations call's > > to 5.11 > > -Fixed some minor coding issues as suggested by > > Moritz. > > Changes for v3: > > -Rewritten the Versal fpga Kconfig contents. > > Changes for v4: > > -Rebased the changes on linux-next. > > No functional changes. > > Changes for v5: > > -None. > > Changes for v6: > > -None. > > > > drivers/fpga/Kconfig | 9 +++ > > drivers/fpga/Makefile | 1 + > > drivers/fpga/versal-fpga.c | 117 > > +++++++++++++++++++++++++++++++++++++ > > 3 files changed, 127 insertions(+) > > create mode 100644 drivers/fpga/versal-fpga.c > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > 33e15058d0dc..92c20b92357a 100644 > > --- a/drivers/fpga/Kconfig > > +++ b/drivers/fpga/Kconfig > > @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA > > to configure the programmable logic(PL) through PS > > on ZynqMP SoC. > > > > +config FPGA_MGR_VERSAL_FPGA > > + tristate "Xilinx Versal FPGA" > > + depends on ARCH_ZYNQMP || COMPILE_TEST > > + help > > + Select this option to enable FPGA manager driver support for > > + Xilinx Versal SoC. This driver uses the firmware interface to > > + configure the programmable logic(PL). > > + > > + To compile this as a module, choose M here. > > endif # FPGA > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > 18dc9885883a..0bff783d1b61 100644 > > --- a/drivers/fpga/Makefile > > +++ b/drivers/fpga/Makefile > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += > ts73xx-fpga.o > > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > > obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o > > obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o > > > > diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c > > new file mode 100644 index 000000000000..5744e44f981d > > --- /dev/null > > +++ b/drivers/fpga/versal-fpga.c > > @@ -0,0 +1,117 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2019-2021 Xilinx, Inc. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/** > > + * struct versal_fpga_priv - Private data structure > > + * @dev: Device data structure > > + */ > > +struct versal_fpga_priv { > > + struct device *dev; > > +}; > > Don't you have this pointer already? What device is this exactly and why > does it differ from the structure it currently lives in? > Agree, this struct is not needed. Will fix this issue in v7. > > + > > +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, > > + struct fpga_image_info *info, > > + const char *buf, size_t size) { > > + return 0; > > +} > > If you don't need this, why include it? > Agree this empty API is not needed. It's a limitation with the framework and this needs to fixed in the fpga_manager core. Will address this generic issue in a different series. > > + > > +static int versal_fpga_ops_write(struct fpga_manager *mgr, > > + const char *buf, size_t size) > > +{ > > + struct versal_fpga_priv *priv; > > + dma_addr_t dma_addr = 0; > > + char *kbuf; > > + int ret; > > + > > + priv = mgr->priv; > > + > > + kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, > GFP_KERNEL); > > + if (!kbuf) > > + return -ENOMEM; > > + > > + memcpy(kbuf, buf, size); > > + > > + wmb(); /* ensure all writes are done before initiate FW call */ > > What "writes"? The memcpy above? Are you _SURE_ that really is correct > here? This feels wrong. > Will fix in v7. > > + > > + ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr); > > If this needs some sort of barrier, shouldn't it be in this call? > Will fix in v7. > > + > > + dma_free_coherent(priv->dev, size, kbuf, dma_addr); > > + > > + return ret; > > +} > > + > > +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr, > > + struct fpga_image_info *info) > > +{ > > + return 0; > > +} > > Again, why have it if it does nothing? > Same as above. > > + > > +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager > > +*mgr) { > > + return FPGA_MGR_STATE_UNKNOWN; > > +} > > Again, is this needed? If so, then the fpga_manager core needs to be fixed > up :) > Same as above. > > +static const struct fpga_manager_ops versal_fpga_ops = { > > + .state = versal_fpga_ops_state, > > + .write_init = versal_fpga_ops_write_init, > > + .write = versal_fpga_ops_write, > > + .write_complete = versal_fpga_ops_write_complete, }; > > + > > +static int versal_fpga_probe(struct platform_device *pdev) { > > + struct device *dev = &pdev->dev; > > + struct versal_fpga_priv *priv; > > + struct fpga_manager *mgr; > > + int ret; > > + > > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > > + if (!priv) > > + return -ENOMEM; > > + > > + priv->dev = dev; > > You save a pointer to a reference counted structure, without incrementing > the reference count. What could go wrong? :) > > You are getting lucky here, but as stated above, why do you need this > pointer? > Will fix in v7. Regards, Navakishore. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel