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Wed, 7 Jul 2021 11:54:57 +0000 From: "Thokala, Srikanth" To: Lorenzo Pieralisi , "maz@kernel.org" CC: "robh+dt@kernel.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "andriy.shevchenko@linux.intel.com" , "mgross@linux.intel.com" , "Raja Subramanian, Lakshmi Bai" , "Sangannavar, Mallikarjunappa" , "kw@linux.com" Subject: RE: [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem Bay Thread-Topic: [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem Bay Thread-Index: AQHXW3FV4CKL56K+SEOKbFusTp+FKasexPQAgASQnFCAEpouoA== Date: Wed, 7 Jul 2021 11:54:57 +0000 Message-ID: References: <20210607154044.26074-1-srikanth.thokala@intel.com> <20210607154044.26074-3-srikanth.thokala@intel.com> <20210621162506.GA31511@lpieralisi> In-Reply-To: Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5595.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 842bcef7-2511-4f34-d569-08d9413e0afd X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Jul 2021 11:54:57.6656 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vgxVy8dy4enUKkZdDvQibke6duehQjr40XYO5aeDK+BEuj2QY7ahpD6zYpys0wixMa+FeVR+NIrCll48A98VI/DhZG+DM1Dey62LiRFT+LU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB5577 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Lorenzo and Marc, > -----Original Message----- > From: Thokala, Srikanth > Sent: Friday, June 25, 2021 8:54 AM > To: Lorenzo Pieralisi ; maz@kernel.org > Cc: robh+dt@kernel.org; linux-pci@vger.kernel.org; > devicetree@vger.kernel.org; andriy.shevchenko@linux.intel.com; > mgross@linux.intel.com; Raja Subramanian, Lakshmi Bai > ; Sangannavar, Mallikarjunappa > ; kw@linux.com > Subject: RE: [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem > Bay >=20 > Hi Lorenzo, >=20 > > -----Original Message----- > > From: Lorenzo Pieralisi > > Sent: Monday, June 21, 2021 10:23 PM > > To: Thokala, Srikanth ; maz@kernel.org > > Cc: robh+dt@kernel.org; linux-pci@vger.kernel.org; > > devicetree@vger.kernel.org; andriy.shevchenko@linux.intel.com; > > mgross@linux.intel.com; Raja Subramanian, Lakshmi Bai > > ; Sangannavar, > Mallikarjunappa > > ; kw@linux.com > > Subject: Re: [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem > Bay > > > > [+Marc] > > > > On Mon, Jun 07, 2021 at 09:10:44PM +0530, srikanth.thokala@intel.com > > wrote: > > [...] > > > > > +static void keembay_pcie_msi_irq_handler(struct irq_desc *desc) > > > +{ > > > + struct keembay_pcie *pcie =3D irq_desc_get_handler_data(desc); > > > + struct irq_chip *chip =3D irq_desc_get_chip(desc); > > > + u32 val, mask, status; > > > + struct pcie_port *pp; > > > + > > > + chained_irq_enter(chip, desc); > > > + > > > + pp =3D &pcie->pci.pp; > > > + val =3D readl(pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS); > > > + mask =3D readl(pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); > > > + > > > + status =3D val & mask; > > > + > > > + if (status & MSI_CTRL_INT) { > > > + dw_handle_msi_irq(pp); > > > + writel(status, pcie->apb_base + > PCIE_REGS_INTERRUPT_STATUS); > > > + } > > > + > > > + chained_irq_exit(chip, desc); > > > +} > > > + > > > +static int keembay_pcie_setup_msi_irq(struct keembay_pcie *pcie) > > > +{ > > > + struct dw_pcie *pci =3D &pcie->pci; > > > + struct device *dev =3D pci->dev; > > > + struct platform_device *pdev =3D to_platform_device(dev); > > > + int irq; > > > + > > > + irq =3D platform_get_irq_byname(pdev, "pcie"); > > > + if (irq < 0) > > > + return irq; > > > + > > > + irq_set_chained_handler_and_data(irq, > keembay_pcie_msi_irq_handler, > > > + pcie); > > > + > > > > Ok this is yet another DWC MSI incantation and given that Marc worked > > hard consolidating them let's have a look before we merge it. > > > > IIUC - this IP relies on the DWC logic to handle MSIs + custom > > registers to detect a pending MSI IRQ because the logic in > > dw_chained_msi_irq() is *not* enough so you have to register > > a driver specific chained handler. This looks similar to the dra7xx > > driver MSI handling but I am not entirely convinced it is needed. > > > > I assume this code in keembay_pcie_msi_irq_handler() is required > > owing to additional IP logic on top of the standard DWC IP, in > > particular the PCIE_REGS_INTERRUPT_STATUS write to "clear" the > > IRQ. > > > > We need more insights before merging it so please provide them. > > > > pp =3D &pcie->pci.pp; > > val =3D readl(pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS); > > mask =3D readl(pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); > > > > status =3D val & mask; > > > > if (status & MSI_CTRL_INT) { > > dw_handle_msi_irq(pp); > > writel(status, pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS); > > } >=20 > Yes, your understanding is correct. >=20 > Additional registers PCIE_REGS_INTERRUPT_ENABLE/_STATUS are provided > by IP to control the interrupts. >=20 > To receive MSI interrupts, SW must enable bit '8' of _ENABLE register. > And once a MSI is raised by the End point, bit '8' of _STATUS register > will be set and it needs to be cleared after servicing the interrupt. Hope I have provided all the necessary information. Kindly feedback. Thanks! Srikanth >=20 > Thanks! > Srikanth >=20 > > > > Thanks, > > Lorenzo > > > > > +static void keembay_pcie_ep_init(struct dw_pcie_ep *ep) > > > +{ > > > + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); > > > + struct keembay_pcie *pcie =3D dev_get_drvdata(pci->dev); > > > + > > > + writel(EDMA_INT_EN, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); > > > +} > > > + > > > +static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 > func_no, > > > + enum pci_epc_irq_type type, > > > + u16 interrupt_num) > > > +{ > > > + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); > > > + > > > + switch (type) { > > > + case PCI_EPC_IRQ_LEGACY: > > > + /* Legacy interrupts are not supported in Keem Bay */ > > > + dev_err(pci->dev, "Legacy IRQ is not supported\n"); > > > + return -EINVAL; > > > + case PCI_EPC_IRQ_MSI: > > > + return dw_pcie_ep_raise_msi_irq(ep, func_no, > interrupt_num); > > > + case PCI_EPC_IRQ_MSIX: > > > + return dw_pcie_ep_raise_msix_irq(ep, func_no, > interrupt_num); > > > + default: > > > + dev_err(pci->dev, "Unknown IRQ type %d\n", type); > > > + return -EINVAL; > > > + } > > > +} > > > + > > > +static const struct pci_epc_features keembay_pcie_epc_features =3D { > > > + .linkup_notifier =3D false, > > > + .msi_capable =3D true, > > > + .msix_capable =3D true, > > > + .reserved_bar =3D BIT(BAR_1) | BIT(BAR_3) | BIT(BAR_5), > > > + .bar_fixed_64bit =3D BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4), > > > + .align =3D SZ_16K, > > > +}; > > > + > > > +static const struct pci_epc_features * > > > +keembay_pcie_get_features(struct dw_pcie_ep *ep) > > > +{ > > > + return &keembay_pcie_epc_features; > > > +} > > > + > > > +static const struct dw_pcie_ep_ops keembay_pcie_ep_ops =3D { > > > + .ep_init =3D keembay_pcie_ep_init, > > > + .raise_irq =3D keembay_pcie_ep_raise_irq, > > > + .get_features =3D keembay_pcie_get_features, > > > +}; > > > + > > > +static const struct dw_pcie_host_ops keembay_pcie_host_ops =3D { > > > +}; > > > + > > > +static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie, > > > + struct platform_device *pdev) > > > +{ > > > + struct dw_pcie *pci =3D &pcie->pci; > > > + struct pcie_port *pp =3D &pci->pp; > > > + struct device *dev =3D &pdev->dev; > > > + u32 val; > > > + int ret; > > > + > > > + pp->ops =3D &keembay_pcie_host_ops; > > > + pp->msi_irq =3D -ENODEV; > > > + > > > + ret =3D keembay_pcie_setup_msi_irq(pcie); > > > + if (ret) > > > + return ret; > > > + > > > + pcie->reset =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); > > > + if (IS_ERR(pcie->reset)) > > > + return PTR_ERR(pcie->reset); > > > + > > > + ret =3D keembay_pcie_probe_clocks(pcie); > > > + if (ret) > > > + return ret; > > > + > > > + val =3D readl(pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL); > > > + val |=3D PHY0_SRAM_BYPASS; > > > + writel(val, pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL); > > > + > > > + writel(PCIE_DEVICE_TYPE, pcie->apb_base + PCIE_REGS_PCIE_CFG); > > > + > > > + ret =3D keembay_pcie_pll_init(pcie); > > > + if (ret) > > > + return ret; > > > + > > > + val =3D readl(pcie->apb_base + PCIE_REGS_PCIE_CFG); > > > + writel(val | PCIE_RSTN, pcie->apb_base + PCIE_REGS_PCIE_CFG); > > > + keembay_ep_reset_deassert(pcie); > > > + > > > + ret =3D dw_pcie_host_init(pp); > > > + if (ret) { > > > + keembay_ep_reset_assert(pcie); > > > + dev_err(dev, "Failed to initialize host: %d\n", ret); > > > + return ret; > > > + } > > > + > > > + val =3D readl(pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); > > > + if (IS_ENABLED(CONFIG_PCI_MSI)) > > > + val |=3D MSI_CTRL_INT_EN; > > > + writel(val, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); > > > + > > > + return 0; > > > +} > > > + > > > +static int keembay_pcie_probe(struct platform_device *pdev) > > > +{ > > > + const struct keembay_pcie_of_data *data; > > > + struct device *dev =3D &pdev->dev; > > > + struct keembay_pcie *pcie; > > > + struct dw_pcie *pci; > > > + enum dw_pcie_device_mode mode; > > > + > > > + data =3D device_get_match_data(dev); > > > + if (!data) > > > + return -ENODEV; > > > + > > > + mode =3D (enum dw_pcie_device_mode)data->mode; > > > + > > > + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > > > + if (!pcie) > > > + return -ENOMEM; > > > + > > > + pci =3D &pcie->pci; > > > + pci->dev =3D dev; > > > + pci->ops =3D &keembay_pcie_ops; > > > + > > > + pcie->mode =3D mode; > > > + > > > + pcie->apb_base =3D devm_platform_ioremap_resource_byname(pdev, > "apb"); > > > + if (IS_ERR(pcie->apb_base)) > > > + return PTR_ERR(pcie->apb_base); > > > + > > > + platform_set_drvdata(pdev, pcie); > > > + > > > + switch (pcie->mode) { > > > + case DW_PCIE_RC_TYPE: > > > + if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_HOST)) > > > + return -ENODEV; > > > + > > > + return keembay_pcie_add_pcie_port(pcie, pdev); > > > + case DW_PCIE_EP_TYPE: > > > + if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_EP)) > > > + return -ENODEV; > > > + > > > + pci->ep.ops =3D &keembay_pcie_ep_ops; > > > + return dw_pcie_ep_init(&pci->ep); > > > + default: > > > + dev_err(dev, "Invalid device type %d\n", pcie->mode); > > > + return -ENODEV; > > > + } > > > +} > > > + > > > +static const struct keembay_pcie_of_data keembay_pcie_rc_of_data =3D > { > > > + .mode =3D DW_PCIE_RC_TYPE, > > > +}; > > > + > > > +static const struct keembay_pcie_of_data keembay_pcie_ep_of_data =3D > { > > > + .mode =3D DW_PCIE_EP_TYPE, > > > +}; > > > + > > > +static const struct of_device_id keembay_pcie_of_match[] =3D { > > > + { > > > + .compatible =3D "intel,keembay-pcie", > > > + .data =3D &keembay_pcie_rc_of_data, > > > + }, > > > + { > > > + .compatible =3D "intel,keembay-pcie-ep", > > > + .data =3D &keembay_pcie_ep_of_data, > > > + }, > > > + {} > > > +}; > > > + > > > +static struct platform_driver keembay_pcie_driver =3D { > > > + .driver =3D { > > > + .name =3D "keembay-pcie", > > > + .of_match_table =3D keembay_pcie_of_match, > > > + .suppress_bind_attrs =3D true, > > > + }, > > > + .probe =3D keembay_pcie_probe, > > > +}; > > > +builtin_platform_driver(keembay_pcie_driver); > > > -- > > > 2.17.1 > > >