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From: "Thokala, Srikanth" <srikanth.thokala@intel.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	PCI <linux-pci@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Mark Gross <mgross@linux.intel.com>,
	"Raja Subramanian,
	Lakshmi Bai"  <lakshmi.bai.raja.subramanian@intel.com>,
	"Sangannavar,
	Mallikarjunappa"  <mallikarjunappa.sangannavar@intel.com>,
	Krzysztof Wilczynski <kw@linux.com>
Subject: RE: [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem Bay
Date: Wed, 16 Jun 2021 07:49:27 +0000	[thread overview]
Message-ID: <PH0PR11MB559572D1AA5A56294211A432850F9@PH0PR11MB5595.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CAL_JsqJmLz2TChWYGtEGtHpd5aO4hp+zvx8cExb760PDsx-nRg@mail.gmail.com>

Hi Rob,

> -----Original Message-----
> From: Rob Herring <robh+dt@kernel.org>
> Sent: Wednesday, June 16, 2021 2:39 AM
> To: Thokala, Srikanth <srikanth.thokala@intel.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>; PCI <linux-
> pci@vger.kernel.org>; devicetree@vger.kernel.org; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; Mark Gross <mgross@linux.intel.com>;
> Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>;
> Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com>;
> Krzysztof Wilczynski <kw@linux.com>
> Subject: Re: [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem Bay
> 
> On Mon, Jun 7, 2021 at 1:47 AM <srikanth.thokala@intel.com> wrote:
> >
> > From: Srikanth Thokala <srikanth.thokala@intel.com>
> >
> > Add driver for Intel Keem Bay SoC PCIe controller. This controller
> > is based on DesignWare PCIe core.
> >
> > In Root Complex mode, only internal reference clock is possible for
> > Keem Bay A0. For Keem Bay B0, external reference clock can be used
> > and will be the default configuration. Currently, keembay_pcie_of_data
> > structure has one member. It will be expanded later to handle this
> > difference.
> >
> > Endpoint mode link initialization is handled by the boot firmware.
> >
> > Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> > Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Signed-off-by: Srikanth Thokala <srikanth.thokala@intel.com>
> > Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
> > ---
> >  MAINTAINERS                               |   7 +
> >  drivers/pci/controller/dwc/Kconfig        |  28 ++
> >  drivers/pci/controller/dwc/Makefile       |   1 +
> >  drivers/pci/controller/dwc/pcie-keembay.c | 451 ++++++++++++++++++++++
> >  4 files changed, 487 insertions(+)
> >  create mode 100644 drivers/pci/controller/dwc/pcie-keembay.c
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

Thank you, Rob, for the "Reviewed-by".

Srikanth

  reply	other threads:[~2021-06-16  7:49 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-07 15:40 [PATCH v10 0/2] PCI: keembay: Add support for Intel Keem Bay srikanth.thokala
2021-06-07 15:40 ` [PATCH v10 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller srikanth.thokala
2021-06-07 15:40 ` [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem Bay srikanth.thokala
2021-06-15 21:09   ` Rob Herring
2021-06-16  7:49     ` Thokala, Srikanth [this message]
2021-06-21 16:53   ` Lorenzo Pieralisi
2021-06-25  3:23     ` Thokala, Srikanth
2021-07-07 11:54       ` Thokala, Srikanth
2021-07-26  6:30         ` Thokala, Srikanth
2021-07-26  8:00       ` Marc Zyngier
2021-07-27 16:26         ` Thokala, Srikanth
2021-06-15 14:38 ` [PATCH v10 0/2] " Thokala, Srikanth

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