* [PATCH] drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10
@ 2021-06-07 5:55 Peng Ju Zhou
2021-06-07 8:55 ` Deng, Emily
0 siblings, 1 reply; 2+ messages in thread
From: Peng Ju Zhou @ 2021-06-07 5:55 UTC (permalink / raw)
To: amd-gfx
The NV12 and VEGA10 share the same interface W/RREG32_SOC15*,
the callback functions in these macros may not be defined,
so NULL pointer must be checked but not in
macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fe5908f708cc..044076ec1d03 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -790,7 +790,8 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f
static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
u32 v, u32 acc_flags, u32 hwip)
{
- if (amdgpu_sriov_fullaccess(adev)) {
+ if ((acc_flags & AMDGPU_REGS_RLC) &&
+ amdgpu_sriov_fullaccess(adev)) {
gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
return;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index f6cf70e69cce..0eeb5e073be8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -28,12 +28,12 @@
#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
- ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
+ ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_wreg) ? \
adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
WREG32(reg, value))
#define __RREG32_SOC15_RLC__(reg, flag, hwip) \
- ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
+ ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_rreg) ? \
adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
RREG32(reg))
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 2+ messages in thread
* RE: [PATCH] drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10
2021-06-07 5:55 [PATCH] drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10 Peng Ju Zhou
@ 2021-06-07 8:55 ` Deng, Emily
0 siblings, 0 replies; 2+ messages in thread
From: Deng, Emily @ 2021-06-07 8:55 UTC (permalink / raw)
To: Zhou, Peng Ju, amd-gfx
[AMD Official Use Only]
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Peng Ju
>Zhou
>Sent: Monday, June 7, 2021 1:55 PM
>To: amd-gfx@lists.freedesktop.org
>Subject: [PATCH] drm/amdgpu: Fixing "Indirect register access for Navi12 sriov"
>for vega10
>
>The NV12 and VEGA10 share the same interface W/RREG32_SOC15*, the
>callback functions in these macros may not be defined, so NULL pointer must be
>checked but not in macro __WREG32_SOC15_RLC__, fixing the lock of NULL
>pointer check.
>
>Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>index fe5908f708cc..044076ec1d03 100644
>--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>@@ -790,7 +790,8 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device
>*adev, u32 offset, u32 v, u32 f static void gfx_v9_0_rlcg_wreg(struct
>amdgpu_device *adev, u32 offset,
> u32 v, u32 acc_flags, u32 hwip) {
>- if (amdgpu_sriov_fullaccess(adev)) {
>+ if ((acc_flags & AMDGPU_REGS_RLC) &&
>+ amdgpu_sriov_fullaccess(adev)) {
> gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
>
> return;
>diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>index f6cf70e69cce..0eeb5e073be8 100644
>--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>@@ -28,12 +28,12 @@
> #define SOC15_REG_OFFSET(ip, inst, reg) (adev-
>>reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>
> #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
>- ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
>+ ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs &&
>+adev->gfx.rlc.funcs->rlcg_wreg) ? \
> adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
> WREG32(reg, value))
>
> #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
>- ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
>+ ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs &&
>+adev->gfx.rlc.funcs->rlcg_rreg) ? \
> adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
> RREG32(reg))
>
>--
>2.17.1
>
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2021-06-07 8:55 ` Deng, Emily
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