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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR12MB5481.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 690bd8cb-dc6e-47dd-721d-08db38a89b85 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2023 03:15:01.7543 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: H5T+vPsKYB6MKRM4wAM4uVy9HfyMks5F8H/ko2XzNhWeWaXYUat8TOafRwJmupppCWEZwYHX0H799qyjgL6sNQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5950 Subject: [virtio-dev] RE: [virtio-comment] Re: [PATCH 07/11] transport-pci: Introduce transitional MMR device id > From: Michael S. Tsirkin > Sent: Friday, April 7, 2023 11:51 AM > > 1. A non-transitional device will expose a capability (not a feature bi= t, but a > capability at transport level). >=20 > Note that we can allow this capability in transitional devices too. > This is useful since IO bar might not be enabled even if present. > This capability exposure makes a device transitional in some sense. =20 > > This capability indicates that, it supports legacy interface. > > Lets name it legacy_if_emulation for sake of this discussion. > > It is a two-way pci capability. > > Device reports it. > > And driver enables it. (Why two way and why driver needs to enable it, > described later in point #d below). > > > > Hence, such non transitional device does not need to comply to below li= sted > requirements #a and #b. > > > > a. A driver MUST accept VIRTIO_F_VERSION_1 if it is offered. > > (Because hypervisor driver is a passthrough driver; and legacy driver w= ill not > accept this feature bit). >=20 > This is not a device requirement at all. >=20 Those this is written as driver requirement; a device expects this feature = bit to be negotiated. What should device implementor do? It should allow driver to not negotiate = bit, right? Which means, below line to be change: from: device MAY fail to operate further if VIRTIO_F_VERSION_1 is not accepted. to: Non transitional device that does not have legacy interface capability MAY = fail to operate further if V_1 is not accepted. Non transitional device that has legacy interface capability SHOULD operate= further even if V_1 is not accepted. > > b. device MAY fail to operate further if VIRTIO_F_VERSION_1 is not acce= pted. >=20 > This is optional not a requirement. >=20 Please see above wording, if its acceptable. > > c. A non-transitional device with above legacy_if_supported > > capability, will allow device reset sequence, described in [1] Driver > > Requirements: Device Initialization (3.1.1) [2] Legacy Interface: > > Device Initialization (3.1.2) > > > > > > device reset sequence. > > > > > > what is this one? > > > > I listed above in #c. > > And > > > > d. When legacy_if_emulation capability is offered and hypervisor driver > enabled it, when driver perform device reset, driver will not wait for de= vice > reset to go zero. > > When legacy_if_emulation capability is not enabled by (hypervisor or ot= her > say existing) driver, driver will wait for device reset to turn 0. (Follo= wing the > driver requirement 2.4.2). >=20 > It might not be a bad idea to enable it, but I observe that it is possibl= e for > hypervisor to expose a standard transitional device on top of this MMR > capability. Thus it will not be known whether guest driver accesses legac= y or > modern BAR until guest runs. > I propose, instead, that device exposes same registers at two addresses a= nd > executes reset correctly depending on which address it was accessed throu= gh. > WDYT? Yep, this the exact proposal here. Legacy registers exposes via AQ (aka TVQ) or MMR location, behaves like leg= acy. And regular registers at their location as-is. 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Tsirkin" CC: "virtio-dev@lists.oasis-open.org" , "cohuck@redhat.com" , "virtio-comment@lists.oasis-open.org" , Shahaf Shuler , Satananda Burla Thread-Topic: [virtio-comment] Re: [PATCH 07/11] transport-pci: Introduce transitional MMR device id Thread-Index: AQHZY1tHbf+nicr9uUaxzLNq1cXcgq8ax2UAgACRZQCABHJagIAALYOwgAASQQCAAkyugA== Date: Sun, 9 Apr 2023 03:15:01 +0000 Message-ID: References: <20230330225834.506969-1-parav@nvidia.com> <20230330225834.506969-8-parav@nvidia.com> <20230404032700-mutt-send-email-mst@kernel.org> <94b217ee-29d9-42da-f2b8-28ced7e64371@nvidia.com> <20230407074605-mutt-send-email-mst@kernel.org> <20230407113737-mutt-send-email-mst@kernel.org> In-Reply-To: <20230407113737-mutt-send-email-mst@kernel.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR12MB5481:EE_|PH7PR12MB5950:EE_ x-ms-office365-filtering-correlation-id: 690bd8cb-dc6e-47dd-721d-08db38a89b85 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR12MB5481.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 690bd8cb-dc6e-47dd-721d-08db38a89b85 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2023 03:15:01.7543 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: H5T+vPsKYB6MKRM4wAM4uVy9HfyMks5F8H/ko2XzNhWeWaXYUat8TOafRwJmupppCWEZwYHX0H799qyjgL6sNQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5950 Subject: RE: [virtio-comment] Re: [PATCH 07/11] transport-pci: Introduce transitional MMR device id > From: Michael S. Tsirkin > Sent: Friday, April 7, 2023 11:51 AM > > 1. A non-transitional device will expose a capability (not a feature bi= t, but a > capability at transport level). >=20 > Note that we can allow this capability in transitional devices too. > This is useful since IO bar might not be enabled even if present. > This capability exposure makes a device transitional in some sense. =20 > > This capability indicates that, it supports legacy interface. > > Lets name it legacy_if_emulation for sake of this discussion. > > It is a two-way pci capability. > > Device reports it. > > And driver enables it. (Why two way and why driver needs to enable it, > described later in point #d below). > > > > Hence, such non transitional device does not need to comply to below li= sted > requirements #a and #b. > > > > a. A driver MUST accept VIRTIO_F_VERSION_1 if it is offered. > > (Because hypervisor driver is a passthrough driver; and legacy driver w= ill not > accept this feature bit). >=20 > This is not a device requirement at all. >=20 Those this is written as driver requirement; a device expects this feature = bit to be negotiated. What should device implementor do? It should allow driver to not negotiate = bit, right? Which means, below line to be change: from: device MAY fail to operate further if VIRTIO_F_VERSION_1 is not accepted. to: Non transitional device that does not have legacy interface capability MAY = fail to operate further if V_1 is not accepted. Non transitional device that has legacy interface capability SHOULD operate= further even if V_1 is not accepted. > > b. device MAY fail to operate further if VIRTIO_F_VERSION_1 is not acce= pted. >=20 > This is optional not a requirement. >=20 Please see above wording, if its acceptable. > > c. A non-transitional device with above legacy_if_supported > > capability, will allow device reset sequence, described in [1] Driver > > Requirements: Device Initialization (3.1.1) [2] Legacy Interface: > > Device Initialization (3.1.2) > > > > > > device reset sequence. > > > > > > what is this one? > > > > I listed above in #c. > > And > > > > d. When legacy_if_emulation capability is offered and hypervisor driver > enabled it, when driver perform device reset, driver will not wait for de= vice > reset to go zero. > > When legacy_if_emulation capability is not enabled by (hypervisor or ot= her > say existing) driver, driver will wait for device reset to turn 0. (Follo= wing the > driver requirement 2.4.2). >=20 > It might not be a bad idea to enable it, but I observe that it is possibl= e for > hypervisor to expose a standard transitional device on top of this MMR > capability. Thus it will not be known whether guest driver accesses legac= y or > modern BAR until guest runs. > I propose, instead, that device exposes same registers at two addresses a= nd > executes reset correctly depending on which address it was accessed throu= gh. > WDYT? Yep, this the exact proposal here. Legacy registers exposes via AQ (aka TVQ) or MMR location, behaves like leg= acy. And regular registers at their location as-is. With that feature bit negotiation is the only thing to relax like worded ab= ove. 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