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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR12MB5481.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 827a99e6-0d9d-497b-75ce-08db3483febe X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Apr 2023 20:42:52.2208 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: STLFrmV/I+utO/35o3dsQClVyhlMMMBrT0GJpZYyy7gP/2zdd5r1t7IXpUGifEiiFf6ceosYwEkxnuCV7v3QWw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4928 Subject: [virtio-dev] RE: [virtio-comment] [PATCH 00/11] Introduce transitional mmr pci device > From: Michael S. Tsirkin > Sent: Monday, April 3, 2023 4:03 PM >=20 > On Mon, Apr 03, 2023 at 07:48:56PM +0000, Parav Pandit wrote: > > > OK but supporting them with a passthrough driver such as vfio does > > > not seem that important. > > Not sure on what basis you assert it. > > I clarified in the cover letter that these are the user level requireme= nts to > support transitional and non-transitional devices both via single vfio su= bsystem. >=20 > And what is so wrong with vdpa? Really I don't see how the virtio spec n= eeds to > accomodate specific partitioning between linux modules, be it vdpa or vfi= o. > Way beyond the scope of the driver. > vdpa has its own value. Here requirements are different as listed so let's focus on it. =20 > But anyway, my main > point is about DMA. On the one hand you are asking for a VQ based > management interface because it saves money. On the other you are saying > DMA operations take extremely long to the point where they are unusable i= n > the boot sequence. I think you missed the point I described few emails back. The legacy registers are subset of the 1.x registers, so a device that impl= ements existing 1.x registers, they get legacy registers for free. Hence, there is no _real_ saving. > So what is it? Was admin vq a mistake and we should do memory mapped? No. Certainly not. AQ is needed for LM, SR-IOV (SR-PCIM management), SIOV device life cycle. > Or is > legacy emulation doable over a vq and latency is not a concern, and the r= eal > reason is because it makes you push out a host driver with a bit less eff= ort? >=20 Legacy registers emulation is doable over VQ and has its merits (I listed i= n previous email). I forgot to mention in previous email that device reset is also better via = tvq. It is just that legacy_registers_transport_vq (LRT_VQ) requires more comple= x hypervisor driver and only works for the VFs. At spec level, MMR has value on the PF as well, hence I previously proposed= last week on your first email that spec should allow both. Efforts of hypervisor not really a big concern. Once we converge that LRT_VQ is good, it is viable option too. I will shortly send out little more verbose command on lrt_vq so that its o= ptimal enough. > I just do not see how these claims do not contradict each other. An AQ for queuing, parallelism, memory saving. --------------------------------------------------------------------- To unsubscribe, e-mail: virtio-dev-unsubscribe@lists.oasis-open.org For additional commands, e-mail: virtio-dev-help@lists.oasis-open.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from ws5-mx01.kavi.com (ws5-mx01.kavi.com [34.193.7.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BED9C76188 for ; Mon, 3 Apr 2023 20:42:57 +0000 (UTC) Received: from lists.oasis-open.org (oasis.ws5.connectedcommunity.org [10.110.1.242]) by ws5-mx01.kavi.com (Postfix) with ESMTP id 9933060342 for ; Mon, 3 Apr 2023 20:42:56 +0000 (UTC) Received: from lists.oasis-open.org (oasis-open.org [10.110.1.242]) by lists.oasis-open.org (Postfix) with ESMTP id 7B25A9863E5 for ; Mon, 3 Apr 2023 20:42:56 +0000 (UTC) Received: from host09.ws5.connectedcommunity.org (host09.ws5.connectedcommunity.org [10.110.1.97]) by lists.oasis-open.org (Postfix) with QMQP id 677889843C6; Mon, 3 Apr 2023 20:42:56 +0000 (UTC) Mailing-List: contact virtio-comment-help@lists.oasis-open.org; run by ezmlm List-ID: Sender: Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: Received: from lists.oasis-open.org (oasis-open.org [10.110.1.242]) by lists.oasis-open.org (Postfix) with ESMTP id 5525F9863E4; Mon, 3 Apr 2023 20:42:56 +0000 (UTC) X-Virus-Scanned: amavisd-new at kavi.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=M+s3JMGBxg/SX6K2yVMhbGj80UNfv/I4c0bTHLsTsPJ6nql1RlgUNSNgBVUCxrIwGYpQ2X9ZaEGeLfOGg1jIkEwSnFXeZcDwMOI6R6b7MznOH8eHK/NkhfxEIhNsa7EmdYKCN7rek0wog7DGDsLze+W9FGNTLTwRdgLpivrtiKLOwR94ZxW2ucBo4YiQCeCN1IeO4sgS6UbEUet/08h8fk5KGFa6sxAzUSsCCV+QvutNcSoQkEobBL6MIta9rMxJCujMS9HtZ284xiqKW/9sdKWugaNlHniD6Yb+U/dZdwgfJb8YIxEVY/yJke9X48tQh/sYkrj+jXDfj6TvEqY3sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nCXMn/UDUH/X/mTyvwX9UezfLL8QcuzgJO5F2jInSoE=; b=X96xM1/w3gSUG5tVeh0rLuW7BdwS+h0AvNIFSmW4InQn/TeffG9gf2KTk8nDw794rZ0MvDULZpMJZq2UbDO2e9mijeOjaqPUDYCftcQTrd1oDyNeZXMrVD+mVtc63kEIOvzkaU5SzhFmNxKC/eLgX5leJWz+09IfkChu7y22YvMYbATwfVoyQWxs8DUlEhU2Tgj75v/TKn43rZIIClZiR/74MbkySlSd0mjvZ4zQqvjDMjOYvlzU7NU0d5O4WhHRv7jbD3IGDfazfIQvpIGbJTJRcg0O4WPI8xVksPUDlYZ+4ZE0ynSdCmFFfmas7ljFw7yCeNWr8zsKOLap7OEe3w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none From: Parav Pandit To: "Michael S. Tsirkin" CC: Stefan Hajnoczi , "virtio-dev@lists.oasis-open.org" , "cohuck@redhat.com" , "virtio-comment@lists.oasis-open.org" , Shahaf Shuler Thread-Topic: [virtio-comment] [PATCH 00/11] Introduce transitional mmr pci device Thread-Index: AQHZY1tF5ObSeHDFk0eWHj0gIzL7fK8ZryCAgABed4D//9TGAIAAINwQgAAEjICAAAc8YA== Date: Mon, 3 Apr 2023 20:42:52 +0000 Message-ID: References: <20230330225834.506969-1-parav@nvidia.com> <20230403144523.GC302168@fedora> <46a0db06-f922-2a8a-acf0-cf7e453a2945@nvidia.com> <20230403134407-mutt-send-email-mst@kernel.org> <20230403155310-mutt-send-email-mst@kernel.org> In-Reply-To: <20230403155310-mutt-send-email-mst@kernel.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR12MB5481:EE_|DM6PR12MB4928:EE_ x-ms-office365-filtering-correlation-id: 827a99e6-0d9d-497b-75ce-08db3483febe x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR12MB5481.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 827a99e6-0d9d-497b-75ce-08db3483febe X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Apr 2023 20:42:52.2208 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: STLFrmV/I+utO/35o3dsQClVyhlMMMBrT0GJpZYyy7gP/2zdd5r1t7IXpUGifEiiFf6ceosYwEkxnuCV7v3QWw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4928 Subject: RE: [virtio-comment] [PATCH 00/11] Introduce transitional mmr pci device > From: Michael S. Tsirkin > Sent: Monday, April 3, 2023 4:03 PM >=20 > On Mon, Apr 03, 2023 at 07:48:56PM +0000, Parav Pandit wrote: > > > OK but supporting them with a passthrough driver such as vfio does > > > not seem that important. > > Not sure on what basis you assert it. > > I clarified in the cover letter that these are the user level requireme= nts to > support transitional and non-transitional devices both via single vfio su= bsystem. >=20 > And what is so wrong with vdpa? Really I don't see how the virtio spec n= eeds to > accomodate specific partitioning between linux modules, be it vdpa or vfi= o. > Way beyond the scope of the driver. > vdpa has its own value. Here requirements are different as listed so let's focus on it. =20 > But anyway, my main > point is about DMA. On the one hand you are asking for a VQ based > management interface because it saves money. On the other you are saying > DMA operations take extremely long to the point where they are unusable i= n > the boot sequence. I think you missed the point I described few emails back. The legacy registers are subset of the 1.x registers, so a device that impl= ements existing 1.x registers, they get legacy registers for free. Hence, there is no _real_ saving. > So what is it? Was admin vq a mistake and we should do memory mapped? No. Certainly not. AQ is needed for LM, SR-IOV (SR-PCIM management), SIOV device life cycle. > Or is > legacy emulation doable over a vq and latency is not a concern, and the r= eal > reason is because it makes you push out a host driver with a bit less eff= ort? >=20 Legacy registers emulation is doable over VQ and has its merits (I listed i= n previous email). I forgot to mention in previous email that device reset is also better via = tvq. It is just that legacy_registers_transport_vq (LRT_VQ) requires more comple= x hypervisor driver and only works for the VFs. At spec level, MMR has value on the PF as well, hence I previously proposed= last week on your first email that spec should allow both. Efforts of hypervisor not really a big concern. Once we converge that LRT_VQ is good, it is viable option too. I will shortly send out little more verbose command on lrt_vq so that its o= ptimal enough. > I just do not see how these claims do not contradict each other. An AQ for queuing, parallelism, memory saving. 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