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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR02MB8560.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f9505ad4-77c1-49c2-88c7-08d9d68b4333 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Jan 2022 11:53:06.4791 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: OV3j/H/4W7e6VNJZqt1BiGIf0u8d/36q4Wm8nU4LHRbEMmHcU03V8fMaj4Tf094nLw+8FzUG/Jl1Pj98+DFQFQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB4919 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > -----Original Message----- > From: Robert Hancock > Sent: Wednesday, January 12, 2022 11:07 PM > To: netdev@vger.kernel.org > Cc: Radhey Shyam Pandey ; davem@davemloft.net; > kuba@kernel.org; linux-arm-kernel@lists.infradead.org; Michal Simek > ; ariane.keller@tik.ee.ethz.ch; daniel@iogearbox.net; > Robert Hancock > Subject: [PATCH net v2 2/9] net: axienet: Wait for PhyRstCmplt after core= reset >=20 > When resetting the device, wait for the PhyRstCmplt bit to be set > in the interrupt status register before continuing initialization, to > ensure that the core is actually ready. The MgtRdy bit could also be > waited for, but unfortunately when using 7-series devices, the bit does Just to understand - can you share 7- series design details. Based on documentation - This MgtRdy bit indicates if the TEMAC core is out of reset and ready for use. In systems that use an serial transceiver,= =20 this bit goes to 1 when the serial transceiver is ready to use. Also if we don't wait for phy reset - what is the issue we are seeing? > not appear to work as documented (it seems to behave as some sort of > link state indication and not just an indication the transceiver is > ready) so it can't really be relied on. >=20 > Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethe= rnet > driver") > Signed-off-by: Robert Hancock > --- > drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) >=20 > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > index f950342f6467..f425a8404a9b 100644 > --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > @@ -516,6 +516,16 @@ static int __axienet_device_reset(struct axienet_loc= al > *lp) > return ret; > } >=20 > + /* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has > finished */ > + ret =3D read_poll_timeout(axienet_ior, value, > + value & XAE_INT_PHYRSTCMPLT_MASK, > + DELAY_OF_ONE_MILLISEC, 50000, false, lp, > + XAE_IS_OFFSET); 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Robert Hancock > Sent: Wednesday, January 12, 2022 11:07 PM > To: netdev@vger.kernel.org > Cc: Radhey Shyam Pandey ; davem@davemloft.net; > kuba@kernel.org; linux-arm-kernel@lists.infradead.org; Michal Simek > ; ariane.keller@tik.ee.ethz.ch; daniel@iogearbox.net; > Robert Hancock > Subject: [PATCH net v2 2/9] net: axienet: Wait for PhyRstCmplt after core reset > > When resetting the device, wait for the PhyRstCmplt bit to be set > in the interrupt status register before continuing initialization, to > ensure that the core is actually ready. The MgtRdy bit could also be > waited for, but unfortunately when using 7-series devices, the bit does Just to understand - can you share 7- series design details. Based on documentation - This MgtRdy bit indicates if the TEMAC core is out of reset and ready for use. In systems that use an serial transceiver, this bit goes to 1 when the serial transceiver is ready to use. Also if we don't wait for phy reset - what is the issue we are seeing? > not appear to work as documented (it seems to behave as some sort of > link state indication and not just an indication the transceiver is > ready) so it can't really be relied on. > > Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet > driver") > Signed-off-by: Robert Hancock > --- > drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > index f950342f6467..f425a8404a9b 100644 > --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > @@ -516,6 +516,16 @@ static int __axienet_device_reset(struct axienet_local > *lp) > return ret; > } > > + /* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has > finished */ > + ret = read_poll_timeout(axienet_ior, value, > + value & XAE_INT_PHYRSTCMPLT_MASK, > + DELAY_OF_ONE_MILLISEC, 50000, false, lp, > + XAE_IS_OFFSET); > + if (ret) { > + dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", > __func__); > + return ret; > + } > + > return 0; > } > > -- > 2.31.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel