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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB6991.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3e3cd558-e377-453a-5337-08dc4d1b3a7a X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Mar 2024 22:30:52.0000 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LE43Jcpn7mEt//Z8pOosF/cp63bNRiB6vUlEQYG1pHHoP2JylqNHKalJhiM5NRPgjfUZZi12Bzx6F2w0qXL5ow== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR11MB7953 X-OriginatorOrg: intel.com X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" > -----Original Message----- > From: Intel-xe On Behalf Of Matt= hew > Brost > Sent: Friday, March 8, 2024 12:08 AM > To: intel-xe@lists.freedesktop.org > Cc: Brost, Matthew > Subject: [PATCH v4 16/30] drm/xe: Use ordered WQ for TLB invalidation fen= ces >=20 > TLB invalidation fences need to be ordered within an exec queue and if > an unordered WQ is used TLB invalidation fences could be reordered. Use > an ordered WQ to fix this. The code change below makes sense to me. But I think we should improve the = description. I think we need to explain what need to be in order and why. A= s I understand it, we need things to be in below order (just an example): 1)Gpu page table update (such as invalidate certain page table) 2)Invalidate tlb entries for above page table entries 3)Notify/call back to user fence to let user know above vm_unbind is comple= te. Obviously 1) and 2) can't be re-ordered, because 2) should be triggered by = 1). But 2) and 3) can be reordered if we use unordered WQ - why we want to = use ordered wq here. Simply saying TLB invalidation fences need to be ordered is too simple, at = least it is hard for me to understand. Better to improve it. Thanks, Oak >=20 > Signed-off-by: Matthew Brost > --- > drivers/gpu/drm/xe/xe_pt.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c > index 110d6917089b..a878e2217c7f 100644 > --- a/drivers/gpu/drm/xe/xe_pt.c > +++ b/drivers/gpu/drm/xe/xe_pt.c > @@ -1107,7 +1107,7 @@ static void invalidation_fence_cb(struct dma_fence > *fence, >=20 > trace_xe_gt_tlb_invalidation_fence_cb(&ifence->base); > if (!ifence->fence->error) { > - queue_work(system_wq, &ifence->work); > + queue_work(ifence->gt->ordered_wq, &ifence->work); > } else { > ifence->base.base.error =3D ifence->fence->error; > dma_fence_signal(&ifence->base.base); > -- > 2.34.1