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boundary="_000_SG2PR03MB4263ED48818608B30AE3C801D5F39SG2PR03MB4263apcp_" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SG2PR03MB4263.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1f3f6a8d-7919-4fc4-7700-08d958a11a25 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2021 06:11:59.9658 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: e3ec21b7-ec6c-4041-9add-61aea8171458 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yB5tYgLPb3dNIgIeOk54YXRIEWLqWdurQmIkA3Blf/eZgcAB6D7jYGxmLKweiOGO37UFgrL5OHqj+J4YMbOR2A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR03MB2782 X-OriginatorOrg: andestech.com X-DNSRBL: X-MAIL: ATCSQR.andestech.com 1766C30u088887 Received-SPF: pass client-ip=60.248.187.195; envelope-from=ruinland@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: 32 X-Spam_score: 3.2 X-Spam_bar: +++ X-Spam_report: (3.2 / 5.0 requ) BAYES_40=-0.001, CHARSET_FARAWAY_HEADER=3.2, HTML_MESSAGE=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangjunqiang , Bin Meng , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , =?iso-2022-jp?B?RHlsYW4gRGFpLVJvbmcgSmhvbmcoGyRCPmFCUk07GyhCKQ==?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --_000_SG2PR03MB4263ED48818608B30AE3C801D5F39SG2PR03MB4263apcp_ Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Hi Bin and Alistair, >> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without > The latest RISC-V core from Andes is AX45 and A45. Should we just > support the latest one? Maybe we can have them all ? AX25 and A25 is still in production, and we still have new clients using th= ese CPU models. >> +static void ax25_cpu_init(Object *obj) >nits: for name consistency, should be rv64_andes_ax25_cpu_init() Will do. >> +static void a25_cpu_init(Object *obj) >nits: rv32_andes_a25_cpu_init() Will do. > +{ > + CPURISCVState *env =3D &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > #endif > > Regards, > Bin My sincere regards, Ruinland CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally priv= ileged information or information protected from disclosure. If you are not= the intended recipient, you are hereby notified that any disclosure, copyi= ng, distribution, or use of the information contained herein is strictly pr= ohibited. In this case, please immediately notify the sender by return e-ma= il, delete the message (and any accompanying documents) and destroy all pri= nted hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved. --_000_SG2PR03MB4263ED48818608B30AE3C801D5F39SG2PR03MB4263apcp_ Content-Type: text/html; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable
Hi Bin and Alistair,

>> Adding Andes AX25 and A25 CPU model into = cpu.h and cpu.c without

> The latest RISC-V core from Andes is AX45 and A45. Should we just
> support the latest one?

Maybe we can have them all ?
AX25 and A25 is still in production, and we s= till have new clients using these CPU models.

>> +static void ax25_cpu_init(Object *obj)
>nits: for name consistency, should be rv64_andes_ax25_cpu_init()

Will do.


>> +static void a25_cpu_init(Object *obj)
>nits: rv32_andes_a25_cpu_init()

Will do.

> +{
> +    CPURISCVState *env =3D &RISCV_CPU(obj)->env= ;
> +    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD |= RVC | RVS | RVU);
> +    set_priv_version(env, PRIV_VERSION_1_10_0);
> +}
>  #endif
>

> Regards,
> Bin

My sincere regards,
Ruinland
CONFIDENTIALITY NOTICE:

This e-mail (and its attachments) may contain confidential and legally priv= ileged information or information protected from disclosure. If you are not= the intended recipient, you are hereby notified that any disclosure, copyi= ng, distribution, or use of the information contained herein is strictly prohibited. In this case, please = immediately notify the sender by return e-mail, delete the message (and any= accompanying documents) and destroy all printed hard copies. Thank you for= your cooperation.

Copyright ANDES TECHNOLOGY CORPORATION - Al= l Rights Reserved.
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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Hi Bin and Alistair, >> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without > The latest RISC-V core from Andes is AX45 and A45. Should we just > support the latest one? Maybe we can have them all ? AX25 and A25 is still in production, and we still have new clients using th= ese CPU models. >> +static void ax25_cpu_init(Object *obj) >nits: for name consistency, should be rv64_andes_ax25_cpu_init() Will do. >> +static void a25_cpu_init(Object *obj) >nits: rv32_andes_a25_cpu_init() Will do. > +{ > + CPURISCVState *env =3D &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > #endif > > Regards, > Bin My sincere regards, Ruinland CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally priv= ileged information or information protected from disclosure. If you are not= the intended recipient, you are hereby notified that any disclosure, copyi= ng, distribution, or use of the information contained herein is strictly pr= ohibited. In this case, please immediately notify the sender by return e-ma= il, delete the message (and any accompanying documents) and destroy all pri= nted hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved. --_000_SG2PR03MB4263ED48818608B30AE3C801D5F39SG2PR03MB4263apcp_ Content-Type: text/html; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable
Hi Bin and Alistair,

>> Adding Andes AX25 and A25 CPU model into = cpu.h and cpu.c without

> The latest RISC-V core from Andes is AX45 and A45. Should we just
> support the latest one?

Maybe we can have them all ?
AX25 and A25 is still in production, and we s= till have new clients using these CPU models.

>> +static void ax25_cpu_init(Object *obj)
>nits: for name consistency, should be rv64_andes_ax25_cpu_init()

Will do.


>> +static void a25_cpu_init(Object *obj)
>nits: rv32_andes_a25_cpu_init()

Will do.

> +{
> +    CPURISCVState *env =3D &RISCV_CPU(obj)->env= ;
> +    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD |= RVC | RVS | RVU);
> +    set_priv_version(env, PRIV_VERSION_1_10_0);
> +}
>  #endif
>

> Regards,
> Bin

My sincere regards,
Ruinland
CONFIDENTIALITY NOTICE:

This e-mail (and its attachments) may contain confidential and legally priv= ileged information or information protected from disclosure. If you are not= the intended recipient, you are hereby notified that any disclosure, copyi= ng, distribution, or use of the information contained herein is strictly prohibited. In this case, please = immediately notify the sender by return e-mail, delete the message (and any= accompanying documents) and destroy all printed hard copies. Thank you for= your cooperation.

Copyright ANDES TECHNOLOGY CORPORATION - Al= l Rights Reserved.
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