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Fri, 13 Aug 2021 16:48:51 +0000 Date: Fri, 13 Aug 2021 11:48:49 -0500 From: Chris Morgan To: Jon Lin Cc: u-boot@lists.denx.de, heiko.stuebner@theobroma-systems.com, vigneshr@ti.com, jagan@amarulasolutions.com, kever.yang@rock-chips.com, philipp.tomsich@vrull.eu, sjg@chromium.org Subject: Re: [PATCH v8 1/5] spi: rockchip_sfc: add support for Rockchip SFC Message-ID: References: <20210812131518.21328-1-jon.lin@rock-chips.com> <20210812211334.v8.1.I8f4599cf3ce092922c55387eeb6a8cd984845d08@changeid> <9f84e908-de4a-9550-61f1-80d8fafcf5b4@rock-chips.com> Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9f84e908-de4a-9550-61f1-80d8fafcf5b4@rock-chips.com> X-TMN: [ubbqGBybDpWRbesMpiTVBaQnlzKEN6Jg] X-ClientProxiedBy: SA0PR11CA0147.namprd11.prod.outlook.com (2603:10b6:806:131::32) To SN6PR06MB5342.namprd06.prod.outlook.com (2603:10b6:805:f9::31) X-Microsoft-Original-Message-ID: <20210813164849.GA3327@wintermute.localdomain> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wintermute.localdomain (76.183.134.35) by SA0PR11CA0147.namprd11.prod.outlook.com (2603:10b6:806:131::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4415.14 via Frontend Transport; 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> +       struct rockchip_sfc *sfc = dev_get_plat(bus); >         int ret; > >         if (speed > sfc->max_freq) > @@ -609,7 +609,7 @@ static int rockchip_sfc_set_speed(struct udevice *bus, > uint speed) >         } >         sfc->speed = speed; >  #else > -       dev_dbg(sfc->dev, "sfc failed, CLK not support\n", __func__); > +       dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); >  #endif >         return 0; >  } > This "works", but now I'm getting a MASSIVE performance regression. => sf test 0xc00000 0x400000 SPI flash test: 0 erase: 91154 ticks, 44 KiB/s 0.352 Mbps 1 check: 94878 ticks, 43 KiB/s 0.344 Mbps 2 write: 199305 ticks, 20 KiB/s 0.160 Mbps 3 read: 94808 ticks, 43 KiB/s 0.344 Mbps Test passed Reads used to be on the order of 5MB/s and writes, while slower, were still considerably faster. > > On 2021/8/13 3:13, Chris Morgan wrote: > > On Thu, Aug 12, 2021 at 09:15:14PM +0800, Jon Lin wrote: > > > From: Chris Morgan > > > > > > This patch adds support for the Rockchip serial flash controller > > > found on the PX30 SoC. It should work for versions 3-5 of the SFC > > > IP, however I am only able to test it on v3. > > > > > > This is adapted from the WIP SPI-MEM driver for the SFC on mainline > > > Linux. Note that the main difference between this and earlier versions > > > of the driver is that this one does not support DMA. In testing > > > the performance difference (performing a dual mode read on a 128Mb > > > chip) is negligible. DMA, if used, must also be disabled in SPL > > > mode when using A-TF anyway. > > > > > > Signed-off-by: Chris Morgan > > > Signed-off-by: Jon Lin > > > --- > > > > > I'll need to debug it further, but unfortunately this is not working > > for me. On my Odroid Go Advance I get a "Synchronous Abort" error when > > I attempt to do an "sf probe". This same sequence (boot, then do sf > > probe) has worked on all prior revisions without a crash. > > > > U-Boot TPL board init > > DDR3, 333MHz > > BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB > > out > > > > U-Boot SPL 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500) > > Trying to boot from MMC1 > > NOTICE: BL31: v2.5(release):v2.5-284-g87311b4c1 > > NOTICE: BL31: Built : 10:43:59, Aug 5 2021 > > > > > > U-Boot 2021.10-rc1+ (Aug 12 2021 - 14:03:30 -0500) > > > > Model: ODROID-GO Advance > > DRAM: 1022 MiB > > PMIC: RK8170 (on=0x80, off=0x04) > > MMC: dwmmc@ff370000: 0 > > Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... > > In: serial@ff160000 > > Out: serial@ff160000 > > Err: serial@ff160000 > > Model: ODROID-GO Advance > > Hit any key to stop autoboot: 0 > > switch to partitions #0, OK > > mmc0 is current device > > Scanning mmc 0:1... > > MMC Device 1 not found > > no mmc device at slot 1 > > starting USB... > > Bus usb@ff300000: probe failed, error -2 > > No working controllers found > > USB is stopped. Please issue 'usb start' first. > > => sf probe > > "Synchronous Abort" handler, esr 0x96000010 > > elr: 000000000022d730 lr : 000000000022d72c (reloc) > > elr: 000000003ff85730 lr : 000000003ff8572c > > x0 : 0000000000000000 x1 : 00000000066ff300 > > x2 : 000000003ff85714 x3 : 0000000000000000 > > x4 : 000000003ffccd1d x5 : 000000000000006e > > x6 : 000000003ffba6d8 x7 : 0000000000000044 > > x8 : 000000000000000a x9 : 0000000000000008 > > x10: 0000000000000034 x11: 0000000000000003 > > x12: 0000000000000000 x13: 00000000ffffffd8 > > x14: 000000003df485d0 x15: 0000000000000002 > > x16: 000000003ff8ebe8 x17: 0000000000000001 > > x18: 000000003df53dd0 x19: 00000000066ff300 > > x20: 0000000000000000 x21: 00000000066ff300 > > x22: 000000003ffbdef8 x23: 0000000000001000 > > x24: 000000003df6f530 x25: 000000003df92e90 > > x26: 000000003ffeecc0 x27: 0000000000000000 > > x28: 0000000000000003 x29: 000000003df481c0 > > > > Code: f90013f5 2a0103f5 94003427 aa0003f4 (294c0013) > > Resetting CPU ... > > > > resetting ... > > > > > > > Changes in v8: > > > - Move speed operation to set_speed logic > > > - Use read_poll > > > - Change debug to dev_dbg > > > - Simply exec_op dma logic > > > > > > Changes in v7: > > > - Make sfc-use-dma configurable > > > > > > Changes in v6: > > > - Fix dma transfer logic > > > - Fix the error of the way to wait for dma transfer finished status > > > > > > Changes in v5: > > > - Support dma transfer > > > - Add CONFIG_IS_ENABLED(CLK) limitation > > > - Support spinand devices > > > - Support SFC ver4 ver5 > > > - Using "rockchip, sfc" as compatible id > > > - Get clock from the index to compatible with those case which's > > > clock-names is not parsed > > > > > > Changes in v4: > > > - None > > > > > > Changes in v3: > > > - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux > > > driver to fix potential issue on hardware. Note I never noticed > > > this issue while testing, so I cannot test if it fixed any specific > > > issue for me. > > > - Updated of-compatible string back to "rockchip,sfc" to match what > > > is currently proposed for upstream driver. The hardware itself > > > has multiple versions but a register is present in the hardware that > > > is read by the driver to set version specific functionality. > > > - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that > > > sfc nodes match what is in upstream. > > > > > > Changes in v2: > > > - Resending due to glitch with patch file truncating final two lines > > > on patch 1/5 and incorrect patch version number on patch 5/5. > > > > > > Changes in v1: > > > - Reworked code to utilize spi-mem framework, and based it closely > > > off of work in progress code for mainline Linux. > > > - Removed DMA, as it didn't offer much performance benefit for > > > booting (in my test cases), added complexity to the code, and > > > interfered with A-TF. > > > - Updated the names of the bindings to match the work in progress > > > Linux code. > > > - Moved alias to u-boot specific device-tree for Odroid Go Advance. > > > Alias is updated with the spi0 node pointing to the SFC to > > > help the sf command as well as facilitate booting from the SFC. > > > - Note 2 below no longer applies, as rebasing this off of upstream > > > code should allow the device to work for NAND, and by utilizing > > > the spi-mem framework it no longer has to extract the parameters > > > > > > drivers/spi/Kconfig | 8 + > > > drivers/spi/Makefile | 1 + > > > drivers/spi/rockchip_sfc.c | 646 +++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 655 insertions(+) > > > create mode 100644 drivers/spi/rockchip_sfc.c > > > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > > > index 5c2a60a214..e12699bec7 100644 > > > --- a/drivers/spi/Kconfig > > > +++ b/drivers/spi/Kconfig > > > @@ -319,6 +319,14 @@ config RENESAS_RPC_SPI > > > on Renesas RCar Gen3 SoCs. This uses driver model and requires a > > > device tree binding to operate. > > > +config ROCKCHIP_SFC > > > + bool "Rockchip SFC Driver" > > > + help > > > + Enable the Rockchip SFC Driver for SPI NOR flash. This device is > > > + a limited purpose SPI controller for driving NOR flash on certain > > > + Rockchip SoCs. This uses driver model and requires a device tree > > > + binding to operate. > > > + > > > config ROCKCHIP_SPI > > > bool "Rockchip SPI driver" > > > help > > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > > > index 216e72c60f..d2f24bccef 100644 > > > --- a/drivers/spi/Makefile > > > +++ b/drivers/spi/Makefile > > > @@ -54,6 +54,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o > > > obj-$(CONFIG_SPI_QUP) += spi-qup.o > > > obj-$(CONFIG_SPI_MXIC) += spi-mxic.o > > > obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o > > > +obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o > > > obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o > > > obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o > > > obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o > > > diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c > > > new file mode 100644 > > > index 0000000000..8173724ecd > > > --- /dev/null > > > +++ b/drivers/spi/rockchip_sfc.c > > > @@ -0,0 +1,646 @@ > > > +// SPDX-License-Identifier: GPL-2.0-only > > > +/* > > > + * Rockchip Serial Flash Controller Driver > > > + * > > > + * Copyright (c) 2017-2021, Rockchip Inc. > > > + * Author: Shawn Lin > > > + * Chris Morgan > > > + * Jon Lin > > > + */ > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +/* System control */ > > > +#define SFC_CTRL 0x0 > > > +#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) > > > +#define SFC_CTRL_CMD_BITS_SHIFT 8 > > > +#define SFC_CTRL_ADDR_BITS_SHIFT 10 > > > +#define SFC_CTRL_DATA_BITS_SHIFT 12 > > > + > > > +/* Interrupt mask */ > > > +#define SFC_IMR 0x4 > > > +#define SFC_IMR_RX_FULL BIT(0) > > > +#define SFC_IMR_RX_UFLOW BIT(1) > > > +#define SFC_IMR_TX_OFLOW BIT(2) > > > +#define SFC_IMR_TX_EMPTY BIT(3) > > > +#define SFC_IMR_TRAN_FINISH BIT(4) > > > +#define SFC_IMR_BUS_ERR BIT(5) > > > +#define SFC_IMR_NSPI_ERR BIT(6) > > > +#define SFC_IMR_DMA BIT(7) > > > + > > > +/* Interrupt clear */ > > > +#define SFC_ICLR 0x8 > > > +#define SFC_ICLR_RX_FULL BIT(0) > > > +#define SFC_ICLR_RX_UFLOW BIT(1) > > > +#define SFC_ICLR_TX_OFLOW BIT(2) > > > +#define SFC_ICLR_TX_EMPTY BIT(3) > > > +#define SFC_ICLR_TRAN_FINISH BIT(4) > > > +#define SFC_ICLR_BUS_ERR BIT(5) > > > +#define SFC_ICLR_NSPI_ERR BIT(6) > > > +#define SFC_ICLR_DMA BIT(7) > > > + > > > +/* FIFO threshold level */ > > > +#define SFC_FTLR 0xc > > > +#define SFC_FTLR_TX_SHIFT 0 > > > +#define SFC_FTLR_TX_MASK 0x1f > > > +#define SFC_FTLR_RX_SHIFT 8 > > > +#define SFC_FTLR_RX_MASK 0x1f > > > + > > > +/* Reset FSM and FIFO */ > > > +#define SFC_RCVR 0x10 > > > +#define SFC_RCVR_RESET BIT(0) > > > + > > > +/* Enhanced mode */ > > > +#define SFC_AX 0x14 > > > + > > > +/* Address Bit number */ > > > +#define SFC_ABIT 0x18 > > > + > > > +/* Interrupt status */ > > > +#define SFC_ISR 0x1c > > > +#define SFC_ISR_RX_FULL_SHIFT BIT(0) > > > +#define SFC_ISR_RX_UFLOW_SHIFT BIT(1) > > > +#define SFC_ISR_TX_OFLOW_SHIFT BIT(2) > > > +#define SFC_ISR_TX_EMPTY_SHIFT BIT(3) > > > +#define SFC_ISR_TX_FINISH_SHIFT BIT(4) > > > +#define SFC_ISR_BUS_ERR_SHIFT BIT(5) > > > +#define SFC_ISR_NSPI_ERR_SHIFT BIT(6) > > > +#define SFC_ISR_DMA_SHIFT BIT(7) > > > + > > > +/* FIFO status */ > > > +#define SFC_FSR 0x20 > > > +#define SFC_FSR_TX_IS_FULL BIT(0) > > > +#define SFC_FSR_TX_IS_EMPTY BIT(1) > > > +#define SFC_FSR_RX_IS_EMPTY BIT(2) > > > +#define SFC_FSR_RX_IS_FULL BIT(3) > > > +#define SFC_FSR_TXLV_MASK GENMASK(12, 8) > > > +#define SFC_FSR_TXLV_SHIFT 8 > > > +#define SFC_FSR_RXLV_MASK GENMASK(20, 16) > > > +#define SFC_FSR_RXLV_SHIFT 16 > > > + > > > +/* FSM status */ > > > +#define SFC_SR 0x24 > > > +#define SFC_SR_IS_IDLE 0x0 > > > +#define SFC_SR_IS_BUSY 0x1 > > > + > > > +/* Raw interrupt status */ > > > +#define SFC_RISR 0x28 > > > +#define SFC_RISR_RX_FULL BIT(0) > > > +#define SFC_RISR_RX_UNDERFLOW BIT(1) > > > +#define SFC_RISR_TX_OVERFLOW BIT(2) > > > +#define SFC_RISR_TX_EMPTY BIT(3) > > > +#define SFC_RISR_TRAN_FINISH BIT(4) > > > +#define SFC_RISR_BUS_ERR BIT(5) > > > +#define SFC_RISR_NSPI_ERR BIT(6) > > > +#define SFC_RISR_DMA BIT(7) > > > + > > > +/* Version */ > > > +#define SFC_VER 0x2C > > > +#define SFC_VER_3 0x3 > > > +#define SFC_VER_4 0x4 > > > +#define SFC_VER_5 0x5 > > > + > > > +/* Delay line controller resiter */ > > > +#define SFC_DLL_CTRL0 0x3C > > > +#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) > > > +#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU > > > +#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU > > > + > > > +/* Master trigger */ > > > +#define SFC_DMA_TRIGGER 0x80 > > > +#define SFC_DMA_TRIGGER_START 1 > > > + > > > +/* Src or Dst addr for master */ > > > +#define SFC_DMA_ADDR 0x84 > > > + > > > +/* Length control register extension 32GB */ > > > +#define SFC_LEN_CTRL 0x88 > > > +#define SFC_LEN_CTRL_TRB_SEL 1 > > > +#define SFC_LEN_EXT 0x8C > > > + > > > +/* Command */ > > > +#define SFC_CMD 0x100 > > > +#define SFC_CMD_IDX_SHIFT 0 > > > +#define SFC_CMD_DUMMY_SHIFT 8 > > > +#define SFC_CMD_DIR_SHIFT 12 > > > +#define SFC_CMD_DIR_RD 0 > > > +#define SFC_CMD_DIR_WR 1 > > > +#define SFC_CMD_ADDR_SHIFT 14 > > > +#define SFC_CMD_ADDR_0BITS 0 > > > +#define SFC_CMD_ADDR_24BITS 1 > > > +#define SFC_CMD_ADDR_32BITS 2 > > > +#define SFC_CMD_ADDR_XBITS 3 > > > +#define SFC_CMD_TRAN_BYTES_SHIFT 16 > > > +#define SFC_CMD_CS_SHIFT 30 > > > + > > > +/* Address */ > > > +#define SFC_ADDR 0x104 > > > + > > > +/* Data */ > > > +#define SFC_DATA 0x108 > > > + > > > +/* The controller and documentation reports that it supports up to 4 CS > > > + * devices (0-3), however I have only been able to test a single CS (CS 0) > > > + * due to the configuration of my device. > > > + */ > > > +#define SFC_MAX_CHIPSELECT_NUM 4 > > > + > > > +/* The SFC can transfer max 16KB - 1 at one time > > > + * we set it to 15.5KB here for alignment. > > > + */ > > > +#define SFC_MAX_IOSIZE_VER3 (512 * 31) > > > + > > > +#define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) > > > + > > > +/* DMA is only enabled for large data transmission */ > > > +#define SFC_DMA_TRANS_THRETHOLD (0x40) > > > + > > > +/* Maximum clock values from datasheet suggest keeping clock value under > > > + * 150MHz. No minimum or average value is suggested. > > > + */ > > > +#define SFC_MAX_SPEED (150 * 1000 * 1000) > > > + > > > +struct rockchip_sfc { > > > + struct udevice *dev; > > > + void __iomem *regbase; > > > + struct clk hclk; > > > + struct clk clk; > > > + u32 max_freq; > > > + u32 speed; > > > + bool use_dma; > > > + u32 max_iosize; > > > + u16 version; > > > +}; > > > + > > > +static int rockchip_sfc_reset(struct rockchip_sfc *sfc) > > > +{ > > > + int err; > > > + u32 status; > > > + > > > + writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); > > > + > > > + err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, > > > + !(status & SFC_RCVR_RESET), > > > + 1000000); > > > + if (err) > > > + printf("SFC reset never finished\n"); > > > + > > > + /* Still need to clear the masked interrupt from RISR */ > > > + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); > > > + > > > + return err; > > > +} > > > + > > > +static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) > > > +{ > > > + return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); > > > +} > > > + > > > +static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) > > > +{ > > > + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) > > > + return SFC_MAX_IOSIZE_VER4; > > > + > > > + return SFC_MAX_IOSIZE_VER3; > > > +} > > > + > > > +static int rockchip_sfc_init(struct rockchip_sfc *sfc) > > > +{ > > > + writel(0, sfc->regbase + SFC_CTRL); > > > + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) > > > + writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); > > > + > > > + return 0; > > > +} > > > + > > > +static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) > > > +{ > > > + struct rockchip_sfc *sfc = dev_get_plat(bus); > > > + > > > + sfc->regbase = dev_read_addr_ptr(bus); > > > + if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) > > > + sfc->use_dma = false; > > > + else > > > + sfc->use_dma = true; > > > + > > > +#if CONFIG_IS_ENABLED(CLK) > > > + int ret; > > > + > > > + ret = clk_get_by_index(bus, 0, &sfc->clk); > > > + if (ret < 0) { > > > + printf("Could not get clock for %s: %d\n", bus->name, ret); > > > + return ret; > > > + } > > > + > > > + ret = clk_get_by_index(bus, 1, &sfc->hclk); > > > + if (ret < 0) { > > > + printf("Could not get ahb clock for %s: %d\n", bus->name, ret); > > > + return ret; > > > + } > > > +#endif > > > + > > > + return 0; > > > +} > > > + > > > +static int rockchip_sfc_probe(struct udevice *bus) > > > +{ > > > + struct rockchip_sfc *sfc = dev_get_plat(bus); > > > + int ret; > > > + > > > +#if CONFIG_IS_ENABLED(CLK) > > > + ret = clk_enable(&sfc->hclk); > > > + if (ret) > > > + dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); > > > + > > > + ret = clk_enable(&sfc->clk); > > > + if (ret) > > > + dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); > > > +#endif > > > + > > > + ret = rockchip_sfc_init(sfc); > > > + if (ret) > > > + goto err_init; > > > + > > > + sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); > > > + sfc->version = rockchip_sfc_get_version(sfc); > > > + sfc->max_freq = SFC_MAX_SPEED; > > > + sfc->dev = bus; > > > + > > > + return 0; > > > + > > > +err_init: > > > +#if CONFIG_IS_ENABLED(CLK) > > > + clk_disable(&sfc->clk); > > > + clk_disable(&sfc->hclk); > > > +#endif > > > + > > > + return ret; > > > +} > > > + > > > +static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) > > > +{ > > > + int ret = 0; > > > + u32 status; > > > + > > > + ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, > > > + status & SFC_FSR_TXLV_MASK, > > > + timeout_us); > > > + if (ret) { > > > + dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); > > > + > > > + ret = -ETIMEDOUT; > > > + } > > > + > > > + return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; > > > +} > > > + > > > +static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) > > > +{ > > > + int ret = 0; > > > + u32 status; > > > + > > > + ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, > > > + status & SFC_FSR_RXLV_MASK, > > > + timeout_us); > > > + if (ret) { > > > + dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); > > > + > > > + ret = -ETIMEDOUT; > > > + } > > > + > > > + return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; > > > +} > > > + > > > +static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) > > > +{ > > > + if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { > > > + /* > > > + * SFC not support output DUMMY cycles right after CMD cycles, so > > > + * treat it as ADDR cycles. > > > + */ > > > + op->addr.nbytes = op->dummy.nbytes; > > > + op->addr.buswidth = op->dummy.buswidth; > > > + op->addr.val = 0xFFFFFFFFF; > > > + > > > + op->dummy.nbytes = 0; > > > + } > > > +} > > > + > > > +static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) > > > +{ > > > + unsigned long tbase; > > > + > > > + /* Wait for the DMA interrupt status */ > > > + tbase = get_timer(0); > > > + while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { > > > + if (get_timer(tbase) > timeout) { > > > + printf("dma timeout\n"); > > > + rockchip_sfc_reset(sfc); > > > + > > > + return -ETIMEDOUT; > > > + } > > > + > > > + udelay(1); > > > + } > > > + > > > + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); > > > + > > > + return 0; > > > +} > > > + > > > +static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, > > > + struct spi_slave *mem, > > > + const struct spi_mem_op *op, > > > + u32 len) > > > +{ > > > + struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev); > > > + u32 ctrl = 0, cmd = 0; > > > + > > > + /* set CMD */ > > > + cmd = op->cmd.opcode; > > > + ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); > > > + > > > + /* set ADDR */ > > > + if (op->addr.nbytes) { > > > + if (op->addr.nbytes == 4) { > > > + cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; > > > + } else if (op->addr.nbytes == 3) { > > > + cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; > > > + } else { > > > + cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; > > > + writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); > > > + } > > > + > > > + ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); > > > + } > > > + > > > + /* set DUMMY */ > > > + if (op->dummy.nbytes) { > > > + if (op->dummy.buswidth == 4) > > > + cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; > > > + else if (op->dummy.buswidth == 2) > > > + cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; > > > + else > > > + cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; > > > + } > > > + > > > + /* set DATA */ > > > + if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ > > > + writel(len, sfc->regbase + SFC_LEN_EXT); > > > + else > > > + cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; > > > + if (len) { > > > + if (op->data.dir == SPI_MEM_DATA_OUT) > > > + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; > > > + > > > + ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); > > > + } > > > + if (!len && op->addr.nbytes) > > > + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; > > > + > > > + /* set the Controller */ > > > + ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; > > > + cmd |= plat->cs << SFC_CMD_CS_SHIFT; > > > + > > > + dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", > > > + op->addr.nbytes, op->addr.buswidth, > > > + op->dummy.nbytes, op->dummy.buswidth); > > > + dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", > > > + ctrl, cmd, op->addr.val, len); > > > + > > > + writel(ctrl, sfc->regbase + SFC_CTRL); > > > + writel(cmd, sfc->regbase + SFC_CMD); > > > + if (op->addr.nbytes) > > > + writel(op->addr.val, sfc->regbase + SFC_ADDR); > > > + > > > + return 0; > > > +} > > > + > > > +static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) > > > +{ > > > + u8 bytes = len & 0x3; > > > + u32 dwords; > > > + int tx_level; > > > + u32 write_words; > > > + u32 tmp = 0; > > > + > > > + dwords = len >> 2; > > > + while (dwords) { > > > + tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); > > > + if (tx_level < 0) > > > + return tx_level; > > > + write_words = min_t(u32, tx_level, dwords); > > > + writesl(sfc->regbase + SFC_DATA, buf, write_words); > > > + buf += write_words << 2; > > > + dwords -= write_words; > > > + } > > > + > > > + /* write the rest non word aligned bytes */ > > > + if (bytes) { > > > + tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); > > > + if (tx_level < 0) > > > + return tx_level; > > > + memcpy(&tmp, buf, bytes); > > > + writel(tmp, sfc->regbase + SFC_DATA); > > > + } > > > + > > > + return len; > > > +} > > > + > > > +static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) > > > +{ > > > + u8 bytes = len & 0x3; > > > + u32 dwords; > > > + u8 read_words; > > > + int rx_level; > > > + int tmp; > > > + > > > + /* word aligned access only */ > > > + dwords = len >> 2; > > > + while (dwords) { > > > + rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); > > > + if (rx_level < 0) > > > + return rx_level; > > > + read_words = min_t(u32, rx_level, dwords); > > > + readsl(sfc->regbase + SFC_DATA, buf, read_words); > > > + buf += read_words << 2; > > > + dwords -= read_words; > > > + } > > > + > > > + /* read the rest non word aligned bytes */ > > > + if (bytes) { > > > + rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); > > > + if (rx_level < 0) > > > + return rx_level; > > > + tmp = readl(sfc->regbase + SFC_DATA); > > > + memcpy(buf, &tmp, bytes); > > > + } > > > + > > > + return len; > > > +} > > > + > > > +static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) > > > +{ > > > + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); > > > + writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); > > > + writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); > > > + > > > + return len; > > > +} > > > + > > > +static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, > > > + const struct spi_mem_op *op, u32 len) > > > +{ > > > + dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); > > > + > > > + if (op->data.dir == SPI_MEM_DATA_OUT) > > > + return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); > > > + else > > > + return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); > > > +} > > > + > > > +static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, > > > + const struct spi_mem_op *op, u32 len) > > > +{ > > > + struct bounce_buffer bb; > > > + unsigned int bb_flags; > > > + void *dma_buf; > > > + int ret; > > > + > > > + dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); > > > + > > > + if (op->data.dir == SPI_MEM_DATA_OUT) { > > > + dma_buf = (void *)op->data.buf.out; > > > + bb_flags = GEN_BB_READ; > > > + } else { > > > + dma_buf = (void *)op->data.buf.in; > > > + bb_flags = GEN_BB_WRITE; > > > + } > > > + > > > + ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); > > > + if (ret) > > > + return ret; > > > + > > > + ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); > > > + rockchip_sfc_wait_for_dma_finished(sfc, len * 10); > > > + bounce_buffer_stop(&bb); > > > + > > > + return ret; > > > +} > > > + > > > +static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) > > > +{ > > > + int ret = 0; > > > + u32 status; > > > + > > > + ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, > > > + !(status & SFC_SR_IS_BUSY), > > > + timeout_us); > > > + if (ret) { > > > + dev_err(sfc->dev, "wait sfc idle timeout\n"); > > > + rockchip_sfc_reset(sfc); > > > + > > > + ret = -EIO; > > > + } > > > + > > > + return ret; > > > +} > > > + > > > +static int rockchip_sfc_exec_op(struct spi_slave *mem, > > > + const struct spi_mem_op *op) > > > +{ > > > + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent); > > > + u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); > > > + int ret; > > > + > > > + rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); > > > + rockchip_sfc_xfer_setup(sfc, mem, op, len); > > > + if (len) { > > > + if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) > > > + ret = rockchip_sfc_xfer_data_dma(sfc, op, len); > > > + else > > > + ret = rockchip_sfc_xfer_data_poll(sfc, op, len); > > > + > > > + if (ret != len) { > > > + dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); > > > + > > > + return -EIO; > > > + } > > > + } > > > + > > > + return rockchip_sfc_xfer_done(sfc, 100000); > > > +} > > > + > > > +static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) > > > +{ > > > + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent); > > > + > > > + op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); > > > + > > > + return 0; > > > +} > > > + > > > +static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) > > > +{ > > > + struct rockchip_sfc *sfc = dev_get_priv(bus); > > > + int ret; > > > + > > > + if (speed > sfc->max_freq) > > > + speed = sfc->max_freq; > > > + > > > + if (speed == sfc->speed) > > > + return 0; > > > + > > > +#if CONFIG_IS_ENABLED(CLK) > > > + ret = clk_set_rate(&sfc->clk, speed); > > > + if (ret < 0) { > > > + dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", > > > + speed); > > > + return ret; > > > + } > > > + sfc->speed = speed; > > > +#else > > > + dev_dbg(sfc->dev, "sfc failed, CLK not support\n", __func__); > > > +#endif > > > + return 0; > > > +} > > > + > > > +static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) > > > +{ > > > + return 0; > > > +} > > > + > > > +static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { > > > + .adjust_op_size = rockchip_sfc_adjust_op_size, > > > + .exec_op = rockchip_sfc_exec_op, > > > +}; > > > + > > > +static const struct dm_spi_ops rockchip_sfc_ops = { > > > + .mem_ops = &rockchip_sfc_mem_ops, > > > + .set_speed = rockchip_sfc_set_speed, > > > + .set_mode = rockchip_sfc_set_mode, > > > +}; > > > + > > > +static const struct udevice_id rockchip_sfc_ids[] = { > > > + { .compatible = "rockchip,sfc"}, > > > + {}, > > > +}; > > > + > > > +U_BOOT_DRIVER(rockchip_sfc_driver) = { > > > + .name = "rockchip_sfc", > > > + .id = UCLASS_SPI, > > > + .of_match = rockchip_sfc_ids, > > > + .ops = &rockchip_sfc_ops, > > > + .of_to_plat = rockchip_sfc_ofdata_to_platdata, > > > + .plat_auto = sizeof(struct rockchip_sfc), > > > + .probe = rockchip_sfc_probe, > > > +}; > > > -- > > > 2.17.1 > > > > > > > > > > > > > > >