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x-microsoft-antispam-message-info: wi/n1e2gE/x4aK2zLZDmSG6NV8tAz0PPXpcQTVs6c1e7snSn/Mcuy5bQwZIha7SuZfTdb4GFsre/Q8kdeTS8AnB7++Fv6UMAkotOmYOEychpM6lA/jP/GofpqBih8dBcRvlk9V/1cDeyZDn1c4CaWsh+2iz5HTPVrHIchUdjPK9saxSI8xS7dQhSXsbW1f411Uijoe55iauAZdzprCBpA+78W3Ko6gyoOPMpLDuN/bHc2q36Yv/Zq6cmlRDRlsTdXLOZ3ehriJ87j2GlWclo3g3G5OtOsxs4N2vZ7SuuRgHpQb4sFusAIAnPRQEVi1JLT9dGOVqFahWid92NfP+f89kuTUpDwIXjkJaS3Gj/V2X3BLj/dMtkwK6qWTOp17B9I3d9KB4XVzU8G3BavVRiTNLU4cDyndtlMBz97FwQT3N49NyYzaDsxXiaHIj8McE/O25zfa6bi5yyNItIQqjbHJq8gjRfmUwT+SOmJb87HuUE9rMNMXdO0lwXn7nkcTFL x-ms-exchange-antispam-messagedata: NSlDF8MTa5G0A2zH9gaVZVtjSdFkrJNROObwig9dvbfYDPEuCta8RdHvmjyh/R7zsNnzek7C5ki+XoDtkiMrUeItKrc9qP/aTO5L/XJ2UcqMJEhX44wR2oTuxJf0wD1uOmXGkCBtZypa62suIqxLtg== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c1fe7161-e71a-4c82-82ce-08d7cf5efc5a X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Mar 2020 19:18:36.2231 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /oxCxSqw2jhmQfSUsrhpARg50hj1UdQvJBjR8ZR5cP4yGoUUXIFN/aozKNy9Mct1waNTYpLaP4A/TLX4BeuiztVdk7cZQ+RMB3RYfnIntbs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB3198 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 06/12] ipsec: optimize with c11 atomic for sa outbound sqn update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Honnappa Nagarahalli > Sent: Monday, March 23, 2020 7:08 PM > To: Ananyev, Konstantin ; Phil Yang ; thomas@monjalon.net; Van Haaren, Harry > ; stephen@networkplumber.org; maxime.coquelin= @redhat.com; dev@dpdk.org; Richardson, Bruce > > Cc: david.marchand@redhat.com; jerinj@marvell.com; hemant.agrawal@nxp.com= ; Gavin Hu ; Ruifeng Wang > ; Joyce Kong ; nd ;= Honnappa Nagarahalli > ; nd > Subject: RE: [PATCH v3 06/12] ipsec: optimize with c11 atomic for sa outb= ound sqn update >=20 > >=20 > > Subject: RE: [PATCH v3 06/12] ipsec: optimize with c11 atomic for sa ou= tbound > > sqn update > > > > Hi Phil, > > > > > > > > For SA outbound packets, rte_atomic64_add_return is used to generate > > > SQN atomically. This introduced an unnecessary full barrier by callin= g > > > the '__sync' builtin implemented rte_atomic_XX API on aarch64. This > > > patch optimized it with c11 atomic and eliminated the expensive > > > barrier for aarch64. > > > > > > Signed-off-by: Phil Yang > > > Reviewed-by: Ruifeng Wang > > > Reviewed-by: Gavin Hu > > > --- > > > lib/librte_ipsec/ipsec_sqn.h | 3 ++- > > > lib/librte_ipsec/sa.h | 2 +- > > > 2 files changed, 3 insertions(+), 2 deletions(-) > > > > > > diff --git a/lib/librte_ipsec/ipsec_sqn.h > > > b/lib/librte_ipsec/ipsec_sqn.h index 0c2f76a..e884af7 100644 > > > --- a/lib/librte_ipsec/ipsec_sqn.h > > > +++ b/lib/librte_ipsec/ipsec_sqn.h > > > @@ -128,7 +128,8 @@ esn_outb_update_sqn(struct rte_ipsec_sa *sa, > > > uint32_t *num) > > > > > > n =3D *num; > > > if (SQN_ATOMIC(sa)) > > > - sqn =3D (uint64_t)rte_atomic64_add_return(&sa- > > >sqn.outb.atom, n); > > > + sqn =3D __atomic_add_fetch(&sa->sqn.outb.atom, n, > > > + __ATOMIC_RELAXED); > > > > One generic thing to note: > > clang for i686 in some cases will generate a proper function call for 6= 4-bit > > __atomic builtins (gcc seems to always generate cmpxchng8b for such cas= es). > > Does anyone consider it as a potential problem? > > It probably not a big deal, but would like to know broader opinion. > I had looked at this some time back for GCC. The function call is generat= ed only if the underlying platform does not support the atomic > instructions for the operand size. Otherwise, gcc generates the instructi= ons directly. > I would think the behavior would be the same for clang. >From what I see not really. As an example: $ cat tatm11.c #include struct x { uint64_t v __attribute__((aligned(8))); }; uint64_t ffxadd1(struct x *x, uint32_t n, uint32_t m) { return __atomic_add_fetch(&x->v, n, __ATOMIC_RELAXED); } uint64_t ffxadd11(uint64_t *v, uint32_t n, uint32_t m) { return __atomic_add_fetch(v, n, __ATOMIC_RELAXED); } gcc for i686 will generate code with cmpxchng8b for both cases. clang will generate cmpxchng8b for ffxadd1() - when data is explicitly 8B a= ligned, but will emit a function call for ffxadd11(). >=20 > > > > > else { > > > sqn =3D sa->sqn.outb.raw + n; > > > sa->sqn.outb.raw =3D sqn; > > > diff --git a/lib/librte_ipsec/sa.h b/lib/librte_ipsec/sa.h index > > > d22451b..cab9a2e 100644 > > > --- a/lib/librte_ipsec/sa.h > > > +++ b/lib/librte_ipsec/sa.h > > > @@ -120,7 +120,7 @@ struct rte_ipsec_sa { > > > */ > > > union { > > > union { > > > - rte_atomic64_t atom; > > > + uint64_t atom; > > > uint64_t raw; > > > } outb; > > > > If we don't need rte_atomic64 here anymore, then I think we can collaps= e the > > union to just: > > uint64_t outb; > > > > > struct { > > > -- > > > 2.7.4