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Wed, 5 Jun 2019 08:31:35 +0000 From: Fabrizio Castro To: Wolfram Sang , "linux-mmc@vger.kernel.org" , Geert Uytterhoeven CC: "linux-renesas-soc@vger.kernel.org" , Yoshihiro Shimoda , =?iso-8859-1?Q?Niklas_S=F6derlund?= Subject: RE: [PATCH 1/3] mmc: sdhi: disallow HS400 for M3-W ES1.2 and V3H Thread-Topic: [PATCH 1/3] mmc: sdhi: disallow HS400 for M3-W ES1.2 and V3H Thread-Index: AQHVGuhhkZx8vUr4TEOB9YONHKQ2K6aMuj8Q Date: Wed, 5 Jun 2019 08:31:35 +0000 Message-ID: References: <20190604151530.7023-1-wsa+renesas@sang-engineering.com> <20190604151530.7023-2-wsa+renesas@sang-engineering.com> In-Reply-To: <20190604151530.7023-2-wsa+renesas@sang-engineering.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=fabrizio.castro@bp.renesas.com; x-originating-ip: [193.141.220.21] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d6f6490e-544d-4d8a-9278-08d6e990389f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:TY1PR01MB1580; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-Network-Message-Id: d6f6490e-544d-4d8a-9278-08d6e990389f X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Jun 2019 08:31:35.1419 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fabrizio.castro@bp.renesas.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY1PR01MB1580 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hello Wolfram, Thank you for your patch! > From: linux-renesas-soc-owner@vger.kernel.org On Behalf Of Wolfram Sang > Sent: 04 June 2019 16:15 > Subject: [PATCH 1/3] mmc: sdhi: disallow HS400 for M3-W ES1.2 and V3H >=20 > Our HW engineers informed us that HS400 is not working on these SoC > revisions. >=20 > Fixes: 0f4e2054c971 ("mmc: renesas_sdhi: disable HS400 on H3 ES1.x and M3= -W ES1.[012]") > Signed-off-by: Wolfram Sang > --- >=20 > This one should go back to stable. >=20 > drivers/mmc/host/renesas_sdhi_core.c | 6 ++++++ > 1 file changed, 6 insertions(+) >=20 > diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/rene= sas_sdhi_core.c > index db73f9f1b186..e98ba6cf6c13 100644 > --- a/drivers/mmc/host/renesas_sdhi_core.c > +++ b/drivers/mmc/host/renesas_sdhi_core.c > @@ -620,11 +620,17 @@ static const struct renesas_sdhi_quirks sdhi_quirks= _h3_es2 =3D { > .hs400_4taps =3D true, > }; >=20 > +static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 =3D { > + .hs400_disabled =3D true, > +}; > + > static const struct soc_device_attribute sdhi_quirks_match[] =3D { > { .soc_id =3D "r8a7795", .revision =3D "ES1.*", .data =3D &sdhi_quirks_= h3_m3w_es1 }, > { .soc_id =3D "r8a7795", .revision =3D "ES2.0", .data =3D &sdhi_quirks_= h3_es2 }, > { .soc_id =3D "r8a7796", .revision =3D "ES1.0", .data =3D &sdhi_quirks_= h3_m3w_es1 }, > { .soc_id =3D "r8a7796", .revision =3D "ES1.1", .data =3D &sdhi_quirks_= h3_m3w_es1 }, > + { .soc_id =3D "r8a7796", .revision =3D "ES1.2", .data =3D &sdhi_quirks_= h3_m3w_es1 }, Can we actually detect E1.2 on the M3-W? My understanding is that the conte= nt of the PRR is the same for 1.1 and 1.2 (Geert, could you please jump in?). I am saying this because I am using an RZ/G2M (r8a774a1), revision 1.2, tha= t it's reporting itself as 1.1. Also, the r8a774a1 and r8a7796 are identical (even revision-wise), so I gue= ss we could add r8a774a1 to the pile while at it? Thanks, Fab > + { .soc_id =3D "r8a77980", .data =3D &sdhi_quirks_nohs400 }, > { /* Sentinel. */ }, > }; >=20 > -- > 2.11.0