* [PATCH 0/2] clk: renesas: Add support for R-Car E3
@ 2018-04-11 9:37 Yoshihiro Shimoda
2018-04-11 9:37 ` [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions Yoshihiro Shimoda
2018-04-11 9:37 ` [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3 Yoshihiro Shimoda
0 siblings, 2 replies; 11+ messages in thread
From: Yoshihiro Shimoda @ 2018-04-11 9:37 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, geert+renesas,
linux-clk, devicetree
Cc: linux-renesas-soc, Yoshihiro Shimoda
This patch is based on the renesas-drivers-2018-04-03-v4.16 tag of
renesas-drivers.git.
Takeshi Kihara (1):
clk: renesas: Add r8a77990 CPG Core Clock Definitions
Yoshihiro Shimoda (1):
clk: renesas: cpg-mssr: Add support for R-Car E3
.../devicetree/bindings/clock/renesas,cpg-mssr.txt | 3 +-
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a77990-cpg-mssr.c | 291 +++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
include/dt-bindings/clock/r8a77990-cpg-mssr.h | 63 +++++
7 files changed, 369 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/renesas/r8a77990-cpg-mssr.c
create mode 100644 include/dt-bindings/clock/r8a77990-cpg-mssr.h
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions
2018-04-11 9:37 [PATCH 0/2] clk: renesas: Add support for R-Car E3 Yoshihiro Shimoda
@ 2018-04-11 9:37 ` Yoshihiro Shimoda
2018-04-12 12:23 ` Geert Uytterhoeven
2018-04-11 9:37 ` [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3 Yoshihiro Shimoda
1 sibling, 1 reply; 11+ messages in thread
From: Yoshihiro Shimoda @ 2018-04-11 9:37 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, geert+renesas,
linux-clk, devicetree
Cc: linux-renesas-soc, Takeshi Kihara, Yoshihiro Shimoda
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs.
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC) are not included,
as they are used as internal clock sources only, and never referenced
from DT.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[shimoda: add SPDX-License-Identifier]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
include/dt-bindings/clock/r8a77990-cpg-mssr.h | 63 +++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a77990-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
new file mode 100644
index 0000000..c806fce
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77990 CPG Core Clocks */
+#define R8A77990_CLK_Z2 0
+#define R8A77990_CLK_ZR 1
+#define R8A77990_CLK_ZG 2
+#define R8A77990_CLK_ZTR 3
+#define R8A77990_CLK_ZT 4
+#define R8A77990_CLK_ZX 5
+#define R8A77990_CLK_S0D1 6
+#define R8A77990_CLK_S0D3 7
+#define R8A77990_CLK_S0D6 8
+#define R8A77990_CLK_S0D12 9
+#define R8A77990_CLK_S0D24 10
+#define R8A77990_CLK_S1D1 11
+#define R8A77990_CLK_S1D2 12
+#define R8A77990_CLK_S1D4 13
+#define R8A77990_CLK_S2D1 14
+#define R8A77990_CLK_S2D2 15
+#define R8A77990_CLK_S2D4 16
+#define R8A77990_CLK_S3D1 17
+#define R8A77990_CLK_S3D2 18
+#define R8A77990_CLK_S3D4 19
+#define R8A77990_CLK_S0D6C 20
+#define R8A77990_CLK_S3D1C 21
+#define R8A77990_CLK_S3D2C 22
+#define R8A77990_CLK_S3D4C 23
+#define R8A77990_CLK_LB 24
+#define R8A77990_CLK_CL 25
+#define R8A77990_CLK_ZB3 26
+#define R8A77990_CLK_ZB3D2 27
+#define R8A77990_CLK_CR 28
+#define R8A77990_CLK_CRD2 29
+#define R8A77990_CLK_SD0H 30
+#define R8A77990_CLK_SD0 31
+#define R8A77990_CLK_SD1H 32
+#define R8A77990_CLK_SD1 33
+#define R8A77990_CLK_SD3H 34
+#define R8A77990_CLK_SD3 35
+#define R8A77990_CLK_RPC 36
+#define R8A77990_CLK_RPCD2 37
+#define R8A77990_CLK_ZA2 38
+#define R8A77990_CLK_ZA8 39
+#define R8A77990_CLK_Z2D 40
+#define R8A77990_CLK_CANFD 41
+#define R8A77990_CLK_MSO 42
+#define R8A77990_CLK_R 43
+#define R8A77990_CLK_OSC 44
+#define R8A77990_CLK_LV0 45
+#define R8A77990_CLK_LV1 46
+#define R8A77990_CLK_CSI0 47
+#define R8A77990_CLK_POST3 48
+#define R8A77990_CLK_CP 49
+#define R8A77990_CLK_CPEX 50
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3
2018-04-11 9:37 [PATCH 0/2] clk: renesas: Add support for R-Car E3 Yoshihiro Shimoda
2018-04-11 9:37 ` [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions Yoshihiro Shimoda
@ 2018-04-11 9:37 ` Yoshihiro Shimoda
2018-04-13 10:36 ` Geert Uytterhoeven
1 sibling, 1 reply; 11+ messages in thread
From: Yoshihiro Shimoda @ 2018-04-11 9:37 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, geert+renesas,
linux-clk, devicetree
Cc: linux-renesas-soc, Yoshihiro Shimoda
Initial support for R-Car E3 (r8a77990), including core and module
clocks.
Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual:
Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018".
Inspried by patches by Takeshi Kihara in the BSP.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
.../devicetree/bindings/clock/renesas,cpg-mssr.txt | 3 +-
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a77990-cpg-mssr.c | 291 +++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
6 files changed, 306 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/renesas/r8a77990-cpg-mssr.c
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index c3473df..26b7bae 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -26,6 +26,7 @@ Required Properties:
- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
+ - "renesas,r8a77990-cpg-mssr" for the r8a77995 SoC (R-Car E3)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -36,7 +37,7 @@ Required Properties:
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
- r8a77980, r8a77995)
+ r8a77980, r8a77990, r8a77995)
- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
r8a7794)
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index f32896fa..f9ba71311 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -19,6 +19,7 @@ config CLK_RENESAS
select CLK_R8A77965 if ARCH_R8A77965
select CLK_R8A77970 if ARCH_R8A77970
select CLK_R8A77980 if ARCH_R8A77980
+ select CLK_R8A77990 if ARCH_R8A77990
select CLK_R8A77995 if ARCH_R8A77995
select CLK_SH73A0 if ARCH_SH73A0
@@ -116,6 +117,10 @@ config CLK_R8A77980
bool "R-Car V3H clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
+config CLK_R8A77990
+ bool "R-Car E3 clock support" if COMPILE_TEST
+ select CLK_RCAR_GEN3_CPG
+
config CLK_R8A77995
bool "R-Car D3 clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index a4edea9..fe5bac9 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
new file mode 100644
index 0000000..d345458
--- /dev/null
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL0D4,
+ CLK_PLL0D6,
+ CLK_PLL0D8,
+ CLK_PLL0D20,
+ CLK_PLL0D24,
+ CLK_PLL1D2,
+ CLK_PE,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
+ DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
+ DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
+ DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
+ DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
+ DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
+ DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
+ DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
+ DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
+ DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
+ DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1),
+ DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1),
+ DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074),
+ DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
+ DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
+
+ DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
+ DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1),
+ DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1),
+
+ DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6),
+ DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
+ DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
+ DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
+
+ DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
+ DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
+ DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
+};
+
+static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
+ DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
+ DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
+ DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
+ DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C),
+ DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C),
+ DEF_MOD("msiof3", 208, R8A77990_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77990_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77990_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77990_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
+ DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
+
+ DEF_MOD("cmt3", 300, R8A77990_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77990_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77990_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77990_CLK_R),
+ DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C),
+ DEF_MOD("sdif3", 311, R8A77990_CLK_SD3),
+ DEF_MOD("sdif1", 313, R8A77990_CLK_SD1),
+ DEF_MOD("sdif0", 314, R8A77990_CLK_SD0),
+ DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1),
+ DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1),
+ DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1),
+
+ DEF_MOD("rwdt", 402, R8A77990_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
+
+ DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
+ DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
+ DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
+ DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
+ DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
+ DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
+ DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
+ DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
+ DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
+ DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
+ DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
+ DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
+ DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C),
+ DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C),
+ DEF_MOD("thermal", 522, R8A77990_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C),
+
+ DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2),
+ DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2),
+ DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1),
+ DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1),
+ DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1),
+ DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1),
+ DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2),
+ DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2),
+ DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
+ DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
+
+ DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
+ DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
+ DEF_MOD("du1", 723, R8A77990_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A77990_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
+
+ DEF_MOD("vin7", 804, R8A77990_CLK_S1D2),
+ DEF_MOD("vin6", 805, R8A77990_CLK_S1D2),
+ DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
+ DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
+ DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
+
+ DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
+ DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
+ DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
+ DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
+ DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2),
+ DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2),
+ DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
+
+ DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+};
+
+static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-AP (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
+ *--------------------------------------------------------------------
+ * 0 48 x 1 x100/4 x100/3 x100/3
+ * 1 48 x 1 x100/4 x100/3 x58/3
+ */
+#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div */
+ { 1, 100, 3, 100, 3, },
+ { 1, 100, 3, 58, 3, },
+};
+
+static int __init r8a77990_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a77990_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a77990_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a77990_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a77990_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a77990_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen3_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 2c467f9..49e5106 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -717,6 +717,12 @@ static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
.data = &r8a77980_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_CLK_R8A77990
+ {
+ .compatible = "renesas,r8a77990-cpg-mssr",
+ .data = &r8a77990_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A77995
{
.compatible = "renesas,r8a77995-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index efe2a14..642f720 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -143,6 +143,7 @@ struct cpg_mssr_info {
extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions
2018-04-11 9:37 ` [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions Yoshihiro Shimoda
@ 2018-04-12 12:23 ` Geert Uytterhoeven
2018-04-13 2:16 ` Yoshihiro Shimoda
0 siblings, 1 reply; 11+ messages in thread
From: Geert Uytterhoeven @ 2018-04-12 12:23 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Geert Uytterhoeven, linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas, Takeshi Kihara
Hi Shimoda-san,
On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs.
>
> Note that internal CPG clocks (S0, S1, S2, S3, SDSRC) are not included,
> as they are used as internal clock sources only, and never referenced
> from DT.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [shimoda: add SPDX-License-Identifier]
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a77990 CPG Core Clocks */
[...]
> +#define R8A77990_CLK_CSI0 47
Note that CSI0 is not listed in Table 8.2g ("R-Car E3").
Probably it does exist, given:
- Table 8.11 ("Register Configuration") says CSI0CKCR exists on R-Car E3,
- Figure 25.6 ("CSI2 Block Diagram (R-Car E3)") shows CSI0.
> +#define R8A77990_CLK_POST3 48
I noticed these POSTx clocks have been added to all R-Car Gen3 clock tables.
It doesn't look like we will ever need to refer them from DT, so I think we
can treat them as internal clocks, and omit them from the DT bindings.
What do you think?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions
2018-04-12 12:23 ` Geert Uytterhoeven
2018-04-13 2:16 ` Yoshihiro Shimoda
@ 2018-04-13 2:16 ` Yoshihiro Shimoda
0 siblings, 0 replies; 11+ messages in thread
From: Yoshihiro Shimoda @ 2018-04-13 2:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Geert Uytterhoeven, linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
<devicetree@vger.kernel.org>,
Linux-Renesas, TAKESHI KIHARA
Hi Geert-san,
Thank you for the review!
> From: Geert Uytterhoeven, Sent: Thursday, April 12, 2018 9:23 PM
>
> Hi Shimoda-san,
>
> On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
<snip>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
> > @@ -0,0 +1,63 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> > +#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* r8a77990 CPG Core Clocks */
>
> [...]
>
> > +#define R8A77990_CLK_CSI0 47
>
> Note that CSI0 is not listed in Table 8.2g ("R-Car E3").
> Probably it does exist, given:
> - Table 8.11 ("Register Configuration") says CSI0CKCR exists on R-Car E3,
> - Figure 25.6 ("CSI2 Block Diagram (R-Car E3)") shows CSI0.
I think so. I'm asking HW team about missing CSI0 in Table 8.2g now.
> > +#define R8A77990_CLK_POST3 48
>
> I noticed these POSTx clocks have been added to all R-Car Gen3 clock tables.
> It doesn't look like we will ever need to refer them from DT, so I think we
> can treat them as internal clocks, and omit them from the DT bindings.
>
> What do you think?
I agree with you. So, I will omit POSTx clocks from the DT bindings in v2 patch.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions
@ 2018-04-13 2:16 ` Yoshihiro Shimoda
0 siblings, 0 replies; 11+ messages in thread
From: Yoshihiro Shimoda @ 2018-04-13 2:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Geert Uytterhoeven, linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas, TAKESHI KIHARA
Hi Geert-san,
Thank you for the review!
> From: Geert Uytterhoeven, Sent: Thursday, April 12, 2018 9:23 PM
>
> Hi Shimoda-san,
>
> On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
<snip>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
> > @@ -0,0 +1,63 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> > +#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* r8a77990 CPG Core Clocks */
>
> [...]
>
> > +#define R8A77990_CLK_CSI0 47
>
> Note that CSI0 is not listed in Table 8.2g ("R-Car E3").
> Probably it does exist, given:
> - Table 8.11 ("Register Configuration") says CSI0CKCR exists on R-Car E3,
> - Figure 25.6 ("CSI2 Block Diagram (R-Car E3)") shows CSI0.
I think so. I'm asking HW team about missing CSI0 in Table 8.2g now.
> > +#define R8A77990_CLK_POST3 48
>
> I noticed these POSTx clocks have been added to all R-Car Gen3 clock tables.
> It doesn't look like we will ever need to refer them from DT, so I think we
> can treat them as internal clocks, and omit them from the DT bindings.
>
> What do you think?
I agree with you. So, I will omit POSTx clocks from the DT bindings in v2 patch.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions
@ 2018-04-13 2:16 ` Yoshihiro Shimoda
0 siblings, 0 replies; 11+ messages in thread
From: Yoshihiro Shimoda @ 2018-04-13 2:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Geert Uytterhoeven, linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas, TAKESHI KIHARA
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aW5rPw0KDQpJIGFncmVlIHdpdGggeW91LiBTbywgSSB3aWxsIG9taXQgUE9TVHggY2xvY2tzIGZy
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cm8gU2hpbW9kYQ0KDQo=
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3
2018-04-11 9:37 ` [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3 Yoshihiro Shimoda
@ 2018-04-13 10:36 ` Geert Uytterhoeven
2018-04-18 8:46 ` Yoshihiro Shimoda
0 siblings, 1 reply; 11+ messages in thread
From: Geert Uytterhoeven @ 2018-04-13 10:36 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Geert Uytterhoeven, linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
Hi Shimoda-san,
On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Initial support for R-Car E3 (r8a77990), including core and module
> clocks.
>
> Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual:
> Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018".
>
> Inspried by patches by Takeshi Kihara in the BSP.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
> @@ -26,6 +26,7 @@ Required Properties:
> - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
> - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
> - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
> + - "renesas,r8a77990-cpg-mssr" for the r8a77995 SoC (R-Car E3)
r8a77990 SoC
> - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
> --- /dev/null
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -0,0 +1,291 @@
> +static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
> + /* Core Clock Outputs */
> + DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6),
... CLK_PE, 2),
> + DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
> + DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
> + DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
> +
> + DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
I cannot confirm the parent, as Section 8.2.18 ("CAN-FD Clock Frequency
Control Register (CANFDCKCR)") does not specify the source clock frequency
for R-Car E3 (unlike for D3). But 800 MHz sounds sane.
> + DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
I cannot confirm the parent clock, as CSI0 is not documented.
But given PLL1 runs at 1.6 GHz, PLL1/2 is consistent with PLL1/4 on other
R-Car Gen3 SoCs with a faster PLL1 (3.2 GHz).
> +static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
> + DEF_MOD("vin7", 804, R8A77990_CLK_S1D2),
> + DEF_MOD("vin6", 805, R8A77990_CLK_S1D2),
Vin6/7 have been removed in the Feb. errata.
With the above fixed/confirmed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3
2018-04-13 10:36 ` Geert Uytterhoeven
2018-04-18 8:46 ` Yoshihiro Shimoda
@ 2018-04-18 8:46 ` Yoshihiro Shimoda
0 siblings, 0 replies; 11+ messages in thread
From: Yoshihiro Shimoda @ 2018-04-18 8:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Geert Uytterhoeven, linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
<devicetree@vger.kernel.org>,
Linux-Renesas
Hi Geert-san,
Thank you for the review!
> From: Geert Uytterhoeven, Sent: Friday, April 13, 2018 7:37 PM
>
> Hi Shimoda-san,
>
> On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
<snip>
> > --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
> > +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
> > @@ -26,6 +26,7 @@ Required Properties:
> > - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
> > - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
> > - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
> > + - "renesas,r8a77990-cpg-mssr" for the r8a77995 SoC (R-Car E3)
>
> r8a77990 SoC
Oops! I will fix this in v2.
> > - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> > @@ -0,0 +1,291 @@
>
> > +static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
>
> > + /* Core Clock Outputs */
>
> > + DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6),
>
> ... CLK_PE, 2),
I will fix this.
> > + DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
> > + DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
> > + DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
> > +
> > + DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
>
> I cannot confirm the parent, as Section 8.2.18 ("CAN-FD Clock Frequency
> Control Register (CANFDCKCR)") does not specify the source clock frequency
> for R-Car E3 (unlike for D3). But 800 MHz sounds sane.
According to the Figure 8.1g, PLL0 with 1/2 -- 1/3 -- CANFD clock.
So, the parent clock is PLL0D6 (PLL0 with DIV 6).
> > + DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
>
> I cannot confirm the parent clock, as CSI0 is not documented.
> But given PLL1 runs at 1.6 GHz, PLL1/2 is consistent with PLL1/4 on other
> R-Car Gen3 SoCs with a faster PLL1 (3.2 GHz).
I heard the CSI0 will be documented in the future.
> > +static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
>
> > + DEF_MOD("vin7", 804, R8A77990_CLK_S1D2),
> > + DEF_MOD("vin6", 805, R8A77990_CLK_S1D2),
>
> Vin6/7 have been removed in the Feb. errata.
Oops, I will remove them in v2 patch.
> With the above fixed/confirmed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks!
Best regards,
Yoshihiro Shimoda
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3
@ 2018-04-18 8:46 ` Yoshihiro Shimoda
0 siblings, 0 replies; 11+ messages in thread
From: Yoshihiro Shimoda @ 2018-04-18 8:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Geert Uytterhoeven, linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
Hi Geert-san,
Thank you for the review!
> From: Geert Uytterhoeven, Sent: Friday, April 13, 2018 7:37 PM
>
> Hi Shimoda-san,
>
> On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
<snip>
> > --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
> > +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
> > @@ -26,6 +26,7 @@ Required Properties:
> > - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
> > - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
> > - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
> > + - "renesas,r8a77990-cpg-mssr" for the r8a77995 SoC (R-Car E3)
>
> r8a77990 SoC
Oops! I will fix this in v2.
> > - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> > @@ -0,0 +1,291 @@
>
> > +static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
>
> > + /* Core Clock Outputs */
>
> > + DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6),
>
> ... CLK_PE, 2),
I will fix this.
> > + DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
> > + DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
> > + DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
> > +
> > + DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
>
> I cannot confirm the parent, as Section 8.2.18 ("CAN-FD Clock Frequency
> Control Register (CANFDCKCR)") does not specify the source clock frequency
> for R-Car E3 (unlike for D3). But 800 MHz sounds sane.
According to the Figure 8.1g, PLL0 with 1/2 -- 1/3 -- CANFD clock.
So, the parent clock is PLL0D6 (PLL0 with DIV 6).
> > + DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
>
> I cannot confirm the parent clock, as CSI0 is not documented.
> But given PLL1 runs at 1.6 GHz, PLL1/2 is consistent with PLL1/4 on other
> R-Car Gen3 SoCs with a faster PLL1 (3.2 GHz).
I heard the CSI0 will be documented in the future.
> > +static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
>
> > + DEF_MOD("vin7", 804, R8A77990_CLK_S1D2),
> > + DEF_MOD("vin6", 805, R8A77990_CLK_S1D2),
>
> Vin6/7 have been removed in the Feb. errata.
Oops, I will remove them in v2 patch.
> With the above fixed/confirmed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks!
Best regards,
Yoshihiro Shimoda
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3
@ 2018-04-18 8:46 ` Yoshihiro Shimoda
0 siblings, 0 replies; 11+ messages in thread
From: Yoshihiro Shimoda @ 2018-04-18 8:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Geert Uytterhoeven, linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-04-18 8:46 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-11 9:37 [PATCH 0/2] clk: renesas: Add support for R-Car E3 Yoshihiro Shimoda
2018-04-11 9:37 ` [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions Yoshihiro Shimoda
2018-04-12 12:23 ` Geert Uytterhoeven
2018-04-13 2:16 ` Yoshihiro Shimoda
2018-04-13 2:16 ` Yoshihiro Shimoda
2018-04-13 2:16 ` Yoshihiro Shimoda
2018-04-11 9:37 ` [PATCH 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3 Yoshihiro Shimoda
2018-04-13 10:36 ` Geert Uytterhoeven
2018-04-18 8:46 ` Yoshihiro Shimoda
2018-04-18 8:46 ` Yoshihiro Shimoda
2018-04-18 8:46 ` Yoshihiro Shimoda
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