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b=T2zzcL90Hy2qIHQZ9BL27PrVXiZrjw+qlpWv0CCqKhYBS9hgEVjkkrJ8+oE/7r6k7yAIAM6SWaN651ViE6PxCSqrPUKKTeKYwvjNZb7ATvsliSnD7IUrlA20K0DpURCkYkVC+2FKr/jFw198EIokrz/SwIYskhBAoUs7hRcTwrc= Received: from TYBPR01MB5341.jpnprd01.prod.outlook.com (2603:1096:404:8028::13) by OS3PR01MB6227.jpnprd01.prod.outlook.com (2603:1096:604:e2::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.20; Thu, 29 Sep 2022 12:22:15 +0000 Received: from TYBPR01MB5341.jpnprd01.prod.outlook.com ([fe80::2991:1e2d:e62c:37d0]) by TYBPR01MB5341.jpnprd01.prod.outlook.com ([fe80::2991:1e2d:e62c:37d0%3]) with mapi id 15.20.5676.022; Thu, 29 Sep 2022 12:22:15 +0000 From: Yoshihiro Shimoda To: Andrew Lunn CC: "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" Subject: RE: [PATCH v3 2/3] net: ethernet: renesas: Add Ethernet Switch driver Thread-Topic: [PATCH v3 2/3] net: ethernet: renesas: Add Ethernet Switch driver Thread-Index: AQHYzkQbCGZNTw1MNUuaNx/SR8stKK3s/34AgARIsfCAANSngIAAruVQgAB4MACAAQobwIAAeWqAgAGUAQA= Date: Thu, 29 Sep 2022 12:22:15 +0000 Message-ID: References: <20220922052803.3442561-1-yoshihiro.shimoda.uh@renesas.com> <20220922052803.3442561-3-yoshihiro.shimoda.uh@renesas.com> In-Reply-To: Accept-Language: ja-JP, en-US Content-Language: ja-JP X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=renesas.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYBPR01MB5341.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9da0e72a-07b4-4147-2973-08daa2153ead X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Sep 2022 12:22:15.5582 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vvG7ZJQGIJKLw/RamVMhkcdAp4nCM1IzvbEZBPJ+e5ROVKbDv8KgWipR2XUas2c/5DCPwCi1oFN3bPiv7pOdhQAR2ckpKGIEEdhKj+NIm7/FvvwI4g2D+nsoXysr62Ru X-MS-Exchange-Transport-CrossTenantHeadersStamped: OS3PR01MB6227 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Andrew, > From: Andrew Lunn, Sent: Wednesday, September 28, 2022 9:01 PM >=20 > > > How do you direct a frame from the > > > CPU out a specific user port? Via the DMA ring you place it into, or > > > do you need a tag on the frame to indicate its egress port? > > > > Via the DMA ring. >=20 > Are there bits in the ring descriptor which indicate the user port? > Can you set these bits to some other value which causes the switch to > use its MAC table to determine the egress interface? I'm sorry, I misunderstood the hardware behaviors. 1) From CPU to user port: CPU sends a frame to all user ports. 2) From user port to CPU: each user port sends a frame to each DMA ring. About the 1) above, the switch can have MAC tables and sends a frame to a specific user port. However, the driver doesn't support it. > > > > The PHY is 88E2110 on my environment, so Linux has a driver in > > > > drivers/net/phy/marvell10g.c. However, I guess this is related to > > > > configuration of the PHY chip on the board, it needs to change > > > > the host 7interface mode, but the driver doesn't support it for now= . > > > > > > Please give us more details. The marvell10g driver will change its > > > host side depending on the result of the line side negotiation. It > > > changes the value of phydev->interface to indicate what is it doing o= n > > > its host side, and you have some control over what modes it will use > > > on the host side. You can probably define its initial host side mode > > > via phy-mode in DT. > > > > I'm sorry, my explanation was completely wrong. > > My environment needs to change default MAC speed from 2.5G/5G to 1000M. > > The register of 88E2110 is 31.F000.7:6. And sets the register to "10" (= 1000 Mbps). > > (Default value of the register is "11" (Speed controlled by other regis= ter).) >=20 > Is this the host side speed? The speed of the SERDES between the > switch and the PHY? Yes. > Normally, the PHY determines this from the line > side. If the line side is using 2.5G, it will set the host side to > 2500BaseX. If the line side is 1G, the host side is likely to be > SGMII. >=20 > You have already removed speeds you don't support. So the PHY will not > negotiate 2.5G or 5G. It is limited to 1G. So it should always have > the host side as SGMII. This should be enough to make it work. I see. However, if I dropped specific registers setting, it doesn't work correctly= . I'll investigate why removing speeds of PHY didn't work. Best regards, Yoshihiro Shimoda > Andrew