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Thu, 3 Jun 2021 08:17:36 +0000 From: "ishii.shuuichir@fujitsu.com" To: 'Richard Henderson' , Peter Maydell Subject: RE: [RFC] Adding the A64FX's HPC funtions. Thread-Topic: [RFC] Adding the A64FX's HPC funtions. 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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: fujitsu.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYCPR01MB6160.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ae3cad97-b305-4b23-cac2-08d926680bcc X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jun 2021 08:17:36.5134 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a19f121d-81e1-4858-a9d8-736e267fd4c7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: m66hNl5h4ONRM3kGr0uYyhJ1Q+Wak4sStFiti3KZI36qwR5sDKiIrQ6ocPcc3BGykhxt2MqXC7+jAbFJ3J+bWOoljRrB1UmpDwW7iggTSfU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYCPR01MB6835 Received-SPF: pass client-ip=216.71.158.65; envelope-from=ishii.shuuichir@fujitsu.com; helo=esa20.fujitsucc.c3s2.iphmx.com X-Spam_action: no action Received-SPF: pass client-ip=96.88.95.61; envelope-from=mlmgr@proulx.com; helo=havoc.proulx.com X-Spam_score_int: 20 X-Spam_score: 2.0 X-Spam_bar: ++ X-Spam_report: (2.0 / 5.0 requ) BAYES_50=0.8, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, HK_RANDOM_ENVFROM=0.998, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "ishii.shuuichir@fujitsu.com" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, Richard. Thank you for your comment. > My first thought is that -cpu max can simply enable the extensions, witho= ut > extra flags. The max cpu has all of the features that we can enable, and= as I > see it this is just one more. Let me confirm a few things about the above comment. Does it mean that I don't need to explicitly enable individual extensions such as a64fx-hpc-sec, a64fx-hpc-hwpf, and a64fx-hpc-hwb, since all extensions can be enabled by specifying -cpu max? > The microarchitectural document provided does not list all of the system > register reset values for the A64FX, and I would be surprised if there we= re an > architectural id register that specified a non-standard extension like th= is. > Thus I would expect to add ARM_FEATURE_A64FX with which to enable these > extensions in helper.c. As you said, some of the published specifications do not describe the reset values of th= e registers. I would like to implement this in QEMU by referring to a real machine with = A64FX. > I can certainly help you with this. I am not familiar with this, and I apologize for any inconvenience this may= cause, but I appreciate your cooperation. Best regards. > -----Original Message----- > From: Richard Henderson > Sent: Thursday, June 3, 2021 4:02 AM > To: Peter Maydell ; Ishii, Shuuichirou/=1B$B@P0= f=1B(B =1B$B<~0lO:=1B(B > > Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org > Subject: Re: [RFC] Adding the A64FX's HPC funtions. >=20 > On 6/1/21 8:21 AM, Peter Maydell wrote: > >>> I'm thinking of implementing A64FX HPC extension in qemu. > >>> A64FX [1] is a CPU developed by Fujitsu that implements armv8+SVE. > >>> > >>> [1] > >>> > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitec > >>> ture > >>> _Manual_en_1.4.pdf > >>> > >>> A64FX is a CPU developed for HPC (High Performance Computing), and > >>> HPC extensions [2] are implemented to improve the performance of user > programs. > >>> > >>> [2] > >>> > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Specification > >>> _HP > >>> C_Extension_v1_EN.pdf > >>> > >>> The details of each function are described in [2], and the HPC > >>> extensions include > >>> 1) Tag address override > >>> 2) Sector cache > >>> 3) Hardware barrier > >>> 4) Hardware prefetch assist > >>> are implemented. >=20 > Thanks for the pointers. It looks to me that it'll be easy to implement = these in > qemu. We'll need to implement the registers, so that the OS can read bac= k the > values, but we do not need to actually do anything with them. >=20 > >>> 1) Is target/arm/helper.c enough to implement the register > >>> (ARMCPRegInfo > >>> structure) of HPC extension function of A64FX? >=20 > Yes. >=20 > >>> 2) Is it OK to specify the option to set the HPC extension of A64FX > >>> as follows, for example? > >>> > >>> -M virt -cpu max,a64fx-hpc-sec=3Don (*sector cache function) -M virt > >>> -cpu max,a64fx-hpc-hwpf=3Don (*hardware prefetvh assist function) -M > >>> virt -cpu max,a64fx-hpc-hwb=3Don (*hardware barrier function) > >>> > >>> It is also possible to implement something like -cpu a64fx, but > >>> since we don't know if we can implement it immediately, we assume > >>> that we will use the -cpu max option first. >=20 > My first thought is that -cpu max can simply enable the extensions, witho= ut > extra flags. The max cpu has all of the features that we can enable, and= as I > see it this is just one more. >=20 > I would like to add -cpu a64fx at some point. But as you say, that need = not > happen right away. >=20 > >>> Since there is no example of A64FX function implemented in QEMU, we > >>> would appreciate your comments before we post a patch. >=20 > We endeavor to enable features by the architectural id registers when pos= sible. > Thus the cpu_isar_feature() checks in helper.c. >=20 > The microarchitectural document provided does not list all of the system > register reset values for the A64FX, and I would be surprised if there we= re an > architectural id register that specified a non-standard extension like th= is. > Thus I would expect to add ARM_FEATURE_A64FX with which to enable these > extensions in helper.c. >=20 > I can certainly help you with this. >=20 >=20 > r~