From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Fabrizio Castro Subject: RE: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes Date: Fri, 26 Oct 2018 09:48:05 +0000 Message-ID: References: <1540542307-63158-1-git-send-email-biju.das@bp.renesas.com> In-Reply-To: <1540542307-63158-1-git-send-email-biju.das@bp.renesas.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 To: Biju Das , Rob Herring , Mark Rutland Cc: Simon Horman , Magnus Damm , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , Geert Uytterhoeven , Chris Paterson , Daniel Lezcano , Thomas Gleixner , John Stultz List-ID: > Subject: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes > > This patch adds CMT{0|1|2|3} device nodes for r8a7796 SoC. > > Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro > --- > This patch is tested against renesas-dev > > I have executed on inconsistency-check, nanosleep and clocksource_switch > selftests on this arm64 SoC. The inconsistency-check and nanosleep tests > are working fine.The clocksource_switch asynchronous test is failing due > to inconsistency-check failure on "arch_sys_counter". > > But if i skip the clocksource_switching of "arch_sys_counter", the > asynchronous test is passing for CMT0/1/2/3 timer. > > Has any one noticed this issue? > --- > arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++= ++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/d= ts/renesas/r8a7796.dtsi > index 1ec6aaa..d62febd0 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > @@ -401,6 +401,76 @@ > reg =3D <0 0xe6060000 0 0x50c>; > }; > > +cmt0: timer@e60f0000 { > +compatible =3D "renesas,r8a7796-cmt0", > + "renesas,rcar-gen3-cmt0"; > +reg =3D <0 0xe60f0000 0 0x1004>; > +interrupts =3D , > + ; > +clocks =3D <&cpg CPG_MOD 303>; > +clock-names =3D "fck"; > +power-domains =3D <&sysc R8A7796_PD_ALWAYS_ON>; > +resets =3D <&cpg 303>; > +status =3D "disabled"; > +}; > + > +cmt1: timer@e6130000 { > +compatible =3D "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg =3D <0 0xe6130000 0 0x1004>; > +interrupts =3D , > + , > + , > + , > + , > + , > + , > + ; > +clocks =3D <&cpg CPG_MOD 302>; > +clock-names =3D "fck"; > +power-domains =3D <&sysc R8A7796_PD_ALWAYS_ON>; > +resets =3D <&cpg 302>; > +status =3D "disabled"; > +}; > + > +cmt2: timer@e6140000 { > +compatible =3D "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg =3D <0 0xe6140000 0 0x1004>; > +interrupts =3D , > + , > + , > + , > + , > + , > + , > + ; > +clocks =3D <&cpg CPG_MOD 301>; > +clock-names =3D "fck"; > +power-domains =3D <&sysc R8A7796_PD_ALWAYS_ON>; > +resets =3D <&cpg 301>; > +status =3D "disabled"; > +}; > + > +cmt3: timer@e6148000 { > +compatible =3D "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg =3D <0 0xe6148000 0 0x1004>; > +interrupts =3D , > + , > + , > + , > + , > + , > + , > + ; > +clocks =3D <&cpg CPG_MOD 300>; > +clock-names =3D "fck"; > +power-domains =3D <&sysc R8A7796_PD_ALWAYS_ON>; > +resets =3D <&cpg 300>; > +status =3D "disabled"; > +}; > + > cpg: clock-controller@e6150000 { > compatible =3D "renesas,r8a7796-cpg-mssr"; > reg =3D <0 0xe6150000 0 0x1000>; > -- > 2.7.4 Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, B= uckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered= No. 04586709. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-os2jpn01on0132.outbound.protection.outlook.com ([104.47.92.132]:61952 "EHLO JPN01-OS2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726580AbeJZSZC (ORCPT ); Fri, 26 Oct 2018 14:25:02 -0400 From: Fabrizio Castro To: Biju Das , Rob Herring , Mark Rutland CC: Biju Das , Simon Horman , Magnus Damm , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , Geert Uytterhoeven , Chris Paterson , Daniel Lezcano , Thomas Gleixner , John Stultz Subject: RE: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes Date: Fri, 26 Oct 2018 09:48:05 +0000 Message-ID: References: <1540542307-63158-1-git-send-email-biju.das@bp.renesas.com> In-Reply-To: <1540542307-63158-1-git-send-email-biju.das@bp.renesas.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: > Subject: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes > > This patch adds CMT{0|1|2|3} device nodes for r8a7796 SoC. > > Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro > --- > This patch is tested against renesas-dev > > I have executed on inconsistency-check, nanosleep and clocksource_switch > selftests on this arm64 SoC. The inconsistency-check and nanosleep tests > are working fine.The clocksource_switch asynchronous test is failing due > to inconsistency-check failure on "arch_sys_counter". > > But if i skip the clocksource_switching of "arch_sys_counter", the > asynchronous test is passing for CMT0/1/2/3 timer. > > Has any one noticed this issue? > --- > arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++= ++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/d= ts/renesas/r8a7796.dtsi > index 1ec6aaa..d62febd0 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > @@ -401,6 +401,76 @@ > reg =3D <0 0xe6060000 0 0x50c>; > }; > > +cmt0: timer@e60f0000 { > +compatible =3D "renesas,r8a7796-cmt0", > + "renesas,rcar-gen3-cmt0"; > +reg =3D <0 0xe60f0000 0 0x1004>; > +interrupts =3D , > + ; > +clocks =3D <&cpg CPG_MOD 303>; > +clock-names =3D "fck"; > +power-domains =3D <&sysc R8A7796_PD_ALWAYS_ON>; > +resets =3D <&cpg 303>; > +status =3D "disabled"; > +}; > + > +cmt1: timer@e6130000 { > +compatible =3D "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg =3D <0 0xe6130000 0 0x1004>; > +interrupts =3D , > + , > + , > + , > + , > + , > + , > + ; > +clocks =3D <&cpg CPG_MOD 302>; > +clock-names =3D "fck"; > +power-domains =3D <&sysc R8A7796_PD_ALWAYS_ON>; > +resets =3D <&cpg 302>; > +status =3D "disabled"; > +}; > + > +cmt2: timer@e6140000 { > +compatible =3D "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg =3D <0 0xe6140000 0 0x1004>; > +interrupts =3D , > + , > + , > + , > + , > + , > + , > + ; > +clocks =3D <&cpg CPG_MOD 301>; > +clock-names =3D "fck"; > +power-domains =3D <&sysc R8A7796_PD_ALWAYS_ON>; > +resets =3D <&cpg 301>; > +status =3D "disabled"; > +}; > + > +cmt3: timer@e6148000 { > +compatible =3D "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg =3D <0 0xe6148000 0 0x1004>; > +interrupts =3D , > + , > + , > + , > + , > + , > + , > + ; > +clocks =3D <&cpg CPG_MOD 300>; > +clock-names =3D "fck"; > +power-domains =3D <&sysc R8A7796_PD_ALWAYS_ON>; > +resets =3D <&cpg 300>; > +status =3D "disabled"; > +}; > + > cpg: clock-controller@e6150000 { > compatible =3D "renesas,r8a7796-cpg-mssr"; > reg =3D <0 0xe6150000 0 0x1000>; > -- > 2.7.4 Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, B= uckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered= No. 04586709.