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bh=UQ/SOJZMdpXAB64KPTLVoTiUFV4F8QWzRnxN6r2WL9c=; b=B9EnXsMtjEVbbFPBOJh7BV6shUAvTOC/yiBYgebkiHmz6W+8BbuamR62EyYYcMq9OVow2p1rllHg19yw/tEMM0PiCQhEhrMGEWe2LBo+Z6J6UoVNgTa3AgGYKAAN8c+nQB+3gm/oILrDhpzyoBrR4GGMHFLKbFCZMw5rt1A4ArU= From: Hongda Deng To: Stefano Stabellini , Julien Grall CC: "xen-devel@lists.xenproject.org" , Bertrand Marquis , Wei Chen Subject: RE: [PATCH] xen/arm: vgic to ignore GICD ICPENRn registers access Thread-Topic: [PATCH] xen/arm: vgic to ignore GICD ICPENRn registers access Thread-Index: AQHXsEJR/bwf5T3s+UClXsOnMpcjEquxXHcAgAC9YACAHOFnsA== Date: Tue, 12 Oct 2021 06:00:20 +0000 Message-ID: References: <20210923061429.16361-1-Hongda.Deng@arm.com> <0b0ede18-b944-8693-dede-616c3386e965@xen.org> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 573175DF71BC404DB7EA184F64FE3B78.0 x-checkrecipientchecked: true Authentication-Results-Original: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2021 06:00:30.3262 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58d3e0e2-8fd2-493e-bbf1-08d98d4598ac X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT057.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0802MB2558 Hi, Thanks for your great and detailed advice, I did some investigations about = vgic especially inflight_irqs in the last few days. > -----Original Message----- > From: Stefano Stabellini > Sent: 2021=1B$BG/=1B(B9=1B$B7n=1B(B24=1B$BF|=1B(B 4:54 > To: Julien Grall > Cc: Hongda Deng ; xen-devel@lists.xenproject.org; > sstabellini@kernel.org; Bertrand Marquis ; Wei > Chen > Subject: Re: [PATCH] xen/arm: vgic to ignore GICD ICPENRn registers acces= s >=20 > On Thu, 23 Sep 2021, Julien Grall wrote: > > Hi, > > > > On 23/09/2021 11:14, Hongda Deng wrote: > > > Currently, Xen will return IO unhandled when guests access GICD ICPEN= Rn > > > registers. This will raise a data abort inside guest. For Linux Guest= , > > > these virtual registers will not be accessed. But for Zephyr, in its > > > GIC initilization code, these virtual registers will be accessed. And > > > zephyr guest will get an IO dataabort in initilization stage and ente= r > > > > s/dataabort/data abort/ > > s/initilization/initialization/ > > Ack. > > > fatal error. Emulating ICPENDR is not easy with the existing vGIC, so > > > we currently ignore these virtual registers access and print a messag= e > > > about whether they are already pending instead of returning unhandled= . > > > More details can be found at [1]. > > > > > > [1] https://lists.xenproject.org/archives/html/xen-devel/2021-09/ > > > msg00744.html > > > > > > Signed-off-by: Hongda Deng > > > --- > > > xen/arch/arm/vgic-v2.c | 10 +++++++--- > > > xen/arch/arm/vgic-v3.c | 29 +++++++++++++++++------------ > > > xen/arch/arm/vgic.c | 37 +++++++++++++++++++++++++++++++++++= ++ > > > xen/include/asm-arm/vgic.h | 2 ++ > > > 4 files changed, 63 insertions(+), 15 deletions(-) > > > > > > diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c > > > index b2da886adc..644c62757c 100644 > > > --- a/xen/arch/arm/vgic-v2.c > > > +++ b/xen/arch/arm/vgic-v2.c > > > @@ -481,10 +481,14 @@ static int vgic_v2_distr_mmio_write(struct vcpu= *v, > > > mmio_info_t *info, > > > case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN): > > > if ( dabt.size !=3D DABT_WORD ) goto bad_width; > > > + rank =3D vgic_rank_offset(v, 1, gicd_reg - GICD_ICPENDR, DAB= T_WORD); > > > + if ( rank =3D=3D NULL ) goto write_ignore; > > > > > > > > > + > > > printk(XENLOG_G_ERR > > > - "%pv: vGICD: unhandled word write %#"PRIregister" to > > > ICPENDR%d\n", > > > - v, r, gicd_reg - GICD_ICPENDR); > > > - return 0; > > > + "%pv: vGICD: unhandled word write %#"PRIregister" to > > > ICPENDR%d, and current pending state is: %s\n", > > > + v, r, gicd_reg - GICD_ICPENDR, > > > + vgic_get_irqs_pending(v, r, rank->index) ? "on" : "of= f"); > > > > Each register contain the information for multiple pending interrupts. = So it > > is a bit confusing to say whether the state is on/off. Instead, it woul= d be > > better to state which interrupt is pending. > > > > Also, I would rather avoid printing a message if there are no interrupt= s > > pending because there are no issues if this is happening. I will fix it in the next version patch. > > > > > + goto write_ignore_32; > > > case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN): > > > if ( dabt.size !=3D DABT_WORD ) goto bad_width; > > > diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c > > > index cb5a70c42e..c94e33ff4f 100644 > > > --- a/xen/arch/arm/vgic-v3.c > > > +++ b/xen/arch/arm/vgic-v3.c > > > @@ -817,10 +817,14 @@ static int > __vgic_v3_distr_common_mmio_write(const > > > char *name, struct vcpu *v, > > > case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN): > > > if ( dabt.size !=3D DABT_WORD ) goto bad_width; > > > + rank =3D vgic_rank_offset(v, 1, reg - GICD_ICPENDR, DABT_WOR= D); > > > + if ( rank =3D=3D NULL ) goto write_ignore; > > > + > > > printk(XENLOG_G_ERR > > > - "%pv: %s: unhandled word write %#"PRIregister" to > > > ICPENDR%d\n", > > > - v, name, r, reg - GICD_ICPENDR); > > > - return 0; > > > + "%pv: %s: unhandled word write %#"PRIregister" to ICP= ENDR%d, > > > and current pending state is: %s\n", > > > + v, name, r, reg - GICD_ICPENDR, > > > + vgic_get_irqs_pending(v, r, rank->index) ? "on" : "of= f"); > > > + goto write_ignore_32; > > > case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN): > > > if ( dabt.size !=3D DABT_WORD ) goto bad_width; > > > @@ -978,19 +982,20 @@ static int vgic_v3_rdistr_sgi_mmio_write(struct > vcpu > > > *v, mmio_info_t *info, > > > case VREG32(GICR_ICFGR1): > > > case VRANGE32(GICR_IPRIORITYR0, GICR_IPRIORITYR7): > > > case VREG32(GICR_ISPENDR0): > > > - /* > > > - * Above registers offset are common with GICD. > > > - * So handle common with GICD handling > > > - */ > > > + /* > > > + * Above registers offset are common with GICD. > > > + * So handle common with GICD handling > > > + */ > > > return __vgic_v3_distr_common_mmio_write("vGICR: SGI", v, > > > info, gicr_reg, r)= ; > > > case VREG32(GICR_ICPENDR0): > > > - if ( dabt.size !=3D DABT_WORD ) goto bad_width; > > > - printk(XENLOG_G_ERR > > > - "%pv: vGICR: SGI: unhandled word write %#"PRIregister= " to > > > ICPENDR0\n", > > > - v, r); > > > - return 0; > > > + /* > > > + * Above registers offset are common with GICD. > > > + * So handle common with GICD handling > > > + */ > > > + return __vgic_v3_distr_common_mmio_write("vGICR: SGI", v, > > > + info, gicr_reg, r); > > > case VREG32(GICR_IGRPMODR0): > > > /* We do not implement security extensions for guests, writ= e > > > ignore */ > > > diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c > > > index 8f9400a519..29a1aa5056 100644 > > > --- a/xen/arch/arm/vgic.c > > > +++ b/xen/arch/arm/vgic.c > > > @@ -470,6 +470,43 @@ void vgic_set_irqs_pending(struct vcpu *v, uint3= 2_t > r, > > > unsigned int rank) > > > } > > > } > > > +bool vgic_get_irqs_pending(struct vcpu *v, uint32_t r, unsigned in= t rank) > > > +{ > > > + const unsigned long mask =3D r; > > > + unsigned int i; > > > + /* The first rank is always per-vCPU */ > > > + bool private =3D rank =3D=3D 0; > > > + bool is_pending =3D false; > > > + > > > + /* LPIs status will never be retrieved via this function */ > > > + ASSERT(!is_lpi(32 * rank + 31)); > > > + > > > + for_each_set_bit( i, &mask, 32 ) > > > + { > > > + unsigned int irq =3D i + 32 * rank; > > > + > > > + if ( !private ) > > > > It is not clear to me why you not handling PPIs/SGIs and ... > > > > > + { > > > + struct pending_irq *p =3D spi_to_pending(v->domain, irq)= ; > > > + > > > + if ( p->desc !=3D NULL ) > > > > ... emulated SPIs (e.g. PL011). > > > > > + { > > > + unsigned long flags; > > > + > > > + spin_lock_irqsave(&p->desc->lock, flags); > > > + is_pending =3D gic_read_pending_state(p->desc); > > > + spin_unlock_irqrestore(&p->desc->lock, flags); > > > > What you are reading here is the pending state from the HW. This is not= the > > same as the pending state from the VM PoV. In fact, in the most common = case, > > the interrupt will be pending from the VM PoV, but simply active from t= he HW > > PoV (it is deactivated once the interrupt has been handled by the guest= ). > > > > I think what you want to check is whether the flag GIC_IRQ_GUEST_QUEUED > is set > > in p->status (Stefano ?). >=20 > Yeah, that's right. In fact, there is no need for checking the hardware > registers. You can just go through the inflight_irqs list and print all > of them (the list is sync on hyp entry on the cpu you are running on, > not the others of course). >=20 >=20 > > This is technically still a bit racy as Xen may still think the interru= pt is > > pending while the it may be actually active in the guest. AFAIK, the ot= her way > > around (i.e. not pending in Xen but pending in the guest) cannot happen= . > > > > Anyway, this is just a message, so it is still better than crashing :). >=20 > +1 Thanks again for your advice.=20 Based on that, I wrote a new patch to go through vcpu->arch.vgic.inflight_i= rqs to check the pending states and print them if there are in the next version patch. I will send i= t for review later. Cheers, Hongda