[U-Boot] [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A SoC

[U-Boot] [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A SoC

[Priyanka Jain]

From: Priyanka Jain <Priyanka.Jain@freescale.com>

LS2088A is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)Process to release secondary cores is different
4)LS2088A SoC has TZASC controller

In preparation of using same binary for LS2088A and LS2080A as both
are using same development boards. code is update to detect difference
based on SVR at runtime


Priyanka Jain (5):
  armv8: lsch3: Use SVR based timer base address detection
  armv8: fsl-layerscape: Update TZASC registers type
  armv8: fsl-layerscape : Check SVR for initializing TZASC
  armv8: fsl-layerscape: Add NXP LS2088A SoC support
  armv8/fsl-lsch3: Update code to release secondary cores

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |   16 +++++-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.h            |    1 +
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   |   58 +++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |   47 +++++++++++-----
 arch/arm/cpu/armv8/fsl-layerscape/mp.c             |   59 ++++++++++++++++++-
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            |    6 +-
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |    1 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |    4 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |    7 ++-
 arch/arm/include/asm/arch-fsl-layerscape/soc.h     |   10 +++
 board/freescale/ls2080a/MAINTAINERS                |    2 +-
 board/freescale/ls2080aqds/MAINTAINERS             |    2 +-
 board/freescale/ls2080aqds/README                  |   12 ++--
 board/freescale/ls2080ardb/MAINTAINERS             |    2 +-
 board/freescale/ls2080ardb/README                  |    8 +-
 15 files changed, 198 insertions(+), 37 deletions(-)

-- 
Changes for v2:
 Rename LS2080A_LS2085A_TIMER_ADDR to
 SYS_FSL_LS2080A_LS2085A_TIMER_ADDR in first patch
1.7.4.1

[U-Boot] [PATCH 1/5][v2] armv8: lsch3: Use SVR based timer base address detection

[Priyanka Jain]

Timer base address has been changed from LS2080A SoC to
new SoCs like LS2088A, LS1088A.

Use SVR based timer base address detection to avoid compile time #ifdef.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v2:
 Rename LS2080A_LS2085A_TIMER_ADDR to SYS_FSL_LS2080A_LS2085A_TIMER_ADDR

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |   14 +++++++++++++-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |    3 ++-
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index b7a2e0c..ce04e48 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -424,8 +424,10 @@ int arch_early_init_r(void)
 
 int timer_init(void)
 {
-	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+	u32 __iomem *cntcr;
 #ifdef CONFIG_FSL_LSCH3
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 svr, ver;
 	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
 #ifdef CONFIG_LS2080A
@@ -439,6 +441,16 @@ int timer_init(void)
 #endif
 
 #ifdef CONFIG_FSL_LSCH3
+	svr = gur_in32(&gur->svr);
+	ver = SVR_SOC_VER(svr);
+	if ((ver == SVR_LS2080A) || (ver == SVR_LS2040A) ||
+	    (ver == SVR_LS2085A) || (ver == SVR_LS2045A))
+		cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
+	else
+#endif
+		cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+
+#ifdef CONFIG_FSL_LSCH3
 	/* Enable timebase for all clusters.
 	 * It is safe to do so even some clusters are not enabled.
 	 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 7acba27..e6cdfcb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -23,7 +23,8 @@
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
-#define CONFIG_SYS_FSL_TIMER_ADDR		0x023d0000
+#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR	0x023d0000
+#define CONFIG_SYS_FSL_TIMER_ADDR		0x023e0000
 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
-- 
1.7.4.1

[U-Boot] [PATCH 2/5][v2] armv8: fsl-layerscape: Update TZASC registers type

[Priyanka Jain]

TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES
are 32-bit regsiters.
So while doing register load-store operations, 32-bit intermediate
register, w0 should be used.
Update x0 register to w0 register type.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S |   28 +++++++++++++-------------
 1 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5d0b7a4..3274cad 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -145,26 +145,26 @@ ENTRY(lowlevel_init)
 	 * 	 placeholders.
 	 */
 	ldr	x1, =TZASC_GATE_KEEPER(0)
-	ldr	x0, [x1]		/* Filter 0 Gate Keeper Register */
-	orr	x0, x0, #1 << 0		/* Set open_request for Filter 0 */
-	str	x0, [x1]
+	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
+	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
+	str	w0, [x1]
 
 	ldr	x1, =TZASC_GATE_KEEPER(1)
-	ldr	x0, [x1]		/* Filter 0 Gate Keeper Register */
-	orr	x0, x0, #1 << 0		/* Set open_request for Filter 0 */
-	str	x0, [x1]
+	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
+	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
+	str	w0, [x1]
 
 	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(0)
-	ldr	x0, [x1]		/* Region-0 Attributes Register */
-	orr	x0, x0, #1 << 31	/* Set Sec global write en, Bit[31] */
-	orr	x0, x0, #1 << 30	/* Set Sec global read en, Bit[30] */
-	str	x0, [x1]
+	ldr	w0, [x1]		/* Region-0 Attributes Register */
+	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
+	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
+	str	w0, [x1]
 
 	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(1)
-	ldr	x0, [x1]		/* Region-1 Attributes Register */
-	orr	x0, x0, #1 << 31	/* Set Sec global write en, Bit[31] */
-	orr	x0, x0, #1 << 30	/* Set Sec global read en, Bit[30] */
-	str	x0, [x1]
+	ldr	w0, [x1]		/* Region-1 Attributes Register */
+	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
+	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
+	str	w0, [x1]
 
 	ldr	x1, =TZASC_REGION_ID_ACCESS_0(0)
 	ldr	w0, [x1]		/* Region-0 Access Register */
-- 
1.7.4.1

[U-Boot] [PATCH 3/5][v2] armv8: fsl-layerscape : Check SVR for initializing TZASC

[Priyanka Jain]

LS2080 SoC and its personalities does not support TZASC
But other new SoCs like LS2088A, LS1088A supports TASC

Hence, skip initializing TZASC for Ls2080A based on SVR

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |   19 ++++++++++++++++++-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |    4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h     |    6 ++++++
 3 files changed, 28 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 3274cad..82b7696 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -10,6 +10,8 @@
 #include <linux/linkage.h>
 #include <asm/gic.h>
 #include <asm/macro.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/soc.h>
 #ifdef CONFIG_MP
 #include <asm/arch/mp.h>
 #endif
@@ -137,6 +139,15 @@ ENTRY(lowlevel_init)
 #endif
 
 #ifdef CONFIG_FSL_TZASC_400
+	bl	svr_dev_id		/* get high 16 bits of SVR */
+	/*
+	 * LS2080 and its personalities does not support TZASC
+	 * So skip TZASC related operations
+	 */
+	ldr	x1, =SVR_DEV_LS2080A
+	cmp	x0, x1
+	b.eq	1f
+
 	/* Set TZASC so that:
 	 * a. We use only Region0 whose global secure write/read is EN
 	 * b. We use only Region0 whose NSAID write/read is EN
@@ -179,7 +190,7 @@ ENTRY(lowlevel_init)
 	isb
 	dsb	sy
 #endif
-
+1:
 #ifdef CONFIG_ARCH_LS1046A
 	/* Initialize the L2 RAM latency */
 	mrs   x1, S3_1_c11_c0_2
@@ -198,6 +209,12 @@ ENTRY(lowlevel_init)
 	ret
 ENDPROC(lowlevel_init)
 
+svr_dev_id:
+	ldr	x1, =FSL_LSCH3_SVR
+	ldr	w0, [x1]
+	lsr	w0, w0, #16
+	ret
+
 #ifdef CONFIG_FSL_LSCH3
 hnf_pstate_poll:
 	/* x0 has the desired status, return 0 for success, 1 for timeout
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index e6cdfcb..1034bf4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -28,6 +28,8 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR				(CONFIG_SYS_FSL_GUTS_ADDR + \
+						 0xA4)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
@@ -155,6 +157,7 @@
 #define TP_INIT_PER_CLUSTER     4
 /* This is chassis generation 3 */
 
+#ifndef __ASSEMBLY__
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
 	unsigned long freq_systembus;
@@ -320,4 +323,5 @@ struct ccsr_reset {
 
 uint get_svr(void);
 
+#endif
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 58e90d8..c20fa97 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -31,6 +31,7 @@
 #define pex_lut_out32(a, v)   out_be32(a, v)
 #endif
 
+#ifndef __ASSEMBLY__
 struct cpu_type {
 	char name[15];
 	u32 soc_ver;
@@ -39,6 +40,7 @@ struct cpu_type {
 
 #define CPU_TYPE_ENTRY(n, v, nc) \
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+#endif
 
 #define SVR_WO_E		0xFFFFFE
 #define SVR_LS1012A		0x870400
@@ -51,6 +53,8 @@ struct cpu_type {
 #define SVR_LS2085A		0x870100
 #define SVR_LS2040A		0x870130
 
+#define SVR_DEV_LS2080A		0x8701
+
 #define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
 #define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
@@ -63,6 +67,7 @@ struct cpu_type {
 #define AHCI_PORT_TRANS_CFG    0x08000029
 #define AHCI_PORT_AXICC_CFG	0x3fffffff
 
+#ifndef __ASSEMBLY__
 /* AHCI (sata) register map */
 struct ccsr_ahci {
 	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
@@ -105,4 +110,5 @@ void erratum_a010315(void);
 
 bool soc_has_dp_ddr(void);
 bool soc_has_aiop(void);
+#endif
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
-- 
1.7.4.1

[U-Boot] [PATCH 4/5][v2] armv8: fsl-layerscape: Add NXP LS2088A SoC support

[Priyanka Jain]

The QorIQ LS2088A SoC is built on layerscape architecture.

It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc  |   58 +++++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           |    6 ++-
 arch/arm/include/asm/arch-fsl-layerscape/config.h |    1 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h    |    4 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |    4 ++
 board/freescale/ls2080a/MAINTAINERS               |    2 +-
 board/freescale/ls2080aqds/MAINTAINERS            |    2 +-
 board/freescale/ls2080aqds/README                 |   12 ++--
 board/freescale/ls2080ardb/MAINTAINERS            |    2 +-
 board/freescale/ls2080ardb/README                 |    8 ++--
 10 files changed, 84 insertions(+), 15 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index f7b949a..c7496c0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -4,6 +4,7 @@ SoC overview
 	2. LS2080A
 	3. LS1012A
 	4. LS1046A
+	5. LS2088A
 
 LS1043A
 ---------
@@ -169,3 +170,60 @@ The LS1046A SoC includes the following function and features:
    - Two DUARTs
    - Integrated flash controller (IFC) supporting NAND and NOR flash
  - QorIQ platform's trust architecture 2.1
+
+LS2088A
+--------
+The LS2088A integrated multicore processor combines eight ARM Cortex-A72
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2088A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A72 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+   the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+   the following functions:
+   - Packet parsing, classification, and distribution (WRIOP)
+   - Queue and Hardware buffer management for scheduling, packet sequencing, and
+     congestion management, buffer allocation and de-allocation (QBMan)
+   - Cryptography acceleration (SEC) at up to 10 Gbps
+   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+   - Decompression/compression acceleration (DCE) at up to 20 Gbps
+   - Accelerated I/O processing (AIOP) at up to 20 Gbps
+   - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+   - Up to eight 10 Gbps Ethernet MACs
+   - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 3.0) controllers
+   - Two high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Serial peripheral interface (SPI) controller
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+ capabilities
+
+LS2088A SoC has 3 more similar SoC personalities
+1)LS2048A, few difference w.r.t. LS2088A:
+       a) Four 64-bit ARM v8 Cortex-A72 CPUs
+
+2)LS2084A, few difference w.r.t. LS2088A:
+       a) No AIOP
+       b) No 32-bit DDR3 SDRAM memory
+       c) 5 * 1/10G + 5 *1G WRIOP
+       d) No L2 switch
+
+3)LS2044A, few difference w.r.t. LS2084A:
+       a) Four 64-bit ARM v8 Cortex-A72 CPUs
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d68eeba..d43361f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -31,8 +31,10 @@ bool soc_has_dp_ddr(void)
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 svr = gur_in32(&gur->svr);
 
-	/* LS2085A has DP_DDR */
-	if (SVR_SOC_VER(svr) == SVR_LS2085A)
+	/* LS2085A, LS2088A, LS2048A has DP_DDR */
+	if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
+	    (SVR_SOC_VER(svr) == SVR_LS2088A) ||
+	    (SVR_SOC_VER(svr) == SVR_LS2048A))
 		return true;
 
 	return false;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 4201e0f..6c3ba49 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -25,6 +25,7 @@
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT		6
 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
+#define CONFIG_FSL_TZASC_400
 #endif
 
 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index e2d96a1..a97be5c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -11,6 +11,10 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
 	CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
 	CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+	CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
+	CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
+	CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
+	CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
 	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
 	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
 	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index c20fa97..5622e74 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -52,6 +52,10 @@ struct cpu_type {
 #define SVR_LS2080A		0x870110
 #define SVR_LS2085A		0x870100
 #define SVR_LS2040A		0x870130
+#define SVR_LS2088A		0x870900
+#define SVR_LS2084A		0x870910
+#define SVR_LS2048A		0x870920
+#define SVR_LS2044A		0x870930
 
 #define SVR_DEV_LS2080A		0x8701
 
diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
index c8dac99..de137ef 100644
--- a/board/freescale/ls2080a/MAINTAINERS
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	York Sun <york.sun@nxp.com>
+M:	York Sun <york.sun@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080a/
 F:	include/configs/ls2080a_emu.h
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 8f78b67..79877d7 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080aqds/
 F:	board/freescale/ls2080a/ls2080aqds.c
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index f288750..2808bd5 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -2,14 +2,14 @@ Overview
 --------
 The LS2080A Development System (QDS) is a high-performance computing,
 evaluation, and development platform that supports the QorIQ LS2080A
-Layerscape Architecture processor. The LS2080AQDS provides validation and
-SW development platform for the Freescale LS2080A processor series, with
-a complete debugging environment.
+and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
+validation and SW development platform for the Freescale LS2080A, LS2088A
+processor series, with a complete debugging environment.
 
-LS2080A SoC Overview
+LS2080A, LS2088A SoC Overview
 --------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
 
  LS2080AQDS board Overview
  -----------------------
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index a20c003..759a146 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080ardb/
 F:	board/freescale/ls2080a/ls2080ardb.c
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index b1613ba..0c9c574 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -1,13 +1,13 @@
 Overview
 --------
 The LS2080A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2080A
+evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
 Layerscape Architecture processor.
 
-LS2080A SoC Overview
+LS2080A, LS2088A SoC Overview
 --------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
-- 
1.7.4.1

[U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[Priyanka Jain]

NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
But other new SoCs like LS2088A, LS1088A release secondary
cores one by one to avoid power spike.

Update code to release secondary cores based on SoC SVR
Add code to release cores one by one for non LS2080A SoCs

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c |    2 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.h |    1 +
 arch/arm/cpu/armv8/fsl-layerscape/mp.c  |   59 ++++++++++++++++++++++++++++--
 3 files changed, 57 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ce04e48..15d157c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -190,7 +190,7 @@ void enable_caches(void)
 }
 #endif
 
-static inline u32 initiator_type(u32 cluster, int init_id)
+inline u32 initiator_type(u32 cluster, int init_id)
 {
 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
index 8072f3c..a05f8aa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
@@ -5,4 +5,5 @@
  */
 
 int fsl_qoriq_core_to_cluster(unsigned int core);
+u32 initiator_type(u32 cluster, int init_id);
 u32 cpu_mask(void);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index f607c39..5cf080f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -9,6 +9,8 @@
 #include <asm/system.h>
 #include <asm/arch/mp.h>
 #include <asm/arch/soc.h>
+#include "cpu.h"
+#include <asm/arch-fsl-layerscape/soc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -22,11 +24,30 @@ phys_addr_t determine_mp_bootpg(void)
 	return (phys_addr_t)&secondary_boot_code;
 }
 
+#ifdef CONFIG_FSL_LSCH3
+void wake_secondary_core_n(int cluster, int core, int cluster_cores)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+	u32 mpidr = 0;
+
+	mpidr = ((cluster << 8) | core);
+	gur_out32(&gur->scratchrw[6], mpidr);
+	asm volatile("dsb st" : : : "memory");
+	rst->brrl |= 1 << ((cluster * cluster_cores) + core);
+	asm volatile("dsb st" : : : "memory");
+	while (gur_in32(&gur->scratchrw[6]) != 0)
+		;
+}
+#endif
+
 int fsl_layerscape_wake_seconday_cores(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #ifdef CONFIG_FSL_LSCH3
 	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+	u32 svr, ver, cluster, type;
+	int j = 0, cluster_cores = 0;
 #elif defined(CONFIG_FSL_LSCH2)
 	struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
 #endif
@@ -55,10 +76,40 @@ int fsl_layerscape_wake_seconday_cores(void)
 #ifdef CONFIG_FSL_LSCH3
 	gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
 	gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
-	gur_out32(&gur->scratchrw[6], 1);
-	asm volatile("dsb st" : : : "memory");
-	rst->brrl = cores;
-	asm volatile("dsb st" : : : "memory");
+
+	svr = gur_in32(&gur->svr);
+	ver = SVR_SOC_VER(svr);
+	if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
+		gur_out32(&gur->scratchrw[6], 1);
+		asm volatile("dsb st" : : : "memory");
+		rst->brrl = cores;
+		asm volatile("dsb st" : : : "memory");
+	} else {
+		/*
+		 * Release the cores out of reset one-at-a-time to avoid
+		 * power spikes
+		 */
+		i = 0;
+		cluster = in_le32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			type = initiator_type(cluster, j);
+			if (type &&
+			    TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
+				cluster_cores++;
+		}
+
+		do {
+			cluster = in_le32(&gur->tp_cluster[i].lower);
+			for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+				type = initiator_type(cluster, j);
+				if (type &&
+				    TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
+					wake_secondary_core_n(i, j,
+							      cluster_cores);
+			}
+		i++;
+		} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+	}
 #elif defined(CONFIG_FSL_LSCH2)
 	scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
 	scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
-- 
1.7.4.1

[U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[york sun]

On 10/24/2016 01:33 AM, Priyanka Jain wrote:
> NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
> But other new SoCs like LS2088A, LS1088A release secondary
> cores one by one to avoid power spike.
>
> Update code to release secondary cores based on SoC SVR
> Add code to release cores one by one for non LS2080A SoCs
>

Have you observed the power spike when releasing them together? They 
only run very short before entering "wfe". Why wasn't it a problem for 
any other multi-core SoCs?

York

[U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[york sun]

On 10/24/2016 01:33 AM, Priyanka Jain wrote:
> NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
> But other new SoCs like LS2088A, LS1088A release secondary
> cores one by one to avoid power spike.
>
> Update code to release secondary cores based on SoC SVR
> Add code to release cores one by one for non LS2080A SoCs
>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c |    2 +-
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.h |    1 +
>  arch/arm/cpu/armv8/fsl-layerscape/mp.c  |   59 ++++++++++++++++++++++++++++--
>  3 files changed, 57 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index ce04e48..15d157c 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -190,7 +190,7 @@ void enable_caches(void)
>  }
>  #endif
>
> -static inline u32 initiator_type(u32 cluster, int init_id)
> +inline u32 initiator_type(u32 cluster, int init_id)
>  {
>  	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>  	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> index 8072f3c..a05f8aa 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> @@ -5,4 +5,5 @@
>   */
>
>  int fsl_qoriq_core_to_cluster(unsigned int core);
> +u32 initiator_type(u32 cluster, int init_id);
>  u32 cpu_mask(void);
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> index f607c39..5cf080f 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> @@ -9,6 +9,8 @@
>  #include <asm/system.h>
>  #include <asm/arch/mp.h>
>  #include <asm/arch/soc.h>
> +#include "cpu.h"
> +#include <asm/arch-fsl-layerscape/soc.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -22,11 +24,30 @@ phys_addr_t determine_mp_bootpg(void)
>  	return (phys_addr_t)&secondary_boot_code;
>  }
>
> +#ifdef CONFIG_FSL_LSCH3
> +void wake_secondary_core_n(int cluster, int core, int cluster_cores)
> +{
> +	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> +	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
> +	u32 mpidr = 0;
> +
> +	mpidr = ((cluster << 8) | core);
> +	gur_out32(&gur->scratchrw[6], mpidr);

What's the definition of each bit for scratchrw[6]? Before this patch, 
secondary cores only check if it is zero.

> +	asm volatile("dsb st" : : : "memory");
> +	rst->brrl |= 1 << ((cluster * cluster_cores) + core);
> +	asm volatile("dsb st" : : : "memory");
> +	while (gur_in32(&gur->scratchrw[6]) != 0)
> +		;

Does each secondary core clear this register after it starts to run?

York

[U-Boot] [PATCH 3/5][v2] armv8: fsl-layerscape : Check SVR for initializing TZASC

[york sun]

On 10/24/2016 01:33 AM, Priyanka Jain wrote:
> LS2080 SoC and its personalities does not support TZASC
> But other new SoCs like LS2088A, LS1088A supports TASC
>
> Hence, skip initializing TZASC for Ls2080A based on SVR
>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |   19 ++++++++++++++++++-
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |    4 ++++
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h     |    6 ++++++
>  3 files changed, 28 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> index 3274cad..82b7696 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> @@ -10,6 +10,8 @@
>  #include <linux/linkage.h>
>  #include <asm/gic.h>
>  #include <asm/macro.h>
> +#include <asm/arch-fsl-layerscape/immap_lsch3.h>
> +#include <asm/arch-fsl-layerscape/soc.h>
>  #ifdef CONFIG_MP
>  #include <asm/arch/mp.h>
>  #endif
> @@ -137,6 +139,15 @@ ENTRY(lowlevel_init)
>  #endif
>
>  #ifdef CONFIG_FSL_TZASC_400
> +	bl	svr_dev_id		/* get high 16 bits of SVR */
> +	/*
> +	 * LS2080 and its personalities does not support TZASC
> +	 * So skip TZASC related operations
> +	 */
> +	ldr	x1, =SVR_DEV_LS2080A
> +	cmp	x0, x1

It will be better to consolidate the get_svr() function to implemente in 
assembly code.

> +	b.eq	1f
> +

Please clarify, before this patch the code runs through this section for 
LS2080A but actually it has no effect, correct?

York

[U-Boot] [PATCH 3/5][v2] armv8: fsl-layerscape : Check SVR for initializing TZASC

[york sun]

On 10/24/2016 10:27 AM, york.sun at nxp.com wrote:
>
> Please clarify, before this patch the code runs through this section for
> LS2080A but actually it has no effect, correct?
>

Never mind. I just realized CONFIG_FSL_TZASC_400 wasn't defined before.

York

[U-Boot] [PATCH 4/5][v2] armv8: fsl-layerscape: Add NXP LS2088A SoC support

[york sun]

On 10/24/2016 01:33 AM, Priyanka Jain wrote:
>
> diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
> index c8dac99..de137ef 100644
> --- a/board/freescale/ls2080a/MAINTAINERS
> +++ b/board/freescale/ls2080a/MAINTAINERS
> @@ -1,5 +1,5 @@
>  LS2080A BOARD
> -M:	York Sun <york.sun@nxp.com>
> +M:	York Sun <york.sun@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>

You can drop my name for this board if you can maintain it. I don't use 
the emulator as much as you do now.

York

[U-Boot] [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A SoC

[york sun]

On 10/24/2016 01:32 AM, Priyanka Jain wrote:
> From: Priyanka Jain <Priyanka.Jain@freescale.com>
>
> LS2088A is similar to LS2080A SoC with some differences like
> 1)Timer controller offset is different
> 2)It has A72 cores
> 3)Process to release secondary cores is different
> 4)LS2088A SoC has TZASC controller
>
> In preparation of using same binary for LS2088A and LS2080A as both
> are using same development boards. code is update to detect difference
> based on SVR at runtime
>
>
> Priyanka Jain (5):
>   armv8: lsch3: Use SVR based timer base address detection
>   armv8: fsl-layerscape: Update TZASC registers type
>   armv8: fsl-layerscape : Check SVR for initializing TZASC
>   armv8: fsl-layerscape: Add NXP LS2088A SoC support
>   armv8/fsl-lsch3: Update code to release secondary cores

Priyanka,

Does PCIe work for you? It doesn't work for my test. The same binary 
works for LS2080ARDB/LS2085ARDB. Do you have other patches? I noticed 
several internal commits related to LS2088A PCIe. Do we need them?

York

[U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[york sun]

On 10/24/2016 08:49 AM, york.sun at nxp.com wrote:
> On 10/24/2016 01:33 AM, Priyanka Jain wrote:
>> NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
>> But other new SoCs like LS2088A, LS1088A release secondary
>> cores one by one to avoid power spike.
>>
>> Update code to release secondary cores based on SoC SVR
>> Add code to release cores one by one for non LS2080A SoCs
>>
>> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
>> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
>> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
>> ---
>>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c |    2 +-
>>  arch/arm/cpu/armv8/fsl-layerscape/cpu.h |    1 +
>>  arch/arm/cpu/armv8/fsl-layerscape/mp.c  |   59
>> ++++++++++++++++++++++++++++--
>>  3 files changed, 57 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> index ce04e48..15d157c 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> @@ -190,7 +190,7 @@ void enable_caches(void)
>>  }
>>  #endif
>>
>> -static inline u32 initiator_type(u32 cluster, int init_id)
>> +inline u32 initiator_type(u32 cluster, int init_id)
>>  {
>>      struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>>      u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> index 8072f3c..a05f8aa 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> @@ -5,4 +5,5 @@
>>   */
>>
>>  int fsl_qoriq_core_to_cluster(unsigned int core);
>> +u32 initiator_type(u32 cluster, int init_id);
>>  u32 cpu_mask(void);
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> index f607c39..5cf080f 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> @@ -9,6 +9,8 @@
>>  #include <asm/system.h>
>>  #include <asm/arch/mp.h>
>>  #include <asm/arch/soc.h>
>> +#include "cpu.h"
>> +#include <asm/arch-fsl-layerscape/soc.h>
>>
>>  DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -22,11 +24,30 @@ phys_addr_t determine_mp_bootpg(void)
>>      return (phys_addr_t)&secondary_boot_code;
>>  }
>>
>> +#ifdef CONFIG_FSL_LSCH3
>> +void wake_secondary_core_n(int cluster, int core, int cluster_cores)
>> +{
>> +    struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>> +    struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
>> +    u32 mpidr = 0;
>> +
>> +    mpidr = ((cluster << 8) | core);
>> +    gur_out32(&gur->scratchrw[6], mpidr);
>
> What's the definition of each bit for scratchrw[6]? Before this patch,
> secondary cores only check if it is zero.
>
>> +    asm volatile("dsb st" : : : "memory");
>> +    rst->brrl |= 1 << ((cluster * cluster_cores) + core);
>> +    asm volatile("dsb st" : : : "memory");
>> +    while (gur_in32(&gur->scratchrw[6]) != 0)
>> +        ;
>
> Does each secondary core clear this register after it starts to run?
>

Priyanka,

I got hold of the architect for the bootrom. I understand the story 
behind the release one-by-one now. It would be better if you can add 
some comments for scratchrw[6] for its expected behaviour.

York

[U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[Priyanka Jain]

> -----Original Message-----
> From: york sun
> Sent: Tuesday, October 25, 2016 12:37 AM
> To: Priyanka Jain <priyanka.jain@nxp.com>; u-boot at lists.denx.de;
> Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> Cc: Raghav Dogra <raghav.dogra@nxp.com>
> Subject: Re: [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release
> secondary cores
> 
> On 10/24/2016 08:49 AM, york.sun at nxp.com wrote:
> > On 10/24/2016 01:33 AM, Priyanka Jain wrote:
> >> NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
> >> But other new SoCs like LS2088A, LS1088A release secondary cores one
> >> by one to avoid power spike.
> >>
> >> Update code to release secondary cores based on SoC SVR Add code to
> >> release cores one by one for non LS2080A SoCs
> >>
> >> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> >> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
> >> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> >> ---
> >>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c |    2 +-
> >>  arch/arm/cpu/armv8/fsl-layerscape/cpu.h |    1 +
> >>  arch/arm/cpu/armv8/fsl-layerscape/mp.c  |   59
> >> ++++++++++++++++++++++++++++--
> >>  3 files changed, 57 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> index ce04e48..15d157c 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> @@ -190,7 +190,7 @@ void enable_caches(void)  }  #endif
> >>
> >> -static inline u32 initiator_type(u32 cluster, int init_id)
> >> +inline u32 initiator_type(u32 cluster, int init_id)
> >>  {
> >>      struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> >>      u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> >> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> >> index 8072f3c..a05f8aa 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
> >> @@ -5,4 +5,5 @@
> >>   */
> >>
> >>  int fsl_qoriq_core_to_cluster(unsigned int core);
> >> +u32 initiator_type(u32 cluster, int init_id);
> >>  u32 cpu_mask(void);
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> >> index f607c39..5cf080f 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
> >> @@ -9,6 +9,8 @@
> >>  #include <asm/system.h>
> >>  #include <asm/arch/mp.h>
> >>  #include <asm/arch/soc.h>
> >> +#include "cpu.h"
> >> +#include <asm/arch-fsl-layerscape/soc.h>
> >>
> >>  DECLARE_GLOBAL_DATA_PTR;
> >>
> >> @@ -22,11 +24,30 @@ phys_addr_t determine_mp_bootpg(void)
> >>      return (phys_addr_t)&secondary_boot_code;
> >>  }
> >>
> >> +#ifdef CONFIG_FSL_LSCH3
> >> +void wake_secondary_core_n(int cluster, int core, int cluster_cores)
> >> +{
> >> +    struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> >> +    struct ccsr_reset __iomem *rst = (void
> *)(CONFIG_SYS_FSL_RST_ADDR);
> >> +    u32 mpidr = 0;
> >> +
> >> +    mpidr = ((cluster << 8) | core);
> >> +    gur_out32(&gur->scratchrw[6], mpidr);
> >
> > What's the definition of each bit for scratchrw[6]? Before this patch,
> > secondary cores only check if it is zero.
> >
> >> +    asm volatile("dsb st" : : : "memory");
> >> +    rst->brrl |= 1 << ((cluster * cluster_cores) + core);
> >> +    asm volatile("dsb st" : : : "memory");
> >> +    while (gur_in32(&gur->scratchrw[6]) != 0)
> >> +        ;
> >
> > Does each secondary core clear this register after it starts to run?
> >
> 
> Priyanka,
> 
> I got hold of the architect for the bootrom. I understand the story behind the
> release one-by-one now. It would be better if you can add some comments
> for scratchrw[6] for its expected behaviour.
> 
> York

Thanks for your inputs.
I will add the comments in code about scratchrcw[6]

[U-Boot] [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A SoC

[Priyanka Jain]

> -----Original Message-----
> From: york sun
> Sent: Tuesday, October 25, 2016 12:33 AM
> To: Priyanka Jain <priyanka.jain@nxp.com>; u-boot at lists.denx.de;
> Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> Cc: Priyanka Jain <Priyanka.Jain@freescale.com>
> Subject: Re: [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A
> SoC
> 
> On 10/24/2016 01:32 AM, Priyanka Jain wrote:
> > From: Priyanka Jain <Priyanka.Jain@freescale.com>
> >
> > LS2088A is similar to LS2080A SoC with some differences like 1)Timer
> > controller offset is different 2)It has A72 cores 3)Process to release
> > secondary cores is different 4)LS2088A SoC has TZASC controller
> >
> > In preparation of using same binary for LS2088A and LS2080A as both
> > are using same development boards. code is update to detect difference
> > based on SVR at runtime
> >
> >
> > Priyanka Jain (5):
> >   armv8: lsch3: Use SVR based timer base address detection
> >   armv8: fsl-layerscape: Update TZASC registers type
> >   armv8: fsl-layerscape : Check SVR for initializing TZASC
> >   armv8: fsl-layerscape: Add NXP LS2088A SoC support
> >   armv8/fsl-lsch3: Update code to release secondary cores
> 
> Priyanka,
> 
> Does PCIe work for you? It doesn't work for my test. The same binary works
> for LS2080ARDB/LS2085ARDB. Do you have other patches? I noticed several
> internal commits related to LS2088A PCIe. Do we need them?
> 
> York

There are some additional patches for PCIe for LS2088A.
I have requested Mingkai to send those patches

--Priyanka

[U-Boot] [PATCH 0/5][v2] Update LS2080A SoC code to support LS2088A SoC

[york sun]

On 10/25/2016 03:36 AM, Priyanka Jain wrote:
>>
>> Priyanka,
>>
>> Does PCIe work for you? It doesn't work for my test. The same binary works
>> for LS2080ARDB/LS2085ARDB. Do you have other patches? I noticed several
>> internal commits related to LS2088A PCIe. Do we need them?
>>
>> York
>
> There are some additional patches for PCIe for LS2088A.
> I have requested Mingkai to send those patches

PCIe is still not working for LS2088A. Please send out those patches ASAP.

York