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x-ms-office365-filtering-correlation-id: 59307d23-debd-45e9-071c-08d644a99dbd x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020);SRVR:VI1PR0402MB2751; x-ms-traffictypediagnostic: VI1PR0402MB2751: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(227817650892897)(275809806118684)(185117386973197); x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(93006095)(93001095)(10201501046)(3002001)(3231382)(944501410)(52105095)(6055026)(148016)(149066)(150057)(6041310)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051)(76991095);SRVR:VI1PR0402MB2751;BCL:0;PCL:0;RULEID:;SRVR:VI1PR0402MB2751; x-forefront-prvs: 08497C3D99 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(346002)(136003)(366004)(376002)(396003)(39860400002)(189003)(199004)(44832011)(9686003)(110136005)(66066001)(53936002)(478600001)(97736004)(2900100001)(14454004)(6116002)(3846002)(316002)(476003)(68736007)(486006)(25786009)(55016002)(81166006)(2501003)(33656002)(8936002)(2201001)(81156014)(86362001)(39060400002)(8676002)(6246003)(575784001)(102836004)(7736002)(7696005)(4326008)(256004)(53546011)(6506007)(76176011)(14444005)(2906002)(105586002)(99286004)(6436002)(74316002)(186003)(71200400001)(106356001)(5660300001)(446003)(71190400001)(229853002)(305945005)(26005);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0402MB2751;H:VI1PR0402MB3485.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 9Lu63InRbCaSHIZKrfdhCULOmp6kSi5On6saGxTlUKXUbb/kweyU52SxsYNlKf+6PSvTFlv73D3crc6Y86WgzQ7rW+6YHKEnbb45wEO0dE0Px+GOwJBuOF+eBUcPmgoGK6vpTL5HemUGmMiCQ4vfPOtNrD7Ou+mxjzkbbkX6qy8qUMKpA9uvERLYtNJ1olt9cbh9xitcwW+SzqbGHMLGW1MGMj8F7GMTausWEX/0cW2yzA0BYMj5FRWPxgxmi8iu8iYmPU5tvBUZHJJZOhiKbfpNxjfAQq/pNS6NuRLLsxh58BgZPsOfjWCzj98739RAwwaC/kRvbEA3dXbg+6P6qTg8ixqMh7kjEJ0SYnRv3T4= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 59307d23-debd-45e9-071c-08d644a99dbd X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Nov 2018 12:07:40.4865 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB2751 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/30/2018 10:31 PM, Roy Pledge wrote:=0A= > Starting with v5 of NXP QBMan devices the hardware supports using=0A= > regular cacheable/shareable memory as the backing store for the=0A= > portals.=0A= > =0A= > This patch adds support for the new portal mode by switching to=0A= > use the DPRC get object region v2 command which returns both=0A= > a base address and offset for the portal memory. The new portal=0A= > region is identified as shareable through the addition of a new=0A= > flag.=0A= > =0A= > Signed-off-by: Roy Pledge =0A= > ---=0A= > drivers/bus/fsl-mc/dprc.c | 3 ++-=0A= > drivers/bus/fsl-mc/fsl-mc-bus.c | 14 ++++++++++++--=0A= > drivers/bus/fsl-mc/fsl-mc-private.h | 17 ++++++++++++++---=0A= > 3 files changed, 28 insertions(+), 6 deletions(-)=0A= > =0A= > diff --git a/drivers/bus/fsl-mc/dprc.c b/drivers/bus/fsl-mc/dprc.c=0A= > index 1c3f621..bde856d 100644=0A= > --- a/drivers/bus/fsl-mc/dprc.c=0A= > +++ b/drivers/bus/fsl-mc/dprc.c=0A= > @@ -461,8 +461,9 @@ int dprc_get_obj_region(struct fsl_mc_io *mc_io,=0A= > =0A= > /* retrieve response parameters */=0A= > rsp_params =3D (struct dprc_rsp_get_obj_region *)cmd.params;=0A= > - region_desc->base_offset =3D le64_to_cpu(rsp_params->base_addr);=0A= > + region_desc->base_offset =3D le64_to_cpu(rsp_params->base_offset);=0A= > region_desc->size =3D le32_to_cpu(rsp_params->size);=0A= > + region_desc->base_address =3D le64_to_cpu(rsp_params->base_addr);=0A= > =0A= > return 0;=0A= > }=0A= > diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-= bus.c=0A= > index f0404c6..25ad422 100644=0A= > --- a/drivers/bus/fsl-mc/fsl-mc-bus.c=0A= > +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c=0A= > @@ -487,10 +487,18 @@ static int fsl_mc_device_get_mmio_regions(struct fs= l_mc_device *mc_dev,=0A= > "dprc_get_obj_region() failed: %d\n", error);=0A= > goto error_cleanup_regions;=0A= > }=0A= > -=0A= > - error =3D translate_mc_addr(mc_dev, mc_region_type,=0A= > + /* Older MC only returned region offset and no base address=0A= Nitpick: comment style is not consistent with existing code in fsl-mc.=0A= =0A= > + * If base address is in the region_desc use it otherwise=0A= > + * revert to old mechanism=0A= > + */=0A= > + if (region_desc.base_address)=0A= > + regions[i].start =3D region_desc.base_address +=0A= > + region_desc.base_offset;=0A= > + else=0A= > + error =3D translate_mc_addr(mc_dev, mc_region_type,=0A= > region_desc.base_offset,=0A= > ®ions[i].start);=0A= > +=0A= > if (error < 0) {=0A= > dev_err(parent_dev,=0A= > "Invalid MC offset: %#x (for %s.%d\'s region %d)\n",=0A= > @@ -504,6 +512,8 @@ static int fsl_mc_device_get_mmio_regions(struct fsl_= mc_device *mc_dev,=0A= > regions[i].flags =3D IORESOURCE_IO;=0A= > if (region_desc.flags & DPRC_REGION_CACHEABLE)=0A= > regions[i].flags |=3D IORESOURCE_CACHEABLE;=0A= > + if (region_desc.flags & DPRC_REGION_SHAREABLE)=0A= > + regions[i].flags |=3D IORESOURCE_MEM;=0A= > }=0A= > =0A= > mc_dev->regions =3D regions;=0A= > diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl= -mc-private.h=0A= > index ea11b4f..28e40d1 100644=0A= > --- a/drivers/bus/fsl-mc/fsl-mc-private.h=0A= > +++ b/drivers/bus/fsl-mc/fsl-mc-private.h=0A= > @@ -79,9 +79,11 @@ int dpmcp_reset(struct fsl_mc_io *mc_io,=0A= > =0A= > /* DPRC command versioning */=0A= > #define DPRC_CMD_BASE_VERSION 1=0A= > +#define DPRC_CMD_2ND_VERSION 2=0A= > #define DPRC_CMD_ID_OFFSET 4=0A= > =0A= > #define DPRC_CMD(id) (((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSI= ON)=0A= > +#define DPRC_CMD_V2(id) (((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_2ND_VER= SION)=0A= > =0A= > /* DPRC command IDs */=0A= > #define DPRC_CMDID_CLOSE DPRC_CMD(0x800)=0A= > @@ -99,7 +101,7 @@ int dpmcp_reset(struct fsl_mc_io *mc_io,=0A= > #define DPRC_CMDID_GET_CONT_ID DPRC_CMD(0x830)=0A= > #define DPRC_CMDID_GET_OBJ_COUNT DPRC_CMD(0x159)=0A= > #define DPRC_CMDID_GET_OBJ DPRC_CMD(0x15A)=0A= > -#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD(0x15E)=0A= > +#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD_V2(0x15E)=0A= > #define DPRC_CMDID_SET_OBJ_IRQ DPRC_CMD(0x15F)=0A= > =0A= > struct dprc_cmd_open {=0A= > @@ -199,9 +201,15 @@ struct dprc_rsp_get_obj_region {=0A= > /* response word 0 */=0A= > __le64 pad;=0A= > /* response word 1 */=0A= > - __le64 base_addr;=0A= > + __le64 base_offset;=0A= > /* response word 2 */=0A= > __le32 size;=0A= > + u8 pad2[3];=0A= Padding size (3B) is incorrect.=0A= =0A= Either add 4B of padding:=0A= __le32 pad2;=0A= =0A= or expose the "type" field:=0A= u8 type;=0A= u8 pad2[3];=0A= =0A= > + /* response word 3 */=0A= > + __le32 flags;=0A= > + __le32 pad3;=0A= > + /* response word 4 */=0A= > + __le64 base_addr;=0A= > };=0A= > =0A= > struct dprc_cmd_set_obj_irq {=0A= > @@ -334,6 +342,7 @@ int dprc_set_obj_irq(struct fsl_mc_io *mc_io,=0A= > /* Region flags */=0A= > /* Cacheable - Indicates that region should be mapped as cacheable */=0A= > #define DPRC_REGION_CACHEABLE 0x00000001=0A= > +#define DPRC_REGION_SHAREABLE 0x00000002=0A= > =0A= The new flag should be added in documentation (DPAA2 UM).=0A= =0A= Regards,=0A= Horia=0A= =0A= From mboxrd@z Thu Jan 1 00:00:00 1970 From: horia.geanta@nxp.com (Horia Geanta) Date: Wed, 7 Nov 2018 12:07:40 +0000 Subject: [PATCH v1 1/2] bus: mc-bus: Add support for mapping shareable portals References: <1540931418-10697-1-git-send-email-roy.pledge@nxp.com> <1540931418-10697-2-git-send-email-roy.pledge@nxp.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 10/30/2018 10:31 PM, Roy Pledge wrote: > Starting with v5 of NXP QBMan devices the hardware supports using > regular cacheable/shareable memory as the backing store for the > portals. > > This patch adds support for the new portal mode by switching to > use the DPRC get object region v2 command which returns both > a base address and offset for the portal memory. The new portal > region is identified as shareable through the addition of a new > flag. > > Signed-off-by: Roy Pledge > --- > drivers/bus/fsl-mc/dprc.c | 3 ++- > drivers/bus/fsl-mc/fsl-mc-bus.c | 14 ++++++++++++-- > drivers/bus/fsl-mc/fsl-mc-private.h | 17 ++++++++++++++--- > 3 files changed, 28 insertions(+), 6 deletions(-) > > diff --git a/drivers/bus/fsl-mc/dprc.c b/drivers/bus/fsl-mc/dprc.c > index 1c3f621..bde856d 100644 > --- a/drivers/bus/fsl-mc/dprc.c > +++ b/drivers/bus/fsl-mc/dprc.c > @@ -461,8 +461,9 @@ int dprc_get_obj_region(struct fsl_mc_io *mc_io, > > /* retrieve response parameters */ > rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params; > - region_desc->base_offset = le64_to_cpu(rsp_params->base_addr); > + region_desc->base_offset = le64_to_cpu(rsp_params->base_offset); > region_desc->size = le32_to_cpu(rsp_params->size); > + region_desc->base_address = le64_to_cpu(rsp_params->base_addr); > > return 0; > } > diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c > index f0404c6..25ad422 100644 > --- a/drivers/bus/fsl-mc/fsl-mc-bus.c > +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c > @@ -487,10 +487,18 @@ static int fsl_mc_device_get_mmio_regions(struct fsl_mc_device *mc_dev, > "dprc_get_obj_region() failed: %d\n", error); > goto error_cleanup_regions; > } > - > - error = translate_mc_addr(mc_dev, mc_region_type, > + /* Older MC only returned region offset and no base address Nitpick: comment style is not consistent with existing code in fsl-mc. > + * If base address is in the region_desc use it otherwise > + * revert to old mechanism > + */ > + if (region_desc.base_address) > + regions[i].start = region_desc.base_address + > + region_desc.base_offset; > + else > + error = translate_mc_addr(mc_dev, mc_region_type, > region_desc.base_offset, > ®ions[i].start); > + > if (error < 0) { > dev_err(parent_dev, > "Invalid MC offset: %#x (for %s.%d\'s region %d)\n", > @@ -504,6 +512,8 @@ static int fsl_mc_device_get_mmio_regions(struct fsl_mc_device *mc_dev, > regions[i].flags = IORESOURCE_IO; > if (region_desc.flags & DPRC_REGION_CACHEABLE) > regions[i].flags |= IORESOURCE_CACHEABLE; > + if (region_desc.flags & DPRC_REGION_SHAREABLE) > + regions[i].flags |= IORESOURCE_MEM; > } > > mc_dev->regions = regions; > diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl-mc-private.h > index ea11b4f..28e40d1 100644 > --- a/drivers/bus/fsl-mc/fsl-mc-private.h > +++ b/drivers/bus/fsl-mc/fsl-mc-private.h > @@ -79,9 +79,11 @@ int dpmcp_reset(struct fsl_mc_io *mc_io, > > /* DPRC command versioning */ > #define DPRC_CMD_BASE_VERSION 1 > +#define DPRC_CMD_2ND_VERSION 2 > #define DPRC_CMD_ID_OFFSET 4 > > #define DPRC_CMD(id) (((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION) > +#define DPRC_CMD_V2(id) (((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_2ND_VERSION) > > /* DPRC command IDs */ > #define DPRC_CMDID_CLOSE DPRC_CMD(0x800) > @@ -99,7 +101,7 @@ int dpmcp_reset(struct fsl_mc_io *mc_io, > #define DPRC_CMDID_GET_CONT_ID DPRC_CMD(0x830) > #define DPRC_CMDID_GET_OBJ_COUNT DPRC_CMD(0x159) > #define DPRC_CMDID_GET_OBJ DPRC_CMD(0x15A) > -#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD(0x15E) > +#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD_V2(0x15E) > #define DPRC_CMDID_SET_OBJ_IRQ DPRC_CMD(0x15F) > > struct dprc_cmd_open { > @@ -199,9 +201,15 @@ struct dprc_rsp_get_obj_region { > /* response word 0 */ > __le64 pad; > /* response word 1 */ > - __le64 base_addr; > + __le64 base_offset; > /* response word 2 */ > __le32 size; > + u8 pad2[3]; Padding size (3B) is incorrect. Either add 4B of padding: __le32 pad2; or expose the "type" field: u8 type; u8 pad2[3]; > + /* response word 3 */ > + __le32 flags; > + __le32 pad3; > + /* response word 4 */ > + __le64 base_addr; > }; > > struct dprc_cmd_set_obj_irq { > @@ -334,6 +342,7 @@ int dprc_set_obj_irq(struct fsl_mc_io *mc_io, > /* Region flags */ > /* Cacheable - Indicates that region should be mapped as cacheable */ > #define DPRC_REGION_CACHEABLE 0x00000001 > +#define DPRC_REGION_SHAREABLE 0x00000002 > The new flag should be added in documentation (DPAA2 UM). Regards, Horia