RE: [EXT] fec driver: ethernet rx is deaf on variscite imx6ul board

[Andy Duan <fugang.duan@nxp.com>]

From: Oliver Graute <oliver.graute@gmail.com> Sent: Thursday, October 24, 2019 4:10 AM
> Hello,
> 
> I use the following nodes in my devicetree to get two ethernet ports working
> with fec driver on a Variscite DART-6UL SoM Board (imx6ul).
> 
> But ethernet RX is deaf and not working. Some clue whats is the issue here?
> 
> Best regards,
> 
> Oliver

It is for new board bringup ? If so, please ask support from NXP in normal operation.
I check your dts in simple, below are my comments:
- MDIO/MDC pins are not configurated
- Please ensure the RMII reference clock 50Mhz active on line, measured it by oscillometer.

Andy
> 
> &fec1 {
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_enet1>;
>         phy-mode = "rmii";
>         phy-reset-gpios = <&gpio5 0 1>;
>         phy-reset-duration = <100>;
>         phy-handle = <&ethphy0>;
> };
> 
> &fec2 {
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_enet2>;
>         phy-mode = "rmii";
>         phy-handle = <&ethphy1>;
>         phy-reset-gpios = <&gpio1 10 1>;
>         phy-reset-duration = <100>;
> 
>         mdio {
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> 
>                 ethphy0: ethernet-phy@1 {
>                         compatible = "ethernet-phy-ieee802.3-c22";
>                         micrel,rmii-reference-clock-select-25-mhz;
>                         clocks = <&clk_rmii_ref>;
>                         clock-names = "rmii-ref";
>                         reg = <1>;
>                 };
> 
>                 ethphy1: ethernet-phy@3 {
>                         compatible = "ethernet-phy-ieee802.3-c22";
>                         micrel,rmii-reference-clock-select-25-mhz;
>                         clocks = <&clk_rmii_ref>;
>                         clock-names = "rmii-ref";
>                         reg = <3>;
>                 };
>         };
> };
>         pinctrl_enet1: enet1grp {
>                 fsl,pins = <
>                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN
> 0x1b0b0
>                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER
> 0x1b0b0
> 
> MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
> 
> MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
>                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN
> 0x1b0b0
> 
> MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
> 
> MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
> 
> MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
>                 >;
>         };
> 
>         pinctrl_enet2: enet2grp {
>                 fsl,pins = <
>                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN
> 0x1b0b0
>                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER
> 0x1b0b0
> 
> MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
> 
> MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
>                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN
> 0x1b0b0
> 
> MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
> 
> MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
> 
> MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
>                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10
> 0x1b0b0
>                 >;
>         };