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* [U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC
@ 2019-05-15 10:07 Yinbo Zhu
  2019-05-15 10:07 ` [U-Boot] [PATCH v4 2/2] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled Yinbo Zhu
  2019-05-22 17:32 ` [U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC Prabhakar Kushwaha
  0 siblings, 2 replies; 4+ messages in thread
From: Yinbo Zhu @ 2019-05-15 10:07 UTC (permalink / raw)
  To: u-boot

From: Yangbo Lu <yangbo.lu@nxp.com>

Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
Change in v4:
		Update the Copyright

 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 3 ++-
 arch/arm/include/asm/arch-fsl-layerscape/clock.h    | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index bc268e207c..0985778ff9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2014-2015, Freescale Semiconductor, Inc.
+ * Copyright 2014-2015, 2018 Freescale Semiconductor, Inc.
  *
  * Derived from arch/power/cpu/mpc85xx/speed.c
  */
@@ -214,6 +214,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return get_i2c_freq(0);
 #if defined(CONFIG_FSL_ESDHC)
 	case MXC_ESDHC_CLK:
+	case MXC_ESDHC2_CLK:
 		return get_sdhc_freq(0);
 #endif
 	case MXC_DSPI_CLK:
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
index cf058d22a9..c6e382b41b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2015, 2018 Freescale Semiconductor, Inc.
  *
  */
 
@@ -14,6 +14,7 @@ enum mxc_clock {
 	MXC_BUS_CLK,
 	MXC_UART_CLK,
 	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
 	MXC_I2C_CLK,
 	MXC_DSPI_CLK,
 };
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [U-Boot] [PATCH v4 2/2] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
  2019-05-15 10:07 [U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC Yinbo Zhu
@ 2019-05-15 10:07 ` Yinbo Zhu
  2019-05-22 17:35   ` Prabhakar Kushwaha
  2019-05-22 17:32 ` [U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC Prabhakar Kushwaha
  1 sibling, 1 reply; 4+ messages in thread
From: Yinbo Zhu @ 2019-05-15 10:07 UTC (permalink / raw)
  To: u-boot

From: Yangbo Lu <yangbo.lu@nxp.com>

u-boot is trying to make CONFIG_BLK as a hard requirement
for DM_MMC. But now it's still not.

config BLK
	bool "Support block devices"
	depends on DM
	default y if DM_MMC

When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC
without CONFIG_BLK enabled wasn't considered. This patch is to
fix probe issue without CONFIG_BLK enabled.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
Change in v4:
		Update the Copyright

 drivers/mmc/fsl_esdhc.c | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 9e34557d16..53277c9216 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2007, 2010-2020 Freescale Semiconductor, Inc
  * Andy Fleming
  *
  * Based vaguely on the pxa mmc code:
@@ -25,6 +25,10 @@
 #include <asm-generic/gpio.h>
 #include <dm/pinctrl.h>
 
+#if !CONFIG_IS_ENABLED(BLK)
+#include "mmc_private.h"
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define SDHCI_IRQ_EN_BITS		(IRQSTATEN_CC | IRQSTATEN_TC | \
@@ -34,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
 				IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
 				IRQSTATEN_DINT)
 #define MAX_TUNING_LOOP 40
+#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
 
 struct fsl_esdhc {
 	uint    dsaddr;		/* SDMA system address register */
@@ -1448,6 +1453,9 @@ static int fsl_esdhc_probe(struct udevice *dev)
 	fdt_addr_t addr;
 	unsigned int val;
 	struct mmc *mmc;
+#if !CONFIG_IS_ENABLED(BLK)
+	struct blk_desc *bdesc;
+#endif
 	int ret;
 
 	addr = dev_read_addr(dev);
@@ -1576,6 +1584,26 @@ static int fsl_esdhc_probe(struct udevice *dev)
 	mmc = &plat->mmc;
 	mmc->cfg = &plat->cfg;
 	mmc->dev = dev;
+#if !CONFIG_IS_ENABLED(BLK)
+	mmc->priv = priv;
+
+	/* Setup dsr related values */
+	mmc->dsr_imp = 0;
+	mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
+	/* Setup the universal parts of the block interface just once */
+	bdesc = mmc_get_blk_desc(mmc);
+	bdesc->if_type = IF_TYPE_MMC;
+	bdesc->removable = 1;
+	bdesc->devnum = mmc_get_next_devnum();
+	bdesc->block_read = mmc_bread;
+	bdesc->block_write = mmc_bwrite;
+	bdesc->block_erase = mmc_berase;
+
+	/* setup initial part type */
+	bdesc->part_type = mmc->cfg->part_type;
+	mmc_list_add(mmc);
+#endif
+
 	upriv->mmc = mmc;
 
 	return esdhc_init_common(priv, mmc);
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC
  2019-05-15 10:07 [U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC Yinbo Zhu
  2019-05-15 10:07 ` [U-Boot] [PATCH v4 2/2] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled Yinbo Zhu
@ 2019-05-22 17:32 ` Prabhakar Kushwaha
  1 sibling, 0 replies; 4+ messages in thread
From: Prabhakar Kushwaha @ 2019-05-22 17:32 UTC (permalink / raw)
  To: u-boot


> -----Original Message-----
> From: Yinbo Zhu <yinbo.zhu@nxp.com>
> Sent: Wednesday, May 15, 2019 3:38 PM
> To: York Sun <york.sun@nxp.com>; u-boot at lists.denx.de; Vabhav Sharma
> <vabhav.sharma@nxp.com>
> Cc: Yinbo Zhu <yinbo.zhu@nxp.com>; Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei
> Pan <jiafei.pan@nxp.com>; Y.b. Lu <yangbo.lu@nxp.com>; Jagdish Gediya
> <jagdish.gediya@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second
> eSDHC
> 
> From: Yangbo Lu <yangbo.lu@nxp.com>
> 
> Layerscape began to use two eSDHC controllers, for example, LS1028A. They
> are same IP block with same reference clock.
> This patch is to add clock support for the second eSDHC.
> 
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
> ---
> Change in v4:
> 		Update the Copyright
> 

Please maintain complete history


>  arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 3 ++-
>  arch/arm/include/asm/arch-fsl-layerscape/clock.h    | 3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> index bc268e207c..0985778ff9 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
> - * Copyright 2014-2015, Freescale Semiconductor, Inc.
> + * Copyright 2014-2015, 2018 Freescale Semiconductor, Inc.

Freescale was there till 2016. After that it was NXP. 

So please start adding NXP copyright

/*
 * Copyright 2017-2019 NXP
 */


--pk

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [U-Boot] [PATCH v4 2/2] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
  2019-05-15 10:07 ` [U-Boot] [PATCH v4 2/2] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled Yinbo Zhu
@ 2019-05-22 17:35   ` Prabhakar Kushwaha
  0 siblings, 0 replies; 4+ messages in thread
From: Prabhakar Kushwaha @ 2019-05-22 17:35 UTC (permalink / raw)
  To: u-boot


> -----Original Message-----
> From: Yinbo Zhu <yinbo.zhu@nxp.com>
> Sent: Wednesday, May 15, 2019 3:38 PM
> To: York Sun <york.sun@nxp.com>; u-boot at lists.denx.de; Vabhav Sharma
> <vabhav.sharma@nxp.com>
> Cc: Yinbo Zhu <yinbo.zhu@nxp.com>; Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei
> Pan <jiafei.pan@nxp.com>; Y.b. Lu <yangbo.lu@nxp.com>; Jagdish Gediya
> <jagdish.gediya@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH v4 2/2] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK
> enabled
> 
> From: Yangbo Lu <yangbo.lu@nxp.com>
> 
> u-boot is trying to make CONFIG_BLK as a hard requirement for DM_MMC. But
> now it's still not.
> 
> config BLK
> 	bool "Support block devices"
> 	depends on DM
> 	default y if DM_MMC
> 
> When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC without
> CONFIG_BLK enabled wasn't considered. This patch is to fix probe issue without
> CONFIG_BLK enabled.
> 
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
> ---
> Change in v4:
> 		Update the Copyright
> 

Adding complete history

>  drivers/mmc/fsl_esdhc.c | 30 +++++++++++++++++++++++++++++-
>  1 file changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> 9e34557d16..53277c9216 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
> - * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
> + * Copyright 2007, 2010-2020 Freescale Semiconductor, Inc
>   * Andy Fleming
>   *

Freescale was there till 2016.
After that it is NXP. So add NXP copyright. 

Please resend this patch. 

>   * Based vaguely on the pxa mmc code:
> @@ -25,6 +25,10 @@
>  #include <asm-generic/gpio.h>
>  #include <dm/pinctrl.h>
> 
> +#if !CONFIG_IS_ENABLED(BLK)
> +#include "mmc_private.h"
> +#endif
> +
>  DECLARE_GLOBAL_DATA_PTR;
> 
>  #define SDHCI_IRQ_EN_BITS		(IRQSTATEN_CC | IRQSTATEN_TC | \
> @@ -34,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  				IRQSTATEN_DEBE | IRQSTATEN_BRR |
> IRQSTATEN_BWR | \
>  				IRQSTATEN_DINT)
>  #define MAX_TUNING_LOOP 40
> +#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
> 
>  struct fsl_esdhc {
>  	uint    dsaddr;		/* SDMA system address register */
> @@ -1448,6 +1453,9 @@ static int fsl_esdhc_probe(struct udevice *dev)
>  	fdt_addr_t addr;
>  	unsigned int val;
>  	struct mmc *mmc;
> +#if !CONFIG_IS_ENABLED(BLK)
> +	struct blk_desc *bdesc;
> +#endif
>  	int ret;
> 
>  	addr = dev_read_addr(dev);
> @@ -1576,6 +1584,26 @@ static int fsl_esdhc_probe(struct udevice *dev)
>  	mmc = &plat->mmc;
>  	mmc->cfg = &plat->cfg;
>  	mmc->dev = dev;
> +#if !CONFIG_IS_ENABLED(BLK)
> +	mmc->priv = priv;
> +
> +	/* Setup dsr related values */
> +	mmc->dsr_imp = 0;
> +	mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
> +	/* Setup the universal parts of the block interface just once */
> +	bdesc = mmc_get_blk_desc(mmc);
> +	bdesc->if_type = IF_TYPE_MMC;
> +	bdesc->removable = 1;
> +	bdesc->devnum = mmc_get_next_devnum();
> +	bdesc->block_read = mmc_bread;
> +	bdesc->block_write = mmc_bwrite;
> +	bdesc->block_erase = mmc_berase;
> +
> +	/* setup initial part type */
> +	bdesc->part_type = mmc->cfg->part_type;
> +	mmc_list_add(mmc);
> +#endif
> +
>  	upriv->mmc = mmc;
> 
>  	return esdhc_init_common(priv, mmc);

@ Peng. Can you please ack on this patch

--pk

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2019-05-22 17:35 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-15 10:07 [U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC Yinbo Zhu
2019-05-15 10:07 ` [U-Boot] [PATCH v4 2/2] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled Yinbo Zhu
2019-05-22 17:35   ` Prabhakar Kushwaha
2019-05-22 17:32 ` [U-Boot] [PATCH v4 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC Prabhakar Kushwaha

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