All of lore.kernel.org
 help / color / mirror / Atom feed
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RESEND PATCHv4 5/9] pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs
Date: Sun, 7 Apr 2019 10:52:15 +0000	[thread overview]
Message-ID: <VI1PR0402MB385428D449D4A8C9668C450697530@VI1PR0402MB3854.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <20190325022546.38427-6-Zhiqiang.Hou@nxp.com>


> -----Original Message-----
> From: Z.q. Hou
> Sent: Monday, March 25, 2019 7:55 AM
> To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; Priyanka Jain
> <priyanka.jain@nxp.com>; York Sun <york.sun@nxp.com>;
> sriram.dash at nxp.com; yamada.masahiro at socionext.com; Prabhakar
> Kushwaha <prabhakar.kushwaha@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>;
> bmeng.cn at gmail.com
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [RESEND PATCHv4 5/9] pci: ls_pcie_g4: add device tree fixups for PCI
> Stream IDs
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update
> device tree nodes to convey SMMU stream IDs in the device tree.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V4:
>  - No change
> 
>  drivers/pci/Makefile                     |   3 +-
>  drivers/pci/pcie_layerscape_gen4.c       |   5 -
>  drivers/pci/pcie_layerscape_gen4_fixup.c | 249 +++++++++++++++++++++++
>  3 files changed, 251 insertions(+), 6 deletions(-)  create mode 100644
> drivers/pci/pcie_layerscape_gen4_fixup.c
> 
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index
> 7f585aad55..8ee828af6d 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
>  obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
>  obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
>  obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
> -obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o
> +obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
> +				pcie_layerscape_gen4_fixup.o
>  obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
>  obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o diff --git
> a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
> index fbe7d35911..4e0d5b168e 100644
> --- a/drivers/pci/pcie_layerscape_gen4.c
> +++ b/drivers/pci/pcie_layerscape_gen4.c
> @@ -570,8 +570,3 @@ U_BOOT_DRIVER(pcie_layerscape_gen4) = {
>  	.probe	= ls_pcie_g4_probe,
>  	.priv_auto_alloc_size = sizeof(struct ls_pcie_g4),  };
> -
> -/* No any fixup so far */
> -void ft_pci_setup(void *blob, bd_t *bd) -{ -} diff --git
> a/drivers/pci/pcie_layerscape_gen4_fixup.c
> b/drivers/pci/pcie_layerscape_gen4_fixup.c
> new file mode 100644
> index 0000000000..ceeea17f19
> --- /dev/null
> +++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
> @@ -0,0 +1,249 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR X11
> +/*
> + * Copyright 2018 NXP

Copyright should be now 2018-2019

Check for other files also.

  reply	other threads:[~2019-04-07 10:52 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-25  2:24 [U-Boot] [RESEND PATCHv4 0/9] pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Z.q. Hou
2019-03-25  2:24 ` [U-Boot] [RESEND PATCHv4 1/9] armv8: fsl-layerscpae: correct the PCIe controllers' region size Z.q. Hou
2019-04-01  3:22   ` Bin Meng
2019-04-01  3:48     ` Z.q. Hou
2019-03-25  2:24 ` [U-Boot] [RESEND PATCHv4 2/9] armv8: lx2160a: add MMU table entries for PCIe Z.q. Hou
2019-04-01  3:22   ` Bin Meng
2019-04-01  4:08     ` Z.q. Hou
2019-04-01  5:32       ` Bin Meng
2019-04-01  9:11         ` Z.q. Hou
2019-04-01  9:14           ` Bin Meng
2019-04-01  9:26             ` Z.q. Hou
2019-04-01  9:35               ` Bin Meng
2019-04-07 10:49   ` Prabhakar Kushwaha
2019-04-08  2:45     ` Z.q. Hou
2019-03-25  2:24 ` [U-Boot] [RESEND PATCHv4 3/9] pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Z.q. Hou
2019-04-01  3:22   ` Bin Meng
2019-04-01  4:11     ` Z.q. Hou
2019-03-25  2:24 ` [U-Boot] [RESEND PATCHv4 4/9] kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPAT Z.q. Hou
2019-04-01  3:22   ` Bin Meng
2019-04-01  4:12     ` Z.q. Hou
2019-03-25  2:24 ` [U-Boot] [RESEND PATCHv4 5/9] pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Z.q. Hou
2019-04-07 10:52   ` Prabhakar Kushwaha [this message]
2019-04-08  2:51     ` Z.q. Hou
2019-03-25  2:24 ` [U-Boot] [RESEND PATCHv4 6/9] armv8: lx2160a: add PCIe controller DT nodes Z.q. Hou
2019-04-01  3:22   ` Bin Meng
2019-04-01  4:12     ` Z.q. Hou
2019-03-25  2:24 ` [U-Boot] [RESEND PATCHv4 7/9] armv8: lx2160a: enable PCIe support Z.q. Hou
2019-04-01  3:22   ` Bin Meng
2019-04-01  4:18     ` Z.q. Hou
2019-04-07 10:52   ` Prabhakar Kushwaha
2019-04-08  2:52     ` Z.q. Hou
2019-03-25  2:24 ` [U-Boot] [RESEND PATCHv4 8/9] dm: pci: add APIs for capability accessors Z.q. Hou
2019-04-01  3:36   ` Bin Meng
2019-04-01  4:21     ` Z.q. Hou
2019-03-25  2:24 ` [U-Boot] [RESEND PATCHv4 9/9] dm: pci: add APIs for MPS and MRRS accessors Z.q. Hou
2019-04-01  6:00   ` Bin Meng
2019-04-01  7:31     ` Bin Meng
2019-04-01  9:14       ` Z.q. Hou
2019-04-01  9:13     ` Z.q. Hou

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=VI1PR0402MB385428D449D4A8C9668C450697530@VI1PR0402MB3854.eurprd04.prod.outlook.com \
    --to=prabhakar.kushwaha@nxp.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.