From mboxrd@z Thu Jan  1 00:00:00 1970
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Date: Thu, 22 Aug 2019 08:32:55 +0000
Subject: [U-Boot] [PATCH 3/5] armv8: fsl-layerscape: make icid setup
 endianness aware
In-Reply-To: <VI1PR0402MB34854EFE93C6D282C23D67D298DC0@VI1PR0402MB3485.eurprd04.prod.outlook.com>
References: <20190730142959.8467-1-laurentiu.tudor@nxp.com>
 <20190730142959.8467-3-laurentiu.tudor@nxp.com>
 <VI1PR0402MB34854EFE93C6D282C23D67D298DC0@VI1PR0402MB3485.eurprd04.prod.outlook.com>
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> -----Original Message-----
> From: Horia Geanta
> Sent: Wednesday, July 31, 2019 1:24 AM
> To: Laurentiu Tudor <laurentiu.tudor@nxp.com>; u-boot at lists.denx.de;
> Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> Subject: Re: [PATCH 3/5] armv8: fsl-layerscape: make icid setup endianness
> aware
>=20
> On 7/30/2019 5:30 PM, laurentiu.tudor at nxp.com wrote:
> > From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> >
> > The current implementation assumes that the registers holding the
> > ICIDs are universally big endian. That's no longer the case on newer
> > platforms so update the code to take into account the endianness of
> > each register.
> >
> > Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Reviewed-by: Horia Geant=C4=83 <horia.geanta@nxp.com>
>=20


This patch has been applied to fsl-qoriq master, awaiting upstream.

--pk