[U-Boot] [PATCHv2 0/8] dm: pci: add Freescale PowerPC PCIe driver

[U-Boot] [PATCHv2 0/8] dm: pci: add Freescale PowerPC PCIe driver

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Add PCIe DM driver for Freescale PowerPC PCIe controllers.

Hou Zhiqiang (8):
  powerpc: mpc85xx: Move CONFIG_FSL_PCIE_DISABLE_ASPM to Kconfig
  powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to Kconfig
  powerpc: mpc85xx: Update the condition to compile PCI routines
  powerpc: T208xQDS: Compile the legacy PCIe routines conditionally
  t2080: dts: Added PCIe DT nodes
  dm: pci: add Freescale PowerPC PCIe driver
  powerpc: T208xQDS: Disable legacy PCIe driver
  configs: T2080QDS: Enable PCIe driver

 arch/powerpc/cpu/mpc85xx/Kconfig          |  29 +
 arch/powerpc/cpu/mpc85xx/pci.c            |   2 +-
 arch/powerpc/dts/t2080.dtsi               |  48 ++
 arch/powerpc/include/asm/config_mpc85xx.h |   5 -
 board/freescale/t208xqds/pci.c            |   2 +
 configs/T2080QDS_NAND_defconfig           |   4 +
 configs/T2080QDS_SDCARD_defconfig         |   4 +
 configs/T2080QDS_SPIFLASH_defconfig       |   4 +
 configs/T2080QDS_defconfig                |   4 +
 drivers/pci/Kconfig                       |   8 +
 drivers/pci/Makefile                      |   1 +
 drivers/pci/pcie_fsl.c                    | 611 ++++++++++++++++++++++
 drivers/pci/pcie_fsl.h                    |  57 ++
 drivers/pci/pcie_fsl_fixup.c              |  51 ++
 include/configs/BSC9132QDS.h              |   1 -
 include/configs/C29XPCIE.h                |   1 -
 include/configs/MPC8536DS.h               |   1 -
 include/configs/MPC8544DS.h               |   1 -
 include/configs/MPC8548CDS.h              |   1 -
 include/configs/MPC8568MDS.h              |   1 -
 include/configs/MPC8569MDS.h              |   1 -
 include/configs/MPC8572DS.h               |   1 -
 include/configs/P1010RDB.h                |   1 -
 include/configs/P1022DS.h                 |   1 -
 include/configs/P1023RDB.h                |   1 -
 include/configs/T208xQDS.h                |  19 -
 include/configs/T208xRDB.h                |   1 -
 include/configs/UCP1020.h                 |   1 -
 include/configs/controlcenterd.h          |   1 -
 include/configs/p1_p2_rdb_pc.h            |   1 -
 include/configs/p1_twr.h                  |   1 -
 include/configs/sbc8548.h                 |   1 -
 include/configs/xpedite537x.h             |   1 -
 include/configs/xpedite550x.h             |   1 -
 34 files changed, 824 insertions(+), 44 deletions(-)
 create mode 100644 drivers/pci/pcie_fsl.c
 create mode 100644 drivers/pci/pcie_fsl.h
 create mode 100644 drivers/pci/pcie_fsl_fixup.c

-- 
2.17.1

[U-Boot] [PATCHv2 1/8] powerpc: mpc85xx: Move CONFIG_FSL_PCIE_DISABLE_ASPM to Kconfig

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Use the Kconfig option to select the PCIe ASPM errata.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - New patch.

 arch/powerpc/cpu/mpc85xx/Kconfig          | 8 ++++++++
 arch/powerpc/include/asm/config_mpc85xx.h | 5 -----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 0057f195b3..02bc1caa3f 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -702,6 +702,7 @@ config ARCH_P1011
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
+	select FSL_PCIE_DISABLE_ASPM
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -716,6 +717,7 @@ config ARCH_P1020
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
+	select FSL_PCIE_DISABLE_ASPM
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -735,6 +737,7 @@ config ARCH_P1021
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
+	select FSL_PCIE_DISABLE_ASPM
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -782,6 +785,7 @@ config ARCH_P1024
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
+	select FSL_PCIE_DISABLE_ASPM
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -802,6 +806,7 @@ config ARCH_P1025
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
+	select FSL_PCIE_DISABLE_ASPM
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -1431,6 +1436,9 @@ config SYS_P4080_ERRATUM_SERDES_A001
 config SYS_P4080_ERRATUM_SERDES_A005
 	bool
 
+config FSL_PCIE_DISABLE_ASPM
+	bool
+
 config SYS_FSL_QORIQ_CHASSIS1
 	bool
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7c963cdc35..946e74a93b 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -61,19 +61,16 @@
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_ARCH_P1011)
 #define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 #elif defined(CONFIG_ARCH_P1020)
 #define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #endif
 
 #elif defined(CONFIG_ARCH_P1021)
 #define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
@@ -95,14 +92,12 @@
 /* P1024 is lower end variant of P1020 */
 #elif defined(CONFIG_ARCH_P1024)
 #define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 /* P1025 is lower end variant of P1021 */
 #elif defined(CONFIG_ARCH_P1025)
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
-- 
2.17.1

[U-Boot] [PATCHv2 1/8] powerpc: mpc85xx: Move CONFIG_FSL_PCIE_DISABLE_ASPM to Kconfig

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Z.q. Hou
> Sent: Thursday, May 23, 2019 5:52 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; bmeng.cn at gmail.com; Jagdish Gediya
> <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com;
> sr at denx.de
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 1/8] powerpc: mpc85xx: Move
> CONFIG_FSL_PCIE_DISABLE_ASPM to Kconfig
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Use the Kconfig option to select the PCIe ASPM errata.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---

This patch has been applied to u-boot-mpc85xx, awaiting upstream.

--pk

[U-Boot] [PATCHv2 2/8] powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to Kconfig

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Use the Kconfig option to select the PCIe reset errata.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - New patch.

 arch/powerpc/cpu/mpc85xx/Kconfig | 21 +++++++++++++++++++++
 include/configs/BSC9132QDS.h     |  1 -
 include/configs/C29XPCIE.h       |  1 -
 include/configs/MPC8536DS.h      |  1 -
 include/configs/MPC8544DS.h      |  1 -
 include/configs/MPC8548CDS.h     |  1 -
 include/configs/MPC8568MDS.h     |  1 -
 include/configs/MPC8569MDS.h     |  1 -
 include/configs/MPC8572DS.h      |  1 -
 include/configs/P1010RDB.h       |  1 -
 include/configs/P1022DS.h        |  1 -
 include/configs/P1023RDB.h       |  1 -
 include/configs/T208xQDS.h       |  1 -
 include/configs/T208xRDB.h       |  1 -
 include/configs/UCP1020.h        |  1 -
 include/configs/controlcenterd.h |  1 -
 include/configs/p1_p2_rdb_pc.h   |  1 -
 include/configs/p1_twr.h         |  1 -
 include/configs/sbc8548.h        |  1 -
 include/configs/xpedite537x.h    |  1 -
 include/configs/xpedite550x.h    |  1 -
 21 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 02bc1caa3f..5c23efcf66 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -533,6 +533,7 @@ config ARCH_BSC9132
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_I2C_A004447
 	select SYS_FSL_ERRATUM_IFC_A002769
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -551,6 +552,7 @@ config ARCH_C29X
 	select SYS_FSL_DDR_VER_46
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ESDHC111
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -566,6 +568,7 @@ config ARCH_MPC8536
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
@@ -594,6 +597,7 @@ config ARCH_MPC8544
 	bool
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A005125
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -609,6 +613,7 @@ config ARCH_MPC8548
 	select SYS_FSL_ERRATUM_NMG_LBC103
 	select SYS_FSL_ERRATUM_NMG_ETSEC129
 	select SYS_FSL_ERRATUM_I2C_A004447
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_DDR1
 	select SYS_FSL_HAS_SEC
@@ -633,6 +638,7 @@ config ARCH_MPC8560
 config ARCH_MPC8568
 	bool
 	select FSL_LAW
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -643,6 +649,7 @@ config ARCH_MPC8569
 	select FSL_LAW
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -657,6 +664,7 @@ config ARCH_MPC8572
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_DDR_115
 	select SYS_FSL_ERRATUM_DDR111_DDR134
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
@@ -681,6 +689,7 @@ config ARCH_P1010
 	select SYS_FSL_ERRATUM_P1010_A003549
 	select SYS_FSL_ERRATUM_SEC_A003571
 	select SYS_FSL_ERRATUM_IFC_A003399
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -718,6 +727,7 @@ config ARCH_P1020
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select FSL_PCIE_DISABLE_ASPM
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -738,6 +748,7 @@ config ARCH_P1021
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select FSL_PCIE_DISABLE_ASPM
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -759,6 +770,7 @@ config ARCH_P1022
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_SATA_A001
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -772,6 +784,7 @@ config ARCH_P1023
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_I2C_A004447
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -786,6 +799,7 @@ config ARCH_P1024
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select FSL_PCIE_DISABLE_ASPM
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -807,6 +821,7 @@ config ARCH_P1025
 	select SYS_FSL_ERRATUM_ELBC_A001
 	select SYS_FSL_ERRATUM_ESDHC111
 	select FSL_PCIE_DISABLE_ASPM
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -824,6 +839,7 @@ config ARCH_P2020
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_ERRATUM_ESDHC_A001
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
@@ -1079,6 +1095,7 @@ config ARCH_T2080
 	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
@@ -1103,6 +1120,7 @@ config ARCH_T2081
 	select SYS_FSL_ERRATUM_A007212
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
+	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS2
@@ -1439,6 +1457,9 @@ config SYS_P4080_ERRATUM_SERDES_A005
 config FSL_PCIE_DISABLE_ASPM
 	bool
 
+config FSL_PCIE_RESET
+	bool
+
 config SYS_FSL_QORIQ_CHASSIS1
 	bool
 
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index f385509daf..3522f03009 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -60,7 +60,6 @@
 #define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
 /*
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index ebf44b5529..f9b8e446c1 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -69,7 +69,6 @@
 #define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
 /*
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 1413b3dcfe..bea4021793 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -36,7 +36,6 @@
 #define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 280b873aee..2cbe855235 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -16,7 +16,6 @@
 #define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index be600becfe..b37601c794 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -20,7 +20,6 @@
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 9b3485ed4b..bf27427869 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -16,7 +16,6 @@
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index de5a7ca959..e1f29bf107 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -15,7 +15,6 @@
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 13fbbb3044..e3952f423b 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -27,7 +27,6 @@
 #define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 134ffe5271..88470f69b8 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -127,7 +127,6 @@
 #define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
 /*
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 3ccfeca890..e785826754 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -90,7 +90,6 @@
 #define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3			/* PCIE controller 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
 #define CONFIG_ENABLE_36BIT_PHYS
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 4f6ee22385..1a8b450adc 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -24,7 +24,6 @@
 #define CONFIG_PCIE2		/* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3		/* PCIE controller 3 (slot 3) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 
 #ifndef __ASSEMBLY__
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 9ca384cc0c..7a07679069 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -507,7 +507,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
 #define CONFIG_PCIE4		/* PCIE controller 4 */
-#define CONFIG_FSL_PCIE_RESET   /* pcie reset fix link width 2x-4x*/
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 446e4268ef..77197a1750 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -491,7 +491,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 6a0254a55b..88237ee316 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -17,7 +17,6 @@
 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 
 #if defined(CONFIG_TARTGET_UCP1020T1)
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 1908d35bcc..6d616c3773 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -210,7 +210,6 @@
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 8fda0c1e22..513f6e4767 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -220,7 +220,6 @@
 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 4f48370648..ad1637b5fc 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -35,7 +35,6 @@
 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 9df8604af7..ba613672eb 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -49,7 +49,6 @@
 #define CONFIG_SYS_PCI_64BIT    1	/* enable 64-bit PCI resources */
 #endif
 #ifdef CONFIG_PCIE1
-#define CONFIG_FSL_PCIE_RESET   1	/* need PCIe reset errata */
 #endif
 
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 22dd3c036e..0a87f226f8 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -22,7 +22,6 @@
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 
 /*
  * Multicore config
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index a7c8dc4e33..0389874609 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -22,7 +22,6 @@
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 
 /*
  * Multicore config
-- 
2.17.1

[U-Boot] [PATCHv2 2/8] powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to Kconfig

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Z.q. Hou
> Sent: Thursday, May 23, 2019 5:52 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; bmeng.cn at gmail.com; Jagdish Gediya
> <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com;
> sr at denx.de
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 2/8] powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to
> Kconfig
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Use the Kconfig option to select the PCIe reset errata.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---

This patch has been applied to u-boot-mpc85xx, awaiting upstream.

--pk

[U-Boot] [PATCHv2 3/8] powerpc: mpc85xx: Update the condition to compile PCI routines

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT
and DM_PCI are not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
V2:
 - No change.

 arch/powerpc/cpu/mpc85xx/pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
index 90ccc3427c..1d0213a513 100644
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ b/arch/powerpc/cpu/mpc85xx/pci.c
@@ -12,7 +12,7 @@
 #include <asm/cpm_85xx.h>
 #include <pci.h>
 
-#if !defined(CONFIG_FSL_PCI_INIT)
+#if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI)
 
 #ifndef CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
-- 
2.17.1

[U-Boot] [PATCHv2 3/8] powerpc: mpc85xx: Update the condition to compile PCI routines

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Z.q. Hou
> Sent: Thursday, May 23, 2019 5:52 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; bmeng.cn at gmail.com; Jagdish Gediya
> <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com;
> sr at denx.de
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 3/8] powerpc: mpc85xx: Update the condition to compile PCI
> routines
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT and DM_PCI are
> not enabled.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
This patch has been applied to u-boot-mpc85xx, awaiting upstream.

--pk

[U-Boot] [PATCHv2 4/8] powerpc: T208xQDS: Compile the legacy PCIe routines conditionally

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Compile the legacy PCIe initialization reoutines only when DM_PCI
is not enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
V2:
 - No change.

 board/freescale/t208xqds/pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c
index c761aea0ac..ef26f14c46 100644
--- a/board/freescale/t208xqds/pci.c
+++ b/board/freescale/t208xqds/pci.c
@@ -11,6 +11,7 @@
 #include <fdt_support.h>
 #include <asm/fsl_serdes.h>
 
+#if !defined(CONFIG_DM_PCI)
 void pci_init_board(void)
 {
 	fsl_pcie_init_board(0);
@@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
 {
 	FT_FSL_PCI_SETUP;
 }
+#endif
-- 
2.17.1

[U-Boot] [PATCHv2 4/8] powerpc: T208xQDS: Compile the legacy PCIe routines conditionally

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Z.q. Hou
> Sent: Thursday, May 23, 2019 5:52 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; bmeng.cn at gmail.com; Jagdish Gediya
> <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com;
> sr at denx.de
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 4/8] powerpc: T208xQDS: Compile the legacy PCIe routines
> conditionally
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Compile the legacy PCIe initialization reoutines only when DM_PCI is not
> enabled.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---

This patch has been applied to u-boot-mpc85xx, awaiting upstream.

--pk

[U-Boot] [PATCHv2 5/8] t2080: dts: Added PCIe DT nodes

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

T2080 integrated 4 PCIe controllers, which is compatible with
the PCI Expressâ„¢ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
V2:
 - No change.

 arch/powerpc/dts/t2080.dtsi | 48 +++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi
index db65ea5725..89b2c618ae 100644
--- a/arch/powerpc/dts/t2080.dtsi
+++ b/arch/powerpc/dts/t2080.dtsi
@@ -59,4 +59,52 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie at ffe240000 {
+		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe240000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe250000 {
+		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe260000 {
+		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie at ffe270000 {
+		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe270000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <3>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
 };
-- 
2.17.1

[U-Boot] [PATCHv2 5/8] t2080: dts: Added PCIe DT nodes

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Z.q. Hou
> Sent: Thursday, May 23, 2019 5:52 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; bmeng.cn at gmail.com; Jagdish Gediya
> <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com;
> sr at denx.de
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 5/8] t2080: dts: Added PCIe DT nodes
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> T2080 integrated 4 PCIe controllers, which is compatible with the PCI Expressâ„¢
> Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe
> controller.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---

This patch has been applied to u-boot-mpc85xx, awaiting upstream.

--pk

[U-Boot] [PATCHv2 6/8] dm: pci: add Freescale PowerPC PCIe driver

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Add PCIe DM driver for Freescale PowerPC PCIe controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Add more detail in the PCIE_FSL help info.
 - Sort the included header files.
 - Romve key word 'inline' from fsl_pcie_link_up().
 - Add comments for some members of structure fsl_pcie.
 - Change to determine erratums by IS_ENABLED().
 - Romve unnecessary header file including from pcie_fsl.h.
 - Add info when can't find the DT node to fixup.
 - To avoid compile error, add a null function pci_of_setup()
   when CONFIG_OF_BOARD_SETUP is not enabled. 

 drivers/pci/Kconfig          |   8 +
 drivers/pci/Makefile         |   1 +
 drivers/pci/pcie_fsl.c       | 611 +++++++++++++++++++++++++++++++++++
 drivers/pci/pcie_fsl.h       |  57 ++++
 drivers/pci/pcie_fsl_fixup.c |  51 +++
 5 files changed, 728 insertions(+)
 create mode 100644 drivers/pci/pcie_fsl.c
 create mode 100644 drivers/pci/pcie_fsl.h
 create mode 100644 drivers/pci/pcie_fsl_fixup.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 1521885bde..e679aa1a93 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -60,6 +60,14 @@ config PCIE_DW_MVEBU
 	  Armada-8K SoCs. The PCIe controller on Armada-8K is based on
 	  DesignWare hardware.
 
+config PCIE_FSL
+	bool "FSL PowerPC PCIe support"
+	depends on DM_PCI
+	help
+	  Say Y here if you want to enable PCIe controller support on FSL
+	  PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
+	  This driver does not support SRIO_PCIE_BOOT feature.
+
 config PCI_RCAR_GEN2
 	bool "Renesas RCar Gen2 PCIe driver"
 	depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 4923641895..d984848266 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
 obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
 obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
+obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
 obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
new file mode 100644
index 0000000000..bfb207e788
--- /dev/null
+++ b/drivers/pci/pcie_fsl.c
@@ -0,0 +1,611 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 NXP
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
+ *
+ * PCIe DM U-Boot driver for Freescale PowerPC SoCs
+ * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <mapmem.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include "pcie_fsl.h"
+
+LIST_HEAD(fsl_pcie_list);
+
+static int fsl_pcie_link_up(struct fsl_pcie *pcie);
+
+static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
+{
+	struct udevice *bus = pcie->bus;
+
+	if (!pcie->enabled)
+		return -ENXIO;
+
+	if (PCI_BUS(bdf) < bus->seq)
+		return -EINVAL;
+
+	if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
+		return -EINVAL;
+
+	if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
+		return -EINVAL;
+
+	if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
+				uint offset, ulong *valuep,
+				enum pci_size_t size)
+{
+	struct fsl_pcie *pcie = dev_get_priv(bus);
+	ccsr_fsl_pci_t *regs = pcie->regs;
+	u32 val;
+
+	if (fsl_pcie_addr_valid(pcie, bdf)) {
+		*valuep = pci_get_ff(size);
+		return 0;
+	}
+
+	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
+	val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
+	out_be32(&regs->cfg_addr, val);
+
+	sync();
+
+	switch (size) {
+	case PCI_SIZE_8:
+		*valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
+		break;
+	case PCI_SIZE_16:
+		*valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
+			  (offset & 2)));
+		break;
+	case PCI_SIZE_32:
+		*valuep = in_le32(&regs->cfg_data);
+		break;
+	}
+
+	return 0;
+}
+
+static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+				 uint offset, ulong value,
+				 enum pci_size_t size)
+{
+	struct fsl_pcie *pcie = dev_get_priv(bus);
+	ccsr_fsl_pci_t *regs = pcie->regs;
+	u32 val;
+	u8 val_8;
+	u16 val_16;
+	u32 val_32;
+
+	if (fsl_pcie_addr_valid(pcie, bdf))
+		return 0;
+
+	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
+	val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
+	out_be32(&regs->cfg_addr, val);
+
+	sync();
+
+	switch (size) {
+	case PCI_SIZE_8:
+		val_8 = value;
+		out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
+		break;
+	case PCI_SIZE_16:
+		val_16 = value;
+		out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
+		break;
+	case PCI_SIZE_32:
+		val_32 = value;
+		out_le32(&regs->cfg_data, val_32);
+		break;
+	}
+
+	return 0;
+}
+
+static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
+				     ulong *valuep, enum pci_size_t size)
+{
+	int ret;
+	struct udevice *bus = pcie->bus;
+
+	ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
+				   offset, valuep, size);
+
+	return ret;
+}
+
+static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
+				      ulong value, enum pci_size_t size)
+{
+	struct udevice *bus = pcie->bus;
+
+	return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
+				     offset, value, size);
+}
+
+static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
+					  u8 *valuep)
+{
+	ulong val;
+	int ret;
+
+	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
+	*valuep = val;
+
+	return ret;
+}
+
+static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
+					  u16 *valuep)
+{
+	ulong val;
+	int ret;
+
+	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
+	*valuep = val;
+
+	return ret;
+}
+
+static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
+					   u32 *valuep)
+{
+	ulong val;
+	int ret;
+
+	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
+	*valuep = val;
+
+	return ret;
+}
+
+static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
+					   u8 value)
+{
+	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
+}
+
+static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
+					   u16 value)
+{
+	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
+}
+
+static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
+					    u32 value)
+{
+	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
+}
+
+static int fsl_pcie_link_up(struct fsl_pcie *pcie)
+{
+	ccsr_fsl_pci_t *regs = pcie->regs;
+	u16 ltssm;
+
+	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+		ltssm = (in_be32(&regs->pex_csr0)
+			& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
+		return ltssm == LTSSM_L0_REV3;
+	}
+
+	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
+
+	return ltssm == LTSSM_L0;
+}
+
+static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
+{
+	u8 header_type;
+
+	fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
+
+	return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
+}
+
+static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
+{
+	struct pci_region *io, *mem, *pref;
+
+	pci_get_regions(pcie->bus, &io, &mem, &pref);
+
+	if (mem)
+		set_next_law(mem->phys_start,
+			     law_size_bits(mem->size),
+			     pcie->law_trgt_if);
+
+	if (io)
+		set_next_law(io->phys_start,
+			     law_size_bits(io->size),
+			     pcie->law_trgt_if);
+
+	return 0;
+}
+
+static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
+{
+	ccsr_fsl_pci_t *regs = pcie->regs;
+
+	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+		setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
+		return;
+	}
+
+	fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
+}
+
+static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
+				       int type, u64 phys, u64 bus_addr,
+				       pci_size_t size)
+{
+	ccsr_fsl_pci_t *regs = pcie->regs;
+	pot_t *po = &regs->pot[idx];
+	u32 war, sz;
+
+	if (idx < 0)
+		return -EINVAL;
+
+	out_be32(&po->powbar, phys >> 12);
+	out_be32(&po->potar, bus_addr >> 12);
+#ifdef CONFIG_SYS_PCI_64BIT
+	out_be32(&po->potear, bus_addr >> 44);
+#else
+	out_be32(&po->potear, 0);
+#endif
+
+	sz = (__ilog2_u64((u64)size) - 1);
+	war = POWAR_EN | sz;
+
+	if (type == PCI_REGION_IO)
+		war |= POWAR_IO_READ | POWAR_IO_WRITE;
+	else
+		war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
+
+	out_be32(&po->powar, war);
+
+	return 0;
+}
+
+static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
+				      bool pf, u64 phys, u64 bus_addr,
+				      pci_size_t size)
+{
+	ccsr_fsl_pci_t *regs = pcie->regs;
+	pit_t *pi = &regs->pit[idx];
+	u32 sz = (__ilog2_u64(size) - 1);
+	u32 flag = PIWAR_LOCAL;
+
+	if (idx < 0)
+		return -EINVAL;
+
+	out_be32(&pi->pitar, phys >> 12);
+	out_be32(&pi->piwbar, bus_addr >> 12);
+
+#ifdef CONFIG_SYS_PCI_64BIT
+	out_be32(&pi->piwbear, bus_addr >> 44);
+#else
+	out_be32(&pi->piwbear, 0);
+#endif
+
+	if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434))
+		flag = 0;
+
+	flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+	if (pf)
+		flag |= PIWAR_PF;
+	out_be32(&pi->piwar, flag | sz);
+
+	return 0;
+}
+
+static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
+{
+	struct pci_region *io, *mem, *pref;
+	int idx = 1; /* skip 0 */
+
+	pci_get_regions(pcie->bus, &io, &mem, &pref);
+
+	if (io)
+		/* ATU : OUTBOUND : IO */
+		fsl_pcie_setup_outbound_win(pcie, idx++,
+					    PCI_REGION_IO,
+					    io->phys_start,
+					    io->bus_start,
+					    io->size);
+
+	if (mem)
+		/* ATU : OUTBOUND : MEM */
+		fsl_pcie_setup_outbound_win(pcie, idx++,
+					    PCI_REGION_MEM,
+					    mem->phys_start,
+					    mem->bus_start,
+					    mem->size);
+	return 0;
+}
+
+static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
+{
+	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
+	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
+	u64 sz = min((u64)gd->ram_size, (1ull << 32));
+	pci_size_t pci_sz;
+	int idx;
+
+	if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
+		idx = 2;
+	else
+		idx = 3;
+
+	pci_sz = 1ull << __ilog2_u64(sz);
+
+	dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
+		(u64)bus_start, (u64)phys_start, (u64)sz);
+
+	/* if we aren't an exact power of two match, pci_sz is smaller
+	 * round it up to the next power of two.  We report the actual
+	 * size to pci region tracking.
+	 */
+	if (pci_sz != sz)
+		sz = 2ull << __ilog2_u64(sz);
+
+	fsl_pcie_setup_inbound_win(pcie, idx--, true,
+				   CONFIG_SYS_PCI_MEMORY_PHYS,
+				   CONFIG_SYS_PCI_MEMORY_BUS, sz);
+#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
+	/*
+	 * On 64-bit capable systems, set up a mapping for all of DRAM
+	 * in high pci address space.
+	 */
+	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
+	/* round up to the next largest power of two */
+	if (gd->ram_size > pci_sz)
+		pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
+
+	dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
+		(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
+		(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
+
+	fsl_pcie_setup_inbound_win(pcie, idx--, true,
+				   CONFIG_SYS_PCI_MEMORY_PHYS,
+				   CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
+#endif
+
+	return 0;
+}
+
+static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
+{
+	fsl_pcie_setup_outbound_wins(pcie);
+	fsl_pcie_setup_inbound_wins(pcie);
+
+	return 0;
+}
+
+static int fsl_pcie_init_port(struct fsl_pcie *pcie)
+{
+	ccsr_fsl_pci_t *regs = pcie->regs;
+	u32 val_32;
+	u16 val_16;
+
+	fsl_pcie_init_atmu(pcie);
+
+	if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) {
+		val_32 = 0;
+		fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
+		val_32 &= ~0x03;
+		fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
+		udelay(1);
+	}
+
+	if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) {
+		u16 ltssm;
+		int i;
+
+		if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
+			/* assert PCIe reset */
+			setbits_be32(&regs->pdb_stat, 0x08000000);
+			(void)in_be32(&regs->pdb_stat);
+			udelay(1000);
+			/* clear PCIe reset */
+			clrbits_be32(&regs->pdb_stat, 0x08000000);
+			asm("sync;isync");
+			for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
+				udelay(1000);
+		} else {
+			fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
+			if (ltssm == 1) {
+				/* assert PCIe reset */
+				setbits_be32(&regs->pdb_stat, 0x08000000);
+				(void)in_be32(&regs->pdb_stat);
+				udelay(100);
+				/* clear PCIe reset */
+				clrbits_be32(&regs->pdb_stat, 0x08000000);
+				asm("sync;isync");
+				for (i = 0; i < 100 &&
+				     !fsl_pcie_link_up(pcie); i++)
+					udelay(1000);
+			}
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) &&
+	    !fsl_pcie_link_up(pcie)) {
+		serdes_corenet_t *srds_regs;
+
+		srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+		val_32 = in_be32(&srds_regs->srdspccr0);
+
+		if ((val_32 >> 28) == 3) {
+			int i;
+
+			out_be32(&srds_regs->srdspccr0, 2 << 28);
+			setbits_be32(&regs->pdb_stat, 0x08000000);
+			in_be32(&regs->pdb_stat);
+			udelay(100);
+			clrbits_be32(&regs->pdb_stat, 0x08000000);
+			asm("sync;isync");
+			for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
+				udelay(1000);
+		}
+	}
+
+	/*
+	 * The Read-Only Write Enable bit defaults to 1 instead of 0.
+	 * Set to 0 to protect the read-only registers.
+	 */
+	if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815))
+		clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
+
+	/*
+	 * Enable All Error Interrupts except
+	 * - Master abort (pci)
+	 * - Master PERR (pci)
+	 * - ICCA (PCIe)
+	 */
+	out_be32(&regs->peer, ~0x20140);
+
+	/* set URR, FER, NFER (but not CER) */
+	fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
+	val_32 |= 0xf000e;
+	fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
+
+	/* Clear all error indications */
+	out_be32(&regs->pme_msg_det, 0xffffffff);
+	out_be32(&regs->pme_msg_int_en, 0xffffffff);
+	out_be32(&regs->pedr, 0xffffffff);
+
+	fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
+	if (val_16)
+		fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
+
+	fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
+	if (val_16)
+		fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
+
+	return 0;
+}
+
+static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
+{
+	ccsr_fsl_pci_t *regs = pcie->regs;
+	u32 val;
+
+	setbits_be32(&regs->dbi_ro_wr_en, 0x01);
+	fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);
+	val &= 0xff;
+	val |= PCI_CLASS_BRIDGE_PCI << 16;
+	fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
+	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
+
+	return 0;
+}
+
+static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
+{
+	return fsl_pcie_fixup_classcode(pcie);
+}
+
+static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
+{
+	fsl_pcie_config_ready(pcie);
+
+	return 0;
+}
+
+static int fsl_pcie_probe(struct udevice *dev)
+{
+	struct fsl_pcie *pcie = dev_get_priv(dev);
+	ccsr_fsl_pci_t *regs = pcie->regs;
+	u16 val_16;
+
+	pcie->bus = dev;
+	pcie->block_rev = in_be32(&regs->block_rev1);
+
+	list_add(&pcie->list, &fsl_pcie_list);
+	pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
+	if (!pcie->enabled) {
+		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		return 0;
+	}
+
+	fsl_pcie_setup_law(pcie);
+
+	pcie->mode = fsl_pcie_is_agent(pcie);
+
+	fsl_pcie_init_port(pcie);
+
+	printf("PCIe%d: %s ", pcie->idx, dev->name);
+
+	if (pcie->mode) {
+		printf("Endpoint");
+		fsl_pcie_init_ep(pcie);
+	} else {
+		printf("Root Complex");
+		fsl_pcie_init_rc(pcie);
+	}
+
+	if (!fsl_pcie_link_up(pcie)) {
+		printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
+		return 0;
+	}
+
+	fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
+	printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
+
+	return 0;
+}
+
+static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
+{
+	struct fsl_pcie *pcie = dev_get_priv(dev);
+	int ret;
+
+	pcie->regs = dev_remap_addr(dev);
+	if (!pcie->regs) {
+		pr_err("\"reg\" resource not found\n");
+		return -EINVAL;
+	}
+
+	ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
+	if (ret < 0) {
+		pr_err("\"law_trgt_if\" not found\n");
+		return ret;
+	}
+
+	pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000;
+
+	return 0;
+}
+
+static const struct dm_pci_ops fsl_pcie_ops = {
+	.read_config	= fsl_pcie_read_config,
+	.write_config	= fsl_pcie_write_config,
+};
+
+static const struct udevice_id fsl_pcie_ids[] = {
+	{ .compatible = "fsl,pcie-t2080" },
+	{ }
+};
+
+U_BOOT_DRIVER(fsl_pcie) = {
+	.name = "fsl_pcie",
+	.id = UCLASS_PCI,
+	.of_match = fsl_pcie_ids,
+	.ops = &fsl_pcie_ops,
+	.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
+	.probe = fsl_pcie_probe,
+	.priv_auto_alloc_size = sizeof(struct fsl_pcie),
+};
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
new file mode 100644
index 0000000000..ce2b1afb4d
--- /dev/null
+++ b/drivers/pci/pcie_fsl.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
+ *
+ * PCIe DM U-Boot driver for Freescale PowerPC SoCs
+ * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+ */
+
+#ifndef _PCIE_FSL_H_
+#define _PCIE_FSL_H_
+
+#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
+#define FSL_PCIE_CAP_ID			0x70
+#else
+#define FSL_PCIE_CAP_ID			0x4c
+#endif
+/* PCIe Device Control Register */
+#define PCI_DCR				(FSL_PCIE_CAP_ID + 0x08)
+/* PCIe Device Status Register */
+#define PCI_DSR				(FSL_PCIE_CAP_ID + 0x0a)
+/* PCIe Link Control Register */
+#define PCI_LCR				(FSL_PCIE_CAP_ID + 0x10)
+/* PCIe Link Status Register */
+#define PCI_LSR				(FSL_PCIE_CAP_ID + 0x12)
+
+#ifndef CONFIG_SYS_PCI_MEMORY_BUS
+#define CONFIG_SYS_PCI_MEMORY_BUS	0
+#endif
+
+#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
+#define CONFIG_SYS_PCI_MEMORY_PHYS	0
+#endif
+
+#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
+#define CONFIG_SYS_PCI64_MEMORY_BUS	(64ull * 1024 * 1024 * 1024)
+#endif
+
+#define PEX_CSR0_LTSSM_MASK		0xFC
+#define PEX_CSR0_LTSSM_SHIFT		2
+#define LTSSM_L0_REV3			0x11
+#define LTSSM_L0			0x16
+
+struct fsl_pcie {
+	int idx;
+	struct udevice *bus;
+	void __iomem *regs;
+	u32 law_trgt_if;		/* LAW target ID */
+	u32 block_rev;			/* IP block revision */
+	bool mode;			/* RC&EP mode flag */
+	bool enabled;			/* Enable status */
+	struct list_head list;
+};
+
+extern struct list_head fsl_pcie_list;
+
+#endif /* _PCIE_FSL_H_ */
diff --git a/drivers/pci/pcie_fsl_fixup.c b/drivers/pci/pcie_fsl_fixup.c
new file mode 100644
index 0000000000..1a17436ac0
--- /dev/null
+++ b/drivers/pci/pcie_fsl_fixup.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 NXP
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
+ *
+ * PCIe Kernel DT fixup of DM U-Boot driver for Freescale PowerPC SoCs
+ * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+ */
+
+#include <common.h>
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <dm.h>
+#include <fdt_support.h>
+#include <asm/fsl_pci.h>
+#include <linux/libfdt.h>
+#include "pcie_fsl.h"
+
+static void ft_fsl_pcie_setup(void *blob, struct fsl_pcie *pcie)
+{
+	struct pci_controller *hose = dev_get_uclass_priv(pcie->bus);
+	fdt_addr_t regs_addr;
+	int off;
+
+	regs_addr = dev_read_addr(pcie->bus);
+	off = fdt_node_offset_by_compat_reg(blob, FSL_PCIE_COMPAT, regs_addr);
+	if (off < 0) {
+		printf("%s: Fail to find PCIe node@0x%pa\n",
+		       FSL_PCIE_COMPAT, &regs_addr);
+		return;
+	}
+
+	if (!hose || !pcie->enabled)
+		fdt_del_node(blob, off);
+	else
+		fdt_pci_dma_ranges(blob, off, hose);
+}
+
+/* Fixup Kernel DT for PCIe */
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	struct fsl_pcie *pcie;
+
+	list_for_each_entry(pcie, &fsl_pcie_list, list)
+		ft_fsl_pcie_setup(blob, pcie);
+}
+
+#else
+void pci_of_setup(void *blob, bd_t *bd)
+{
+}
+#endif
-- 
2.17.1

[U-Boot] [PATCHv2 6/8] dm: pci: add Freescale PowerPC PCIe driver

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Z.q. Hou
> Sent: Thursday, May 23, 2019 5:52 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; bmeng.cn at gmail.com; Jagdish Gediya
> <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com;
> sr at denx.de
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 6/8] dm: pci: add Freescale PowerPC PCIe driver
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Add PCIe DM driver for Freescale PowerPC PCIe controllers.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---

Updated copyright!!

This patch has been applied to u-boot-mpc85xx, awaiting upstream.

--pk

[U-Boot] [PATCHv2 7/8] powerpc: T208xQDS: Disable legacy PCIe driver

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Disable legacy PCIe driver and remove unused PCIe macros.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
V2:
 - No change.

 include/configs/T208xQDS.h | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 7a07679069..f58bea7e39 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -507,49 +507,31 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
 #define CONFIG_PCIE4		/* PCIE controller 4 */
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 
 #ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 
-- 
2.17.1

[U-Boot] [PATCHv2 7/8] powerpc: T208xQDS: Disable legacy PCIe driver

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Z.q. Hou
> Sent: Thursday, May 23, 2019 5:52 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; bmeng.cn at gmail.com; Jagdish Gediya
> <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com;
> sr at denx.de
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 7/8] powerpc: T208xQDS: Disable legacy PCIe driver
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Disable legacy PCIe driver and remove unused PCIe macros.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---

Fixed for non PCIe DM build !!

This patch has been applied to u-boot-mpc85xx, awaiting upstream.

--pk

[U-Boot] [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Enable the DM PCIe driver in T2080QDS defconfig.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.

 configs/T2080QDS_NAND_defconfig     | 4 ++++
 configs/T2080QDS_SDCARD_defconfig   | 4 ++++
 configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
 configs/T2080QDS_defconfig          | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 948a05af89..d04e223c23 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -38,6 +38,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 30e87df3bb..7292de750b 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -38,6 +38,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -53,6 +54,9 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 0cccb3a85d..d85cc8d9d1 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -39,6 +39,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 79cf4424b4..df1c5183e5 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -28,6 +28,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
 CONFIG_FSL_CAAM=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -43,6 +44,9 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_E1000=y
 CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_FSL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
-- 
2.17.1

[U-Boot] [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Bin Meng]

On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Enable the DM PCIe driver in T2080QDS defconfig.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
>  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
>
>  configs/T2080QDS_NAND_defconfig     | 4 ++++
>  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
>  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
>  configs/T2080QDS_defconfig          | 4 ++++
>  4 files changed, 16 insertions(+)
>
> diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
> index 948a05af89..d04e223c23 100644
> --- a/configs/T2080QDS_NAND_defconfig
> +++ b/configs/T2080QDS_NAND_defconfig
> @@ -38,6 +38,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
>  CONFIG_OF_CONTROL=y
>  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
>  CONFIG_ENV_IS_IN_NAND=y
> +CONFIG_DM=y
>  CONFIG_FSL_CAAM=y
>  CONFIG_FSL_ESDHC=y
>  CONFIG_MTD_NOR_FLASH=y
> @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_AQUANTIA=y
>  CONFIG_E1000=y
>  CONFIG_MII=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y

I think we should avoid adding DM_PCI_COMPAT.

> +CONFIG_PCIE_FSL=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_FSL_ESPI=y
> diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
> index 30e87df3bb..7292de750b 100644
> --- a/configs/T2080QDS_SDCARD_defconfig
> +++ b/configs/T2080QDS_SDCARD_defconfig
> @@ -38,6 +38,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
>  CONFIG_OF_CONTROL=y
>  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
>  CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_DM=y
>  CONFIG_FSL_CAAM=y
>  CONFIG_FSL_ESDHC=y
>  CONFIG_MTD_NOR_FLASH=y
> @@ -53,6 +54,9 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_AQUANTIA=y
>  CONFIG_E1000=y
>  CONFIG_MII=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y
> +CONFIG_PCIE_FSL=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_FSL_ESPI=y
> diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
> index 0cccb3a85d..d85cc8d9d1 100644
> --- a/configs/T2080QDS_SPIFLASH_defconfig
> +++ b/configs/T2080QDS_SPIFLASH_defconfig
> @@ -39,6 +39,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
>  CONFIG_OF_CONTROL=y
>  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
>  CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_DM=y
>  CONFIG_FSL_CAAM=y
>  CONFIG_FSL_ESDHC=y
>  CONFIG_MTD_NOR_FLASH=y
> @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_AQUANTIA=y
>  CONFIG_E1000=y
>  CONFIG_MII=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y
> +CONFIG_PCIE_FSL=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_FSL_ESPI=y
> diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
> index 79cf4424b4..df1c5183e5 100644
> --- a/configs/T2080QDS_defconfig
> +++ b/configs/T2080QDS_defconfig
> @@ -28,6 +28,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
>  CONFIG_OF_CONTROL=y
>  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
>  CONFIG_ENV_IS_IN_FLASH=y
> +CONFIG_DM=y
>  CONFIG_FSL_CAAM=y
>  CONFIG_FSL_ESDHC=y
>  CONFIG_MTD_NOR_FLASH=y
> @@ -43,6 +44,9 @@ CONFIG_PHYLIB=y
>  CONFIG_PHY_AQUANTIA=y
>  CONFIG_E1000=y
>  CONFIG_MII=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_PCI_COMPAT=y
> +CONFIG_PCIE_FSL=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_SPI=y
>  CONFIG_FSL_ESPI=y
> --

Regards,
Bin

[U-Boot] [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: 2019年5月23日 22:23
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> 
> On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Enable the DM PCIe driver in T2080QDS defconfig.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V2:
> >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> >
> >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> >  configs/T2080QDS_defconfig          | 4 ++++
> >  4 files changed, 16 insertions(+)
> >
> > diff --git a/configs/T2080QDS_NAND_defconfig
> > b/configs/T2080QDS_NAND_defconfig index 948a05af89..d04e223c23
> 100644
> > --- a/configs/T2080QDS_NAND_defconfig
> > +++ b/configs/T2080QDS_NAND_defconfig
> > @@ -38,6 +38,7 @@
> >
> CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),1
> > 28k(dtb),9
> >  CONFIG_OF_CONTROL=y
> >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> >  CONFIG_ENV_IS_IN_NAND=y
> > +CONFIG_DM=y
> >  CONFIG_FSL_CAAM=y
> >  CONFIG_FSL_ESDHC=y
> >  CONFIG_MTD_NOR_FLASH=y
> > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
> >  CONFIG_PHY_AQUANTIA=y
> >  CONFIG_E1000=y
> >  CONFIG_MII=y
> > +CONFIG_DM_PCI=y
> > +CONFIG_DM_PCI_COMPAT=y
> 
> I think we should avoid adding DM_PCI_COMPAT.

Without this macro the non-DM Endpoint driver (such as e1000) won't work.
 
> > +CONFIG_PCIE_FSL=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_FSL_ESPI=y
> > diff --git a/configs/T2080QDS_SDCARD_defconfig
> > b/configs/T2080QDS_SDCARD_defconfig
> > index 30e87df3bb..7292de750b 100644
> > --- a/configs/T2080QDS_SDCARD_defconfig
> > +++ b/configs/T2080QDS_SDCARD_defconfig
> > @@ -38,6 +38,7 @@
> >
> CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),1
> > 28k(dtb),9
> >  CONFIG_OF_CONTROL=y
> >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> >  CONFIG_ENV_IS_IN_MMC=y
> > +CONFIG_DM=y
> >  CONFIG_FSL_CAAM=y
> >  CONFIG_FSL_ESDHC=y
> >  CONFIG_MTD_NOR_FLASH=y
> > @@ -53,6 +54,9 @@ CONFIG_PHYLIB=y
> >  CONFIG_PHY_AQUANTIA=y
> >  CONFIG_E1000=y
> >  CONFIG_MII=y
> > +CONFIG_DM_PCI=y
> > +CONFIG_DM_PCI_COMPAT=y
> > +CONFIG_PCIE_FSL=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_FSL_ESPI=y
> > diff --git a/configs/T2080QDS_SPIFLASH_defconfig
> > b/configs/T2080QDS_SPIFLASH_defconfig
> > index 0cccb3a85d..d85cc8d9d1 100644
> > --- a/configs/T2080QDS_SPIFLASH_defconfig
> > +++ b/configs/T2080QDS_SPIFLASH_defconfig
> > @@ -39,6 +39,7 @@
> >
> CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),1
> > 28k(dtb),9
> >  CONFIG_OF_CONTROL=y
> >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> >  CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_DM=y
> >  CONFIG_FSL_CAAM=y
> >  CONFIG_FSL_ESDHC=y
> >  CONFIG_MTD_NOR_FLASH=y
> > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
> >  CONFIG_PHY_AQUANTIA=y
> >  CONFIG_E1000=y
> >  CONFIG_MII=y
> > +CONFIG_DM_PCI=y
> > +CONFIG_DM_PCI_COMPAT=y
> > +CONFIG_PCIE_FSL=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_FSL_ESPI=y
> > diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
> > index 79cf4424b4..df1c5183e5 100644
> > --- a/configs/T2080QDS_defconfig
> > +++ b/configs/T2080QDS_defconfig
> > @@ -28,6 +28,7 @@
> >
> CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> el),1
> > 28k(dtb),9
> >  CONFIG_OF_CONTROL=y
> >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> >  CONFIG_ENV_IS_IN_FLASH=y
> > +CONFIG_DM=y
> >  CONFIG_FSL_CAAM=y
> >  CONFIG_FSL_ESDHC=y
> >  CONFIG_MTD_NOR_FLASH=y
> > @@ -43,6 +44,9 @@ CONFIG_PHYLIB=y
> >  CONFIG_PHY_AQUANTIA=y
> >  CONFIG_E1000=y
> >  CONFIG_MII=y
> > +CONFIG_DM_PCI=y
> > +CONFIG_DM_PCI_COMPAT=y
> > +CONFIG_PCIE_FSL=y
> >  CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_FSL_ESPI=y
> > --
> 
> Regards,
> Bin

Thanks,
Zhiqiang

[U-Boot] [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Bin Meng]

Hi,

On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> Hi Bin,
>
> Thanks a lot for your comments!
>
> > -----Original Message-----
> > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > Sent: 2019年5月23日 22:23
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> >
> > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > >
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > Enable the DM PCIe driver in T2080QDS defconfig.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > ---
> > > V2:
> > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > >
> > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > >  configs/T2080QDS_defconfig          | 4 ++++
> > >  4 files changed, 16 insertions(+)
> > >
> > > diff --git a/configs/T2080QDS_NAND_defconfig
> > > b/configs/T2080QDS_NAND_defconfig index 948a05af89..d04e223c23
> > 100644
> > > --- a/configs/T2080QDS_NAND_defconfig
> > > +++ b/configs/T2080QDS_NAND_defconfig
> > > @@ -38,6 +38,7 @@
> > >
> > CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > el),1
> > > 28k(dtb),9
> > >  CONFIG_OF_CONTROL=y
> > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > >  CONFIG_ENV_IS_IN_NAND=y
> > > +CONFIG_DM=y
> > >  CONFIG_FSL_CAAM=y
> > >  CONFIG_FSL_ESDHC=y
> > >  CONFIG_MTD_NOR_FLASH=y
> > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
> > >  CONFIG_PHY_AQUANTIA=y
> > >  CONFIG_E1000=y
> > >  CONFIG_MII=y
> > > +CONFIG_DM_PCI=y
> > > +CONFIG_DM_PCI_COMPAT=y
> >
> > I think we should avoid adding DM_PCI_COMPAT.
>
> Without this macro the non-DM Endpoint driver (such as e1000) won't work.

e1000 is a fully DM driver now. Please redo the testing.

Regards,
Bin

[U-Boot] [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Xiaowei Bao]

-----Original Message-----
From: Bin Meng <bmeng.cn@gmail.com> 
Sent: 2019年5月24日 8:11
To: Z.q. Hou <zhiqiang.hou@nxp.com>
Cc: u-boot at lists.denx.de; Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

Caution: EXT Email

Hi,

On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> Hi Bin,
>
> Thanks a lot for your comments!
>
> > -----Original Message-----
> > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > Sent: 2019年5月23日 22:23
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha 
> > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu 
> > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; 
> > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian 
> > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> >
> > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > >
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > Enable the DM PCIe driver in T2080QDS defconfig.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > ---
> > > V2:
> > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > >
> > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > >  configs/T2080QDS_defconfig          | 4 ++++
> > >  4 files changed, 16 insertions(+)
> > >
> > > diff --git a/configs/T2080QDS_NAND_defconfig 
> > > b/configs/T2080QDS_NAND_defconfig index 948a05af89..d04e223c23
> > 100644
> > > --- a/configs/T2080QDS_NAND_defconfig
> > > +++ b/configs/T2080QDS_NAND_defconfig
> > > @@ -38,6 +38,7 @@
> > >
> > CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > el),1
> > > 28k(dtb),9
> > >  CONFIG_OF_CONTROL=y
> > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > >  CONFIG_ENV_IS_IN_NAND=y
> > > +CONFIG_DM=y
> > >  CONFIG_FSL_CAAM=y
> > >  CONFIG_FSL_ESDHC=y
> > >  CONFIG_MTD_NOR_FLASH=y
> > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
> > >  CONFIG_PHY_AQUANTIA=y
> > >  CONFIG_E1000=y
> > >  CONFIG_MII=y
> > > +CONFIG_DM_PCI=y
> > > +CONFIG_DM_PCI_COMPAT=y
> >
> > I think we should avoid adding DM_PCI_COMPAT.
>
> Without this macro the non-DM Endpoint driver (such as e1000) won't work.

e1000 is a fully DM driver now. Please redo the testing.
[Xiaowei Bao] I am not very clear, If someone want to implement the customized device driver(not DM) in u-boot, the driver will not work, yes?

Regards,
Bin

[U-Boot] [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Bin Meng]

On Fri, May 24, 2019 at 10:10 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
>
>
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年5月24日 8:11
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: u-boot at lists.denx.de; Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
>
> Caution: EXT Email
>
> Hi,
>
> On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > Hi Bin,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > Sent: 2019年5月23日 22:23
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> > >
> > > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > > >
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > Enable the DM PCIe driver in T2080QDS defconfig.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > ---
> > > > V2:
> > > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > > >
> > > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > > >  configs/T2080QDS_defconfig          | 4 ++++
> > > >  4 files changed, 16 insertions(+)
> > > >
> > > > diff --git a/configs/T2080QDS_NAND_defconfig
> > > > b/configs/T2080QDS_NAND_defconfig index 948a05af89..d04e223c23
> > > 100644
> > > > --- a/configs/T2080QDS_NAND_defconfig
> > > > +++ b/configs/T2080QDS_NAND_defconfig
> > > > @@ -38,6 +38,7 @@
> > > >
> > > CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > > el),1
> > > > 28k(dtb),9
> > > >  CONFIG_OF_CONTROL=y
> > > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > > >  CONFIG_ENV_IS_IN_NAND=y
> > > > +CONFIG_DM=y
> > > >  CONFIG_FSL_CAAM=y
> > > >  CONFIG_FSL_ESDHC=y
> > > >  CONFIG_MTD_NOR_FLASH=y
> > > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
> > > >  CONFIG_PHY_AQUANTIA=y
> > > >  CONFIG_E1000=y
> > > >  CONFIG_MII=y
> > > > +CONFIG_DM_PCI=y
> > > > +CONFIG_DM_PCI_COMPAT=y
> > >
> > > I think we should avoid adding DM_PCI_COMPAT.
> >
> > Without this macro the non-DM Endpoint driver (such as e1000) won't work.
>
> e1000 is a fully DM driver now. Please redo the testing.
> [Xiaowei Bao] I am not very clear, If someone want to implement the customized device driver(not DM) in u-boot, the driver will not work, yes?

We are going to convert all drivers to DM in U-Boot. There are some
deadlines to be set already. So you don't need consider such non-dm
compatibility.

I guess CONFIG_DM_PCI_COMPAT will be removed once all PCI drivers have
been converted.

Regards,
Bin

[U-Boot] [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Xiaowei Bao]

-----Original Message-----
From: Bin Meng <bmeng.cn@gmail.com> 
Sent: 2019年5月24日 10:14
To: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass <sjg@chromium.org>
Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de; Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>
Subject: Re: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

Caution: EXT Email

On Fri, May 24, 2019 at 10:10 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
>
>
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年5月24日 8:11
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: u-boot at lists.denx.de; Prabhakar Kushwaha 
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu 
> <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; 
> sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian 
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
>
> Caution: EXT Email
>
> Hi,
>
> On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > Hi Bin,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > Sent: 2019年5月23日 22:23
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha 
> > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu 
> > > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; 
> > > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian 
> > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> > >
> > > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > > >
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > Enable the DM PCIe driver in T2080QDS defconfig.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > ---
> > > > V2:
> > > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > > >
> > > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > > >  configs/T2080QDS_defconfig          | 4 ++++
> > > >  4 files changed, 16 insertions(+)
> > > >
> > > > diff --git a/configs/T2080QDS_NAND_defconfig 
> > > > b/configs/T2080QDS_NAND_defconfig index 948a05af89..d04e223c23
> > > 100644
> > > > --- a/configs/T2080QDS_NAND_defconfig
> > > > +++ b/configs/T2080QDS_NAND_defconfig
> > > > @@ -38,6 +38,7 @@
> > > >
> > > CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > > el),1
> > > > 28k(dtb),9
> > > >  CONFIG_OF_CONTROL=y
> > > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > > >  CONFIG_ENV_IS_IN_NAND=y
> > > > +CONFIG_DM=y
> > > >  CONFIG_FSL_CAAM=y
> > > >  CONFIG_FSL_ESDHC=y
> > > >  CONFIG_MTD_NOR_FLASH=y
> > > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y  CONFIG_PHY_AQUANTIA=y  
> > > > CONFIG_E1000=y  CONFIG_MII=y
> > > > +CONFIG_DM_PCI=y
> > > > +CONFIG_DM_PCI_COMPAT=y
> > >
> > > I think we should avoid adding DM_PCI_COMPAT.
> >
> > Without this macro the non-DM Endpoint driver (such as e1000) won't work.
>
> e1000 is a fully DM driver now. Please redo the testing.
> [Xiaowei Bao] I am not very clear, If someone want to implement the customized device driver(not DM) in u-boot, the driver will not work, yes?

We are going to convert all drivers to DM in U-Boot. There are some deadlines to be set already. So you don't need consider such non-dm compatibility.
[Xiaowei Bao] OK, got it, I will remove this macro from all Layerscap platform of NXP, and submit a new patch, thanks a lot.

I guess CONFIG_DM_PCI_COMPAT will be removed once all PCI drivers have been converted.

Regards,
Bin

[U-Boot] [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Prabhakar Kushwaha]

Hi Xiaowei,

> -----Original Message-----
> From: Xiaowei Bao
> Sent: Friday, May 24, 2019 7:47 AM
> To: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de; Prabhakar
> Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>
> Subject: RE: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> 
> 
> 
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年5月24日 10:14
> To: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass <sjg@chromium.org>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de; Prabhakar
> Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>
> Subject: Re: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> 
> Caution: EXT Email
> 
> On Fri, May 24, 2019 at 10:10 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> >
> >
> >
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年5月24日 8:11
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> >
> > Caution: EXT Email
> >
> > Hi,
> >
> > On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > >
> > > Hi Bin,
> > >
> > > Thanks a lot for your comments!
> > >
> > > > -----Original Message-----
> > > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > > Sent: 2019年5月23日 22:23
> > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > > > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > > > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> > > >
> > > > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com>
> wrote:
> > > > >
> > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > >
> > > > > Enable the DM PCIe driver in T2080QDS defconfig.
> > > > >
> > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > ---
> > > > > V2:
> > > > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > > > >
> > > > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > > > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > > > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > > > >  configs/T2080QDS_defconfig          | 4 ++++
> > > > >  4 files changed, 16 insertions(+)
> > > > >
> > > > > diff --git a/configs/T2080QDS_NAND_defconfig
> > > > > b/configs/T2080QDS_NAND_defconfig index 948a05af89..d04e223c23
> > > > 100644
> > > > > --- a/configs/T2080QDS_NAND_defconfig
> > > > > +++ b/configs/T2080QDS_NAND_defconfig
> > > > > @@ -38,6 +38,7 @@
> > > > >
> > > >
> CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > > > el),1
> > > > > 28k(dtb),9
> > > > >  CONFIG_OF_CONTROL=y
> > > > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > > > >  CONFIG_ENV_IS_IN_NAND=y
> > > > > +CONFIG_DM=y
> > > > >  CONFIG_FSL_CAAM=y
> > > > >  CONFIG_FSL_ESDHC=y
> > > > >  CONFIG_MTD_NOR_FLASH=y
> > > > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y  CONFIG_PHY_AQUANTIA=y
> > > > > CONFIG_E1000=y  CONFIG_MII=y
> > > > > +CONFIG_DM_PCI=y
> > > > > +CONFIG_DM_PCI_COMPAT=y
> > > >
> > > > I think we should avoid adding DM_PCI_COMPAT.
> > >
> > > Without this macro the non-DM Endpoint driver (such as e1000) won't work.
> >
> > e1000 is a fully DM driver now. Please redo the testing.
> > [Xiaowei Bao] I am not very clear, If someone want to implement the
> customized device driver(not DM) in u-boot, the driver will not work, yes?
> 
> We are going to convert all drivers to DM in U-Boot. There are some deadlines
> to be set already. So you don't need consider such non-dm compatibility.
> [Xiaowei Bao] OK, got it, I will remove this macro from all Layerscap platform of
> NXP, and submit a new patch, thanks a lot.
> 

Please make sure to test e1000 before sending new patch-set. 

--pk

[U-Boot] [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Xiaowei Bao]

Hi Prabhakar,

-----Original Message-----
From: Prabhakar Kushwaha 
Sent: 2019年5月24日 13:23
To: Xiaowei Bao <xiaowei.bao@nxp.com>; Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>
Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de; wd at denx.de; Shengzhou Liu <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>
Subject: RE: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

Hi Xiaowei,

> -----Original Message-----
> From: Xiaowei Bao
> Sent: Friday, May 24, 2019 7:47 AM
> To: Bin Meng <bmeng.cn@gmail.com>; Simon Glass <sjg@chromium.org>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de; Prabhakar 
> Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu 
> <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; 
> ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>
> Subject: RE: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe 
> driver
> 
> 
> 
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年5月24日 10:14
> To: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass <sjg@chromium.org>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de; Prabhakar 
> Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu 
> <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; 
> ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>
> Subject: Re: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe 
> driver
> 
> Caution: EXT Email
> 
> On Fri, May 24, 2019 at 10:10 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> >
> >
> >
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年5月24日 8:11
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha 
> > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu 
> > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>; 
> > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian 
> > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe 
> > driver
> >
> > Caution: EXT Email
> >
> > Hi,
> >
> > On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > >
> > > Hi Bin,
> > >
> > > Thanks a lot for your comments!
> > >
> > > > -----Original Message-----
> > > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > > Sent: 2019年5月23日 22:23
> > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha 
> > > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu 
> > > > <shengzhou.liu@nxp.com>; Jagdish Gediya 
> > > > <jagdish.gediya@nxp.com>; sjg at chromium.org; 
> > > > ley.foon.tan at intel.com; sr at denx.de; M.h. Lian 
> > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> > > >
> > > > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com>
> wrote:
> > > > >
> > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > >
> > > > > Enable the DM PCIe driver in T2080QDS defconfig.
> > > > >
> > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > ---
> > > > > V2:
> > > > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > > > >
> > > > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > > > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > > > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > > > >  configs/T2080QDS_defconfig          | 4 ++++
> > > > >  4 files changed, 16 insertions(+)
> > > > >
> > > > > diff --git a/configs/T2080QDS_NAND_defconfig 
> > > > > b/configs/T2080QDS_NAND_defconfig index 948a05af89..d04e223c23
> > > > 100644
> > > > > --- a/configs/T2080QDS_NAND_defconfig
> > > > > +++ b/configs/T2080QDS_NAND_defconfig
> > > > > @@ -38,6 +38,7 @@
> > > > >
> > > >
> CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > > > el),1
> > > > > 28k(dtb),9
> > > > >  CONFIG_OF_CONTROL=y
> > > > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > > > >  CONFIG_ENV_IS_IN_NAND=y
> > > > > +CONFIG_DM=y
> > > > >  CONFIG_FSL_CAAM=y
> > > > >  CONFIG_FSL_ESDHC=y
> > > > >  CONFIG_MTD_NOR_FLASH=y
> > > > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y  CONFIG_PHY_AQUANTIA=y 
> > > > > CONFIG_E1000=y  CONFIG_MII=y
> > > > > +CONFIG_DM_PCI=y
> > > > > +CONFIG_DM_PCI_COMPAT=y
> > > >
> > > > I think we should avoid adding DM_PCI_COMPAT.
> > >
> > > Without this macro the non-DM Endpoint driver (such as e1000) won't work.
> >
> > e1000 is a fully DM driver now. Please redo the testing.
> > [Xiaowei Bao] I am not very clear, If someone want to implement the
> customized device driver(not DM) in u-boot, the driver will not work, yes?
> 
> We are going to convert all drivers to DM in U-Boot. There are some 
> deadlines to be set already. So you don't need consider such non-dm compatibility.
> [Xiaowei Bao] OK, got it, I will remove this macro from all Layerscap 
> platform of NXP, and submit a new patch, thanks a lot.
> 

Please make sure to test e1000 before sending new patch-set. 
[Xiaowei Bao] OK


--pk

[U-Boot] [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Z.q. Hou]

Hi Bin and Prabhakar,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: 2019年5月24日 10:14
> To: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass <sjg@chromium.org>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de; Prabhakar
> Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>
> Subject: Re: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> 
> On Fri, May 24, 2019 at 10:10 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> wrote:
> >
> >
> >
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: 2019年5月24日 8:11
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > Subject: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> >
> > Caution: EXT Email
> >
> > Hi,
> >
> > On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > >
> > > Hi Bin,
> > >
> > > Thanks a lot for your comments!
> > >
> > > > -----Original Message-----
> > > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > > Sent: 2019年5月23日 22:23
> > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > > > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > > > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> > > >
> > > > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com>
> wrote:
> > > > >
> > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > >
> > > > > Enable the DM PCIe driver in T2080QDS defconfig.
> > > > >
> > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > ---
> > > > > V2:
> > > > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > > > >
> > > > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > > > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > > > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > > > >  configs/T2080QDS_defconfig          | 4 ++++
> > > > >  4 files changed, 16 insertions(+)
> > > > >
> > > > > diff --git a/configs/T2080QDS_NAND_defconfig
> > > > > b/configs/T2080QDS_NAND_defconfig index 948a05af89..d04e223c23
> > > > 100644
> > > > > --- a/configs/T2080QDS_NAND_defconfig
> > > > > +++ b/configs/T2080QDS_NAND_defconfig
> > > > > @@ -38,6 +38,7 @@
> > > > >
> > > >
> CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > > > el),1
> > > > > 28k(dtb),9
> > > > >  CONFIG_OF_CONTROL=y
> > > > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > > > >  CONFIG_ENV_IS_IN_NAND=y
> > > > > +CONFIG_DM=y
> > > > >  CONFIG_FSL_CAAM=y
> > > > >  CONFIG_FSL_ESDHC=y
> > > > >  CONFIG_MTD_NOR_FLASH=y
> > > > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
> CONFIG_PHY_AQUANTIA=y
> > > > > CONFIG_E1000=y  CONFIG_MII=y
> > > > > +CONFIG_DM_PCI=y
> > > > > +CONFIG_DM_PCI_COMPAT=y
> > > >
> > > > I think we should avoid adding DM_PCI_COMPAT.
> > >
> > > Without this macro the non-DM Endpoint driver (such as e1000) won't
> work.
> >
> > e1000 is a fully DM driver now. Please redo the testing.
> > [Xiaowei Bao] I am not very clear, If someone want to implement the
> customized device driver(not DM) in u-boot, the driver will not work, yes?
> 
> We are going to convert all drivers to DM in U-Boot. There are some
> deadlines to be set already. So you don't need consider such non-dm
> compatibility.
 
To enable e1000 DM driver, I added the DM_ETH to T2080QDS_defconfig, but some
build errors arose, seems FMan driver is not DM compatible. 
The DM e1000 driver works well with DPAA FMan driver disabled.

> I guess CONFIG_DM_PCI_COMPAT will be removed once all PCI drivers have
> been converted.

I think we'd better keep it in defconfig currently, and will remove it when all EP
drivers have been converted.

> 
> Regards,
> Bin

Thanks,
Zhiqiang

[U-Boot] [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Bin Meng]

Hi Zhiqiang,

On Fri, May 24, 2019 at 4:17 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> Hi Bin and Prabhakar,
>
> Thanks a lot for your comments!
>
> > -----Original Message-----
> > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > Sent: 2019年5月24日 10:14
> > To: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass <sjg@chromium.org>
> > Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de; Prabhakar
> > Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>
> > Subject: Re: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> >
> > On Fri, May 24, 2019 at 10:10 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> > wrote:
> > >
> > >
> > >
> > > -----Original Message-----
> > > From: Bin Meng <bmeng.cn@gmail.com>
> > > Sent: 2019年5月24日 8:11
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Subject: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> > >
> > > Caution: EXT Email
> > >
> > > Hi,
> > >
> > > On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > Thanks a lot for your comments!
> > > >
> > > > > -----Original Message-----
> > > > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > > > Sent: 2019年5月23日 22:23
> > > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > > > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > > > > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > > > > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> > > > >
> > > > > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou <zhiqiang.hou@nxp.com>
> > wrote:
> > > > > >
> > > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > >
> > > > > > Enable the DM PCIe driver in T2080QDS defconfig.
> > > > > >
> > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > > ---
> > > > > > V2:
> > > > > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > > > > >
> > > > > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > > > > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > > > > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > > > > >  configs/T2080QDS_defconfig          | 4 ++++
> > > > > >  4 files changed, 16 insertions(+)
> > > > > >
> > > > > > diff --git a/configs/T2080QDS_NAND_defconfig
> > > > > > b/configs/T2080QDS_NAND_defconfig index 948a05af89..d04e223c23
> > > > > 100644
> > > > > > --- a/configs/T2080QDS_NAND_defconfig
> > > > > > +++ b/configs/T2080QDS_NAND_defconfig
> > > > > > @@ -38,6 +38,7 @@
> > > > > >
> > > > >
> > CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > > > > el),1
> > > > > > 28k(dtb),9
> > > > > >  CONFIG_OF_CONTROL=y
> > > > > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > > > > >  CONFIG_ENV_IS_IN_NAND=y
> > > > > > +CONFIG_DM=y
> > > > > >  CONFIG_FSL_CAAM=y
> > > > > >  CONFIG_FSL_ESDHC=y
> > > > > >  CONFIG_MTD_NOR_FLASH=y
> > > > > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
> > CONFIG_PHY_AQUANTIA=y
> > > > > > CONFIG_E1000=y  CONFIG_MII=y
> > > > > > +CONFIG_DM_PCI=y
> > > > > > +CONFIG_DM_PCI_COMPAT=y
> > > > >
> > > > > I think we should avoid adding DM_PCI_COMPAT.
> > > >
> > > > Without this macro the non-DM Endpoint driver (such as e1000) won't
> > work.
> > >
> > > e1000 is a fully DM driver now. Please redo the testing.
> > > [Xiaowei Bao] I am not very clear, If someone want to implement the
> > customized device driver(not DM) in u-boot, the driver will not work, yes?
> >
> > We are going to convert all drivers to DM in U-Boot. There are some
> > deadlines to be set already. So you don't need consider such non-dm
> > compatibility.
>
> To enable e1000 DM driver, I added the DM_ETH to T2080QDS_defconfig, but some
> build errors arose, seems FMan driver is not DM compatible.
> The DM e1000 driver works well with DPAA FMan driver disabled.
>

This is expected. E1000 requires DM_ETH, that means all ethernet
drivers in your system have to be DM. So do you have plan to convert
the FMAN ethernet driver to DM?

> > I guess CONFIG_DM_PCI_COMPAT will be removed once all PCI drivers have
> > been converted.
>
> I think we'd better keep it in defconfig currently, and will remove it when all EP
> drivers have been converted.

Regards,
Bin

[U-Boot] [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Z.q. Hou]

Hi Bin,

> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: 2019年5月24日 17:38
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass <sjg@chromium.org>;
> u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> ley.foon.tan at intel.com; sr at denx.de; M.h. Lian <minghuan.lian@nxp.com>
> Subject: Re: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> 
> Hi Zhiqiang,
> 
> On Fri, May 24, 2019 at 4:17 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > Hi Bin and Prabhakar,
> >
> > Thanks a lot for your comments!
> >
> > > -----Original Message-----
> > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > Sent: 2019年5月24日 10:14
> > > To: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass
> > > <sjg@chromium.org>
> > > Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de; Prabhakar
> > > Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou
> Liu
> > > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > > ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > <minghuan.lian@nxp.com>
> > > Subject: Re: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe
> > > driver
> > >
> > > On Fri, May 24, 2019 at 10:10 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> > > wrote:
> > > >
> > > >
> > > >
> > > > -----Original Message-----
> > > > From: Bin Meng <bmeng.cn@gmail.com>
> > > > Sent: 2019年5月24日 8:11
> > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > > > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > > > sjg at chromium.org; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > Subject: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe
> > > > driver
> > > >
> > > > Caution: EXT Email
> > > >
> > > > Hi,
> > > >
> > > > On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com>
> wrote:
> > > > >
> > > > > Hi Bin,
> > > > >
> > > > > Thanks a lot for your comments!
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > > > > Sent: 2019年5月23日 22:23
> > > > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > > > > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > > > > > <shengzhou.liu@nxp.com>; Jagdish Gediya
> > > > > > <jagdish.gediya@nxp.com>; sjg at chromium.org;
> > > > > > ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe
> > > > > > driver
> > > > > >
> > > > > > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou
> > > > > > <zhiqiang.hou@nxp.com>
> > > wrote:
> > > > > > >
> > > > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > > >
> > > > > > > Enable the DM PCIe driver in T2080QDS defconfig.
> > > > > > >
> > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > > > ---
> > > > > > > V2:
> > > > > > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > > > > > >
> > > > > > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > > > > > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > > > > > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > > > > > >  configs/T2080QDS_defconfig          | 4 ++++
> > > > > > >  4 files changed, 16 insertions(+)
> > > > > > >
> > > > > > > diff --git a/configs/T2080QDS_NAND_defconfig
> > > > > > > b/configs/T2080QDS_NAND_defconfig index
> > > > > > > 948a05af89..d04e223c23
> > > > > > 100644
> > > > > > > --- a/configs/T2080QDS_NAND_defconfig
> > > > > > > +++ b/configs/T2080QDS_NAND_defconfig
> > > > > > > @@ -38,6 +38,7 @@
> > > > > > >
> > > > > >
> > >
> CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > > > > > el),1
> > > > > > > 28k(dtb),9
> > > > > > >  CONFIG_OF_CONTROL=y
> > > > > > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > > > > > >  CONFIG_ENV_IS_IN_NAND=y
> > > > > > > +CONFIG_DM=y
> > > > > > >  CONFIG_FSL_CAAM=y
> > > > > > >  CONFIG_FSL_ESDHC=y
> > > > > > >  CONFIG_MTD_NOR_FLASH=y
> > > > > > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
> > > CONFIG_PHY_AQUANTIA=y
> > > > > > > CONFIG_E1000=y  CONFIG_MII=y
> > > > > > > +CONFIG_DM_PCI=y
> > > > > > > +CONFIG_DM_PCI_COMPAT=y
> > > > > >
> > > > > > I think we should avoid adding DM_PCI_COMPAT.
> > > > >
> > > > > Without this macro the non-DM Endpoint driver (such as e1000)
> > > > > won't
> > > work.
> > > >
> > > > e1000 is a fully DM driver now. Please redo the testing.
> > > > [Xiaowei Bao] I am not very clear, If someone want to implement
> > > > the
> > > customized device driver(not DM) in u-boot, the driver will not work, yes?
> > >
> > > We are going to convert all drivers to DM in U-Boot. There are some
> > > deadlines to be set already. So you don't need consider such non-dm
> > > compatibility.
> >
> > To enable e1000 DM driver, I added the DM_ETH to T2080QDS_defconfig,
> > but some build errors arose, seems FMan driver is not DM compatible.
> > The DM e1000 driver works well with DPAA FMan driver disabled.
> >
> 
> This is expected. E1000 requires DM_ETH, that means all ethernet drivers in
> your system have to be DM. So do you have plan to convert the FMAN
> ethernet driver to DM?

No, I don't, perhaps my colleague is working on this, I will submit a patch to
remove the DM_PCI_COMPAT when all driver has been converted.
> 
> > > I guess CONFIG_DM_PCI_COMPAT will be removed once all PCI drivers
> > > have been converted.
> >
> > I think we'd better keep it in defconfig currently, and will remove it
> > when all EP drivers have been converted.
> 
> Regards,
> Bin

Thanks,
Zhiqiang

[U-Boot] [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Prabhakar Kushwaha]

Hi Bin,

> -----Original Message-----
> From: Z.q. Hou
> Sent: Friday, May 24, 2019 7:42 PM
> To: Bin Meng <bmeng.cn@gmail.com>
> Cc: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass <sjg@chromium.org>;
> u-boot at lists.denx.de; Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>;
> wd at denx.de; Shengzhou Liu <shengzhou.liu@nxp.com>; Jagdish Gediya
> <jagdish.gediya@nxp.com>; ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> <minghuan.lian@nxp.com>
> Subject: RE: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> 
> Hi Bin,
> 
> > -----Original Message-----
> > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > Sent: 2019年5月24日 17:38
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass <sjg@chromium.org>;
> > u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>;
> > wd at denx.de; Shengzhou Liu <shengzhou.liu@nxp.com>; Jagdish Gediya
> > <jagdish.gediya@nxp.com>; ley.foon.tan at intel.com; sr at denx.de; M.h.
> > Lian <minghuan.lian@nxp.com>
> > Subject: Re: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe
> > driver
> >
> > Hi Zhiqiang,
> >
> > On Fri, May 24, 2019 at 4:17 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > >
> > > Hi Bin and Prabhakar,
> > >
> > > Thanks a lot for your comments!
> > >
> > > > -----Original Message-----
> > > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > > Sent: 2019年5月24日 10:14
> > > > To: Xiaowei Bao <xiaowei.bao@nxp.com>; Simon Glass
> > > > <sjg@chromium.org>
> > > > Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> > > > Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; wd at denx.de;
> > > > Shengzhou
> > Liu
> > > > <shengzhou.liu@nxp.com>; Jagdish Gediya <jagdish.gediya@nxp.com>;
> > > > ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > > <minghuan.lian@nxp.com>
> > > > Subject: Re: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable
> > > > PCIe driver
> > > >
> > > > On Fri, May 24, 2019 at 10:10 AM Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > wrote:
> > > > >
> > > > >
> > > > >
> > > > > -----Original Message-----
> > > > > From: Bin Meng <bmeng.cn@gmail.com>
> > > > > Sent: 2019年5月24日 8:11
> > > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > > > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > > > > <shengzhou.liu@nxp.com>; Jagdish Gediya
> > > > > <jagdish.gediya@nxp.com>; sjg at chromium.org;
> > > > > ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > Subject: [EXT] Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe
> > > > > driver
> > > > >
> > > > > Caution: EXT Email
> > > > >
> > > > > Hi,
> > > > >
> > > > > On Fri, May 24, 2019 at 12:04 AM Z.q. Hou <zhiqiang.hou@nxp.com>
> > wrote:
> > > > > >
> > > > > > Hi Bin,
> > > > > >
> > > > > > Thanks a lot for your comments!
> > > > > >
> > > > > > > -----Original Message-----
> > > > > > > From: Bin Meng [mailto:bmeng.cn at gmail.com]
> > > > > > > Sent: 2019年5月23日 22:23
> > > > > > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > > > > > Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
> > > > > > > <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> > > > > > > <shengzhou.liu@nxp.com>; Jagdish Gediya
> > > > > > > <jagdish.gediya@nxp.com>; sjg at chromium.org;
> > > > > > > ley.foon.tan at intel.com; sr at denx.de; M.h. Lian
> > > > > > > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > > > Subject: Re: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe
> > > > > > > driver
> > > > > > >
> > > > > > > On Thu, May 23, 2019 at 8:22 PM Z.q. Hou
> > > > > > > <zhiqiang.hou@nxp.com>
> > > > wrote:
> > > > > > > >
> > > > > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > > > >
> > > > > > > > Enable the DM PCIe driver in T2080QDS defconfig.
> > > > > > > >
> > > > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > > > > ---
> > > > > > > > V2:
> > > > > > > >  - Enable PCIe in NAND flash, SD card and SPI flash boot defconfig.
> > > > > > > >
> > > > > > > >  configs/T2080QDS_NAND_defconfig     | 4 ++++
> > > > > > > >  configs/T2080QDS_SDCARD_defconfig   | 4 ++++
> > > > > > > >  configs/T2080QDS_SPIFLASH_defconfig | 4 ++++
> > > > > > > >  configs/T2080QDS_defconfig          | 4 ++++
> > > > > > > >  4 files changed, 16 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/configs/T2080QDS_NAND_defconfig
> > > > > > > > b/configs/T2080QDS_NAND_defconfig index
> > > > > > > > 948a05af89..d04e223c23
> > > > > > > 100644
> > > > > > > > --- a/configs/T2080QDS_NAND_defconfig
> > > > > > > > +++ b/configs/T2080QDS_NAND_defconfig
> > > > > > > > @@ -38,6 +38,7 @@
> > > > > > > >
> > > > > > >
> > > >
> > CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kern
> > > > > > > el),1
> > > > > > > > 28k(dtb),9
> > > > > > > >  CONFIG_OF_CONTROL=y
> > > > > > > >  CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
> > > > > > > >  CONFIG_ENV_IS_IN_NAND=y
> > > > > > > > +CONFIG_DM=y
> > > > > > > >  CONFIG_FSL_CAAM=y
> > > > > > > >  CONFIG_FSL_ESDHC=y
> > > > > > > >  CONFIG_MTD_NOR_FLASH=y
> > > > > > > > @@ -54,6 +55,9 @@ CONFIG_PHYLIB=y
> > > > CONFIG_PHY_AQUANTIA=y
> > > > > > > > CONFIG_E1000=y  CONFIG_MII=y
> > > > > > > > +CONFIG_DM_PCI=y
> > > > > > > > +CONFIG_DM_PCI_COMPAT=y
> > > > > > >
> > > > > > > I think we should avoid adding DM_PCI_COMPAT.
> > > > > >
> > > > > > Without this macro the non-DM Endpoint driver (such as e1000)
> > > > > > won't
> > > > work.
> > > > >
> > > > > e1000 is a fully DM driver now. Please redo the testing.
> > > > > [Xiaowei Bao] I am not very clear, If someone want to implement
> > > > > the
> > > > customized device driver(not DM) in u-boot, the driver will not work, yes?
> > > >
> > > > We are going to convert all drivers to DM in U-Boot. There are
> > > > some deadlines to be set already. So you don't need consider such
> > > > non-dm compatibility.
> > >
> > > To enable e1000 DM driver, I added the DM_ETH to T2080QDS_defconfig,
> > > but some build errors arose, seems FMan driver is not DM compatible.
> > > The DM e1000 driver works well with DPAA FMan driver disabled.
> > >
> >
> > This is expected. E1000 requires DM_ETH, that means all ethernet
> > drivers in your system have to be DM. So do you have plan to convert
> > the FMAN ethernet driver to DM?
> 
> No, I don't, perhaps my colleague is working on this, I will submit a patch to
> remove the DM_PCI_COMPAT when all driver has been converted.
> >

Considering there is no immediate plan to move FMAN ethernet to DM model.
There is no point of holding this patch series.

I am planning to accept this patch series.

Please do let us know, if you have any further review comments/concern..

--pk 

[U-Boot] [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Z.q. Hou
> Sent: Thursday, May 23, 2019 5:53 PM
> To: u-boot at lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; wd at denx.de; Shengzhou Liu
> <shengzhou.liu@nxp.com>; bmeng.cn at gmail.com; Jagdish Gediya
> <jagdish.gediya@nxp.com>; sjg at chromium.org; ley.foon.tan at intel.com;
> sr at denx.de
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 8/8] configs: T2080QDS: Enable PCIe driver
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Enable the DM PCIe driver in T2080QDS defconfig.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---

Run savedefonfing and enabled for other 2 configs

This patch has been applied to u-boot-mpc85xx, awaiting upstream.

--pk