From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sumit Garg Date: Wed, 30 Aug 2017 08:53:53 +0000 Subject: [U-Boot] [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction In-Reply-To: References: <1503990107-28658-1-git-send-email-sumit.garg@nxp.com> <1503990107-28658-2-git-send-email-sumit.garg@nxp.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de < snip > > >> On 08/29/2017 12:02 AM, Sumit Garg wrote: > >>> Using changes in this patch we were able to reduce approx 8k size of > >>> u-boot-spl.bin image. Following is breif description of changes to > >>> reduce SPL size: > >>> 1. Changes in board/freescale/ls1088a/Makefile to remove > >>> compilation of eth.c and cpld.c in case of SPL build. > >>> 2. Changes in board/freescale/ls1088a/ls1088a.c to keep > >>> board_early_init_f funcations in case of SPL build. > >>> 3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver > >>> specific macros due to which static data was being compiled in > >>> case of SPL build. > >>> 4. Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is > >>> not being enabled in case of SPL image but was compiled in to > >>> add redundant code. > >>> > >>> Signed-off-by: Sumit Garg > >>> --- > >>> > >>> Dependent on ls1088 base SD boot target. Also dependent on ls1088 > >>> QPSI secure boot target. > >>> > >>> board/freescale/ls1088a/Makefile | 4 +++- > >>> board/freescale/ls1088a/ls1088a.c | 14 ++++++++------ > >>> include/configs/ls1088a_common.h | 20 ++++++++++++++++++++ > >>> include/configs/ls1088ardb.h | 20 ++++++++++++++++++++ > >>> 4 files changed, 51 insertions(+), 7 deletions(-) > >>> > >>> diff --git a/board/freescale/ls1088a/Makefile > >>> b/board/freescale/ls1088a/Makefile > >>> index bdcce9e..0e15031 100644 > >>> --- a/board/freescale/ls1088a/Makefile > >>> +++ b/board/freescale/ls1088a/Makefile > >>> @@ -5,6 +5,8 @@ > >>> # > >>> > >>> obj-y += ls1088a.o > >>> +obj-y += ddr.o > >>> +ifndef CONFIG_SPL_BUILD > >>> obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o > >>> obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y += > >>> ddr.o > >>> +endif > >>> diff --git a/board/freescale/ls1088a/ls1088a.c > >>> b/board/freescale/ls1088a/ls1088a.c > >>> index 1860f9c..1c28ab4 100644 > >>> --- a/board/freescale/ls1088a/ls1088a.c > >>> +++ b/board/freescale/ls1088a/ls1088a.c > >>> @@ -24,6 +24,13 @@ > >>> > >>> DECLARE_GLOBAL_DATA_PTR; > >>> > >>> +int board_early_init_f(void) > >>> +{ > >>> + fsl_lsch3_early_init_f(); > >>> + return 0; > >>> +} > >>> + > >>> +#if !defined(CONFIG_SPL_BUILD) > >>> unsigned long long get_qixis_addr(void) > >>> { > >>> unsigned long long addr; > >>> @@ -324,12 +331,6 @@ int board_init(void) > >>> return 0; > >>> } > >>> > >>> -int board_early_init_f(void) > >>> -{ > >>> - fsl_lsch3_early_init_f(); > >>> - return 0; > >>> -} > >>> - > >>> void detail_board_ddr_info(void) > >>> { > >>> puts("\nDDR "); > >>> @@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd) > >>> return 0; > >>> } > >>> #endif > >>> +#endif /* defined(CONFIG_SPL_BUILD) */ > >>> diff --git a/include/configs/ls1088a_common.h > >>> b/include/configs/ls1088a_common.h > >>> index 63b69f8..fb4c852 100644 > >>> --- a/include/configs/ls1088a_common.h > >>> +++ b/include/configs/ls1088a_common.h > >>> @@ -7,6 +7,20 @@ > >>> #ifndef __LS1088_COMMON_H > >>> #define __LS1088_COMMON_H > >>> > >>> +/* SPL build */ > >>> +#ifdef CONFIG_SPL_BUILD > >>> +#define SPL_NO_BOARDINFO > >>> +#define SPL_NO_QIXIS > >>> +#define SPL_NO_PCI > >>> +#define SPL_NO_ENV > >>> +#define SPL_NO_RTC > >>> +#define SPL_NO_USB > >>> +#define SPL_NO_SATA > >>> +#define SPL_NO_QSPI > >>> +#define SPL_NO_IFC > >>> +#define CONFIG_SYS_DCACHE_OFF > >> > >> How much space can you save with data cache off? I prefer to leave > >> the cache on. Cache is used if PPA is loaded in SPL stage for boost booting > speed. > >> > >> York > > > > As we discussed earlier too, dcache was not enabled in SPL for our layerscape > platforms. > > That was a mistake when SPL targets were added. It should be enabled. > As I said, if you load PPA in SPL, cache will be enabled for EL2. You didn't do it > because booting performance is not a concern. If you enable falcon boot, this is > required. Ok. BTW, do you think latest PPA which claims whole of OCRAM could work with SPL. I saw crashes in SPL on ls1043ardb with latest PPA enabled in SPL upstream u-boot. As per my understanding, shouldn't we enable cache as part of main u-boot image running in EL2? Also in case of SD, it uses DMA to copy main u-boot image or kernel in case of falcon boot to DDR. I am not sure how much booting performance gain can we get by enabling dcache in SPL. > > > > > Also we do need more space (approx.. 6KB) on OCRAM for header. As > > currently we are only supporting single key in header (Max Size: 4KB) > > for validation. But actual use-case requires SRK table (8 keys) in header (Size: > 10KB). > > > > Total Available OCRAM for SPL image and header: 88KB > > > > Current SPL image size with GCC 5.4.1 tool-chain: 84KB > > Current SPL header size with GCC 5.4.1 tool-chain: 4KB > > > > Required SPL header size with GCC 5.4.1 tool-chain: 10KB > > > > So we need to reduce SPL image size by 6KB more. > > > > I understand the difficulty to fit secure boot into OCRAM. Please try GCC 6. It > has better optimization. > > York Sure I will use GCC 6 for upstream. But for LSDK, we have to stick with GCCC 5.4.1 for now. Sumit