From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752855AbcCIJMI (ORCPT ); Wed, 9 Mar 2016 04:12:08 -0500 Received: from mail-db3on0082.outbound.protection.outlook.com ([157.55.234.82]:38501 "EHLO emea01-db3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751300AbcCIJLz convert rfc822-to-8bit (ORCPT ); Wed, 9 Mar 2016 04:11:55 -0500 From: Minghuan Lian To: Rob Herring , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" CC: Marc Zyngier , Thomas Gleixner , Jason Cooper , Roy Zang , Mingkai Hu , Stuart Yoder , Yang-Leo Li Subject: RE: [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI Thread-Topic: [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI Thread-Index: AQHReCJWBdbchp3730mJjC5ZcE28Hp9Q0KpQ Date: Wed, 9 Mar 2016 08:57:34 +0000 Message-ID: References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> In-Reply-To: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=nxp.com; x-originating-ip: [199.59.226.141] x-ms-office365-filtering-correlation-id: 747f3cb2-c50d-4e5e-0fa8-08d347f8db95 x-microsoft-exchange-diagnostics: 1;VI1PR04MB1024;5:xKd/0Jr4pughpfQawt6gzO1/EHZhNLi35xLRvrKs2ZtJtR/+M3LlsTv4HgUuS75ej4Dl9kRxq2gBCa9/vRb0bBv855jEwC36yNBTYVCMDYVLMyvkrahFyET0v6K6fbP9C0M/RqkSDKvH0EwHQnw3CA==;24:Zx7XIur00aK2ocOJSg7EPhainhzO9t1qeRqsLOe0SfqEzquLea5l1xDKmzvPSbMwiDDk2fRR5r2dGmbGfHM7R1GA0Rs9udSPU2aeEfEWLc4= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:VI1PR04MB1024; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001);SRVR:VI1PR04MB1024;BCL:0;PCL:0;RULEID:;SRVR:VI1PR04MB1024; x-forefront-prvs: 0876988AF0 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(54534003)(13464003)(377454003)(66066001)(586003)(76176999)(50986999)(54356999)(5002640100001)(1096002)(1220700001)(74316001)(33656002)(102836003)(6116002)(3846002)(106116001)(86362001)(5004730100002)(5008740100001)(2201001)(10400500002)(4326007)(81166005)(5001770100001)(3660700001)(92566002)(11100500001)(5003600100002)(3280700002)(2950100001)(2900100001)(189998001)(76576001)(87936001)(122556002)(19580405001)(2906002)(19580395003)(77096005)(2501003);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR04MB1024;H:VI1PR04MB1615.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Mar 2016 08:57:34.9406 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1024 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob Herring, Could you help to review this patch? Thanks a lot. Regards, Minghuan > -----Original Message----- > From: Minghuan Lian [mailto:Minghuan.Lian@nxp.com] > Sent: Monday, March 07, 2016 11:36 AM > To: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Cc: Marc Zyngier ; Thomas Gleixner > ; Jason Cooper ; Roy Zang > ; Mingkai Hu ; Stuart Yoder > ; Yang-Leo Li ; Minghuan Lian > > Subject: [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI > > Some Layerscape SoCs use a simple MSI controller implementation. > It contains only two SCFG register to trigger and describe a > group 32 MSI interrupts. The patch adds bindings to describe > the controller. > > Signed-off-by: Minghuan Lian > --- > change log: > v4: add interrupt-parent description > v3-v1: no change > > .../interrupt-controller/fsl,ls-scfg-msi.txt | 30 > ++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt > > diff --git > a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt > b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt > new file mode 100644 > index 0000000..9e38949 > --- /dev/null > +++ > b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt > @@ -0,0 +1,30 @@ > +* Freescale Layerscape SCFG PCIe MSI controller > + > +Required properties: > + > +- compatible: should be "fsl,-msi" to identify > + Layerscape PCIe MSI controller block such as: > + "fsl,1s1021a-msi" > + "fsl,1s1043a-msi" > +- msi-controller: indicates that this is a PCIe MSI controller node > +- reg: physical base address of the controller and length of memory mapped. > +- interrupts: an interrupt to the parent interrupt controller. > + > +Optional properties: > +- interrupt-parent: the phandle to the parent interrupt controller. > + > +This interrupt controller hardware is a second level interrupt controller that > +is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based > +platforms. If interrupt-parent is not provided, the default parent interrupt > +controller will be used. > +Each PCIe node needs to have property msi-parent that points to > +MSI controller node > + > +Examples: > + > + msi1: msi-controller@1571000 { > + compatible = "fsl,1s1043a-msi"; > + reg = <0x0 0x1571000 0x0 0x8>, > + msi-controller; > + interrupts = <0 116 0x4>; > + }; > -- > 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: minghuan.lian@nxp.com (Minghuan Lian) Date: Wed, 9 Mar 2016 08:57:34 +0000 Subject: [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI In-Reply-To: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Rob Herring, Could you help to review this patch? Thanks a lot. Regards, Minghuan > -----Original Message----- > From: Minghuan Lian [mailto:Minghuan.Lian at nxp.com] > Sent: Monday, March 07, 2016 11:36 AM > To: linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org > Cc: Marc Zyngier ; Thomas Gleixner > ; Jason Cooper ; Roy Zang > ; Mingkai Hu ; Stuart Yoder > ; Yang-Leo Li ; Minghuan Lian > > Subject: [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI > > Some Layerscape SoCs use a simple MSI controller implementation. > It contains only two SCFG register to trigger and describe a > group 32 MSI interrupts. The patch adds bindings to describe > the controller. > > Signed-off-by: Minghuan Lian > --- > change log: > v4: add interrupt-parent description > v3-v1: no change > > .../interrupt-controller/fsl,ls-scfg-msi.txt | 30 > ++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt > > diff --git > a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt > b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt > new file mode 100644 > index 0000000..9e38949 > --- /dev/null > +++ > b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt > @@ -0,0 +1,30 @@ > +* Freescale Layerscape SCFG PCIe MSI controller > + > +Required properties: > + > +- compatible: should be "fsl,-msi" to identify > + Layerscape PCIe MSI controller block such as: > + "fsl,1s1021a-msi" > + "fsl,1s1043a-msi" > +- msi-controller: indicates that this is a PCIe MSI controller node > +- reg: physical base address of the controller and length of memory mapped. > +- interrupts: an interrupt to the parent interrupt controller. > + > +Optional properties: > +- interrupt-parent: the phandle to the parent interrupt controller. > + > +This interrupt controller hardware is a second level interrupt controller that > +is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based > +platforms. If interrupt-parent is not provided, the default parent interrupt > +controller will be used. > +Each PCIe node needs to have property msi-parent that points to > +MSI controller node > + > +Examples: > + > + msi1: msi-controller at 1571000 { > + compatible = "fsl,1s1043a-msi"; > + reg = <0x0 0x1571000 0x0 0x8>, > + msi-controller; > + interrupts = <0 116 0x4>; > + }; > -- > 1.9.1