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From: York Sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?
Date: Tue, 29 Aug 2017 14:59:37 +0000	[thread overview]
Message-ID: <VI1PR04MB2078979E1A7EE204600693CC9A9F0@VI1PR04MB2078.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1504003621.4350.49.camel@infinera.com>

On 08/29/2017 03:47 AM, Joakim Tjernlund wrote:
> As we are looking at PCI stuff ATM I would like to ask
> about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is setup
> at all for E500 but I THINK this is required.
> 
> In 83xx one do:
> get_clocks();
> /* Configure the PCIE controller core clock ratio */
> out_le32(hose_cfg_base + PEX_GCLK_RATIO,
> (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
> / 1000000) * 16) / 333);
> udelay(1000000);
> 
> Any clues?
> 

Jocke,

P2010 has SerDes. With PCIe, SerDes uses 100MHz reference clock. Please 
see reference manual "SerDes reference clock configuration".

York

      parent reply	other threads:[~2017-08-29 14:59 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-29 10:47 Joakim Tjernlund
2017-08-29 13:21 ` Joakim Tjernlund
2017-08-29 15:43   ` York Sun
2017-08-29 17:06     ` Joakim Tjernlund
2017-08-29 17:33       ` York Sun
2017-08-30 13:05         ` Joakim Tjernlund
2017-08-30 15:25           ` York Sun
2017-08-30 16:04             ` Joakim Tjernlund
2017-09-05 12:45             ` Joakim Tjernlund
2017-09-06  9:36               ` Mingkai Hu
2017-09-06 12:22                 ` Joakim Tjernlund
2017-09-07  6:45               ` Mingkai Hu
2017-09-07  6:55                 ` Joakim Tjernlund
2017-09-07  7:16                   ` Mingkai Hu
2017-08-29 14:59 ` York Sun [this message]

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