[U-Boot] [PATCH 1/4 v3] armv8: fsl: remove sata support

[U-Boot] [PATCH 1/4 v3] armv8: fsl: remove sata support

[andy.tang at nxp.com]

From: Yuantian Tang <andy.tang@nxp.com>

Remove the old implementation in order to enable DM for sata

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
v3:
    - rebase to latest code
v2:
    - no changes

 arch/arm/cpu/armv8/fsl-layerscape/soc.c        |   54 ------------------------
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   32 --------------
 2 files changed, 0 insertions(+), 86 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index bfd6639..8028d52 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,8 +6,6 @@
 #include <common.h>
 #include <fsl_immap.h>
 #include <fsl_ifc.h>
-#include <ahci.h>
-#include <scsi.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <asm/io.h>
@@ -330,36 +328,6 @@ void fsl_lsch3_early_init_f(void)
 #endif
 }
 
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
-	struct ccsr_ahci __iomem *ccsr_ahci;
-
-#ifdef CONFIG_SYS_SATA2
-	ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
-	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
-	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
-	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-#endif
-
-#ifdef CONFIG_SYS_SATA1
-	ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
-	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
-	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
-	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
-	ahci_init((void __iomem *)CONFIG_SYS_SATA1);
-	scsi_scan(false);
-#endif
-
-	return 0;
-}
-#endif
-
 /* Get VDD in the unit mV from voltage ID */
 int get_core_volt_from_fuse(void)
 {
@@ -400,25 +368,6 @@ int get_core_volt_from_fuse(void)
 }
 
 #elif defined(CONFIG_FSL_LSCH2)
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
-	struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
-
-	/* Disable SATA ECC */
-	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
-	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
-	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
-	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
-	ahci_init((void __iomem *)CONFIG_SYS_SATA);
-	scsi_scan(false);
-
-	return 0;
-}
-#endif
 
 static void erratum_a009929(void)
 {
@@ -719,9 +668,6 @@ int qspi_ahb_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-#ifdef CONFIG_SCSI_AHCI_PLAT
-	sata_init();
-#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
 	fsl_setenv_chain_of_trust();
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 9a219a6..6e3a420 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -85,39 +85,7 @@ struct cpu_type {
 #define SVR_DEV(svr)		((svr) >> 8)
 #define IS_SVR_DEV(svr, dev)	(((svr) >> 16) == (dev))
 
-/* ahci port register default value */
-#define AHCI_PORT_PHY_1_CFG    0xa003fffe
-#define AHCI_PORT_PHY2_CFG	0x28184d1f
-#define AHCI_PORT_PHY3_CFG	0x0e081509
-#define AHCI_PORT_TRANS_CFG    0x08000029
-#define AHCI_PORT_AXICC_CFG	0x3fffffff
-
 #ifndef __ASSEMBLY__
-/* AHCI (sata) register map */
-struct ccsr_ahci {
-	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
-	u32 pcfg;	/* port config */
-	u32 ppcfg;	/* port phy1 config */
-	u32 pp2c;	/* port phy2 config */
-	u32 pp3c;	/* port phy3 config */
-	u32 pp4c;	/* port phy4 config */
-	u32 pp5c;	/* port phy5 config */
-	u32 axicc;	/* AXI cache control */
-	u32 paxic;	/* port AXI config */
-	u32 axipc;	/* AXI PROT control */
-	u32 ptc;	/* port Trans Config */
-	u32 pts;	/* port Trans Status */
-	u32 plc;	/* port link config */
-	u32 plc1;	/* port link config1 */
-	u32 plc2;	/* port link config2 */
-	u32 pls;	/* port link status */
-	u32 pls1;	/* port link status1 */
-	u32 pcmdc;	/* port CMD config */
-	u32 ppcs;	/* port phy control status */
-	u32 pberr;	/* port 0/1 BIST error */
-	u32 cmds;	/* port 0/1 CMD status error */
-};
-
 #ifdef CONFIG_FSL_LSCH3
 void fsl_lsch3_early_init_f(void);
 int get_core_volt_from_fuse(void);
-- 
1.7.1

[U-Boot] [PATCH 2/4 v3] armv8: dts: fsl-ls1012a: add sata node support

[andy.tang at nxp.com]

From: Yuantian Tang <andy.tang@nxp.com>

One ls1012a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
v3:
    - no changes
v2:
    - add qds and 2g5rdb board support

 arch/arm/dts/fsl-ls1012a-2g5rdb.dts |    4 ++++
 arch/arm/dts/fsl-ls1012a-qds.dtsi   |    4 ++++
 arch/arm/dts/fsl-ls1012a-rdb.dtsi   |    4 ++++
 arch/arm/dts/fsl-ls1012a.dtsi       |    8 ++++++++
 4 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
index db23cf8..cdd4ce4 100644
--- a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
@@ -40,3 +40,7 @@
 &duart0 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
index d069b60..661af0e 100644
--- a/arch/arm/dts/fsl-ls1012a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -125,3 +125,7 @@
 	status = "okay";
 	phy_type = "ulpi";
 };
+
+&sata {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
index 201e5fa..757e2eb 100644
--- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -34,3 +34,7 @@
 &duart0 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index be99076..f22cbf4 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -134,6 +134,14 @@
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
+		sata: sata at 3200000 {
+			compatible = "fsl,ls1012a-ahci";
+			reg = <0x0 0x3200000 0x0 0x10000>;
+			interrupts = <0 69 4>;
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
 		usb0: usb2 at 8600000 {
 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 			reg = <0x0 0x8600000 0x0 0x1000>;
-- 
1.7.1

[U-Boot] [PATCH 3/4 v3] scsi: ceva: add ls1012a soc support

[andy.tang at nxp.com]

From: Yuantian Tang <andy.tang@nxp.com>

Make the code structure more general so that more socs can be
added easily and also remove speed limitation restriction.
Add the ls1012a sata support as well.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
	(with and without CONFIG_OF_LIVE on zynqmp zcu102)
---
v3:
    - remove #include <asm/arch/hardware.h> to fix compling warning
v2:
    - refine the commit message
    - use live tree functions

 drivers/ata/sata_ceva.c |   87 ++++++++++++++++++++++++++++-------------------
 1 files changed, 52 insertions(+), 35 deletions(-)

diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index a7d45e8..047cff7 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -7,8 +7,6 @@
 #include <dm.h>
 #include <ahci.h>
 #include <scsi.h>
-#include <asm/arch/hardware.h>
-
 #include <asm/io.h>
 
 /* Vendor Specific Register Offsets */
@@ -18,6 +16,7 @@
 #define AHCI_VEND_PP3C  0xB0
 #define AHCI_VEND_PP4C  0xB4
 #define AHCI_VEND_PP5C  0xB8
+#define AHCI_VEND_AXICC 0xBc
 #define AHCI_VEND_PAXIC 0xC0
 #define AHCI_VEND_PTC   0xC8
 
@@ -72,45 +71,57 @@
 #define DRV_NAME	"ahci-ceva"
 #define CEVA_FLAG_BROKEN_GEN2	1
 
+/* flag bit definition */
+#define FLAG_COHERENT	1
+
+/* register config value */
+#define CEVA_PHY1_CFG	0xa003fffe
+#define CEVA_PHY2_CFG	0x28184d1f
+#define CEVA_PHY3_CFG	0x0e081509
+#define CEVA_TRANS_CFG	0x08000029
+#define CEVA_AXICC_CFG	0x3fffffff
+
+/* ecc addr-val pair */
+#define ECC_DIS_ADDR_CH2	0x80000000
+#define ECC_DIS_VAL_CH2	0x20140520
+
+enum ceva_soc {
+	CEVA_1V84,
+	CEVA_LS1012A,
+};
+
 struct ceva_sata_priv {
 	ulong base;
+	enum ceva_soc soc;
+	ulong flag;
 };
 
-static int ceva_init_sata(ulong mmio)
+static int ceva_init_sata(struct ceva_sata_priv *priv)
 {
+	ulong base = priv->base;
 	ulong tmp;
-	int i;
-
-	/*
-	 * AXI Data bus width to 64
-	 * Set Mem Addr Read, Write ID for data transfers
-	 * Transfer limit to 72 DWord
-	 */
-	tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
-	writel(tmp, mmio + AHCI_VEND_PAXIC);
-
-	/* Set AHCI Enable */
-	tmp = readl(mmio + HOST_CTL);
-	tmp |= HOST_AHCI_EN;
-	writel(tmp, mmio + HOST_CTL);
-
-	for (i = 0; i < NR_PORTS; i++) {
-		/* TPSS TPRS scalars, CISE and Port Addr */
-		tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
-		writel(tmp, mmio + AHCI_VEND_PCFG);
-
-		/* Port Phy Cfg register enables */
-		tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
-		writel(tmp, mmio + AHCI_VEND_PPCFG);
 
-		/* Rx Watermark setting  */
+	switch (priv->soc) {
+	case CEVA_1V84:
+		tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+		writel(tmp, base + AHCI_VEND_PAXIC);
+		tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
+		writel(tmp, base + AHCI_VEND_PCFG);
+		tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
+		writel(tmp, base + AHCI_VEND_PPCFG);
 		tmp = PTC_RX_WM_VAL | PTC_RSVD;
-		writel(tmp, mmio + AHCI_VEND_PTC);
-
-		/* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
-		tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
-		writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
+		writel(tmp, base + AHCI_VEND_PTC);
+		break;
+
+	case CEVA_LS1012A:
+		writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
+		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
+		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
+		if (priv->flag & FLAG_COHERENT)
+			writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
+		break;
 	}
+
 	return 0;
 }
 
@@ -125,13 +136,14 @@ static int sata_ceva_probe(struct udevice *dev)
 {
 	struct ceva_sata_priv *priv = dev_get_priv(dev);
 
-	ceva_init_sata(priv->base);
+	ceva_init_sata(priv);
 
 	return ahci_probe_scsi(dev, priv->base);
 }
 
 static const struct udevice_id sata_ceva_ids[] = {
-	{ .compatible = "ceva,ahci-1v84" },
+	{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
+	{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
 	{ }
 };
 
@@ -139,10 +151,15 @@ static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ceva_sata_priv *priv = dev_get_priv(dev);
 
-	priv->base = devfdt_get_addr(dev);
+	if (dev_read_bool(dev, "dma-coherent"))
+		priv->flag |= FLAG_COHERENT;
+
+	priv->base = dev_read_addr(dev);
 	if (priv->base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
+	priv->soc = dev_get_driver_data(dev);
+
 	return 0;
 }
 
-- 
1.7.1

[U-Boot] [PATCH 4/4 v3] arm64: ls1012a: enable DM support for sata

[andy.tang at nxp.com]

From: Yuantian Tang <andy.tang@nxp.com>

Enable related configs to support sata DM feature.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
v3:
    - no changes
v2:
    - add 2g5rdb and qds board support

 configs/ls1012a2g5rdb_qspi_defconfig          |    6 +++++-
 configs/ls1012aqds_qspi_defconfig             |    7 ++++++-
 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig |    7 ++++++-
 configs/ls1012ardb_qspi_defconfig             |    7 ++++++-
 4 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index 37b63ff..223256e 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -29,7 +29,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
@@ -44,3 +44,7 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 1f9b76a..7ade3da 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -34,7 +34,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SCSI_AHCI=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
@@ -56,3 +56,8 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index 7dcfaae..4e3d58a 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -31,7 +31,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
@@ -53,3 +53,8 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 6a8485c..7589431 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -30,7 +30,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
@@ -51,3 +51,8 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
-- 
1.7.1

[U-Boot] [PATCH 1/4 v3] armv8: fsl: remove sata support

[Simon Glass]

On 13 July 2018 at 03:25,  <andy.tang@nxp.com> wrote:
> From: Yuantian Tang <andy.tang@nxp.com>
>
> Remove the old implementation in order to enable DM for sata
>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> ---
> v3:
>     - rebase to latest code
> v2:
>     - no changes
>
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c        |   54 ------------------------
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h |   32 --------------
>  2 files changed, 0 insertions(+), 86 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 2/4 v3] armv8: dts: fsl-ls1012a: add sata node support

[Simon Glass]

On 13 July 2018 at 03:25,  <andy.tang@nxp.com> wrote:
> From: Yuantian Tang <andy.tang@nxp.com>
>
> One ls1012a, there is one SATA 3.0 advanced host controller interface
> which is a high-performance SATA solution that delivers comprehensive
> and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
> capabilities, in accordance with the serial ATA revision 3.0 of Serial
> ATA International Organization.
> Add sata node to support this feature.
>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> ---
> v3:
>     - no changes
> v2:
>     - add qds and 2g5rdb board support
>
>  arch/arm/dts/fsl-ls1012a-2g5rdb.dts |    4 ++++
>  arch/arm/dts/fsl-ls1012a-qds.dtsi   |    4 ++++
>  arch/arm/dts/fsl-ls1012a-rdb.dtsi   |    4 ++++
>  arch/arm/dts/fsl-ls1012a.dtsi       |    8 ++++++++
>  4 files changed, 20 insertions(+), 0 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 1/4 v3] armv8: fsl: remove sata support

[York Sun]

On 07/13/2018 02:27 AM, andy.tang at nxp.com wrote:
> From: Yuantian Tang <andy.tang@nxp.com>
> 
> Remove the old implementation in order to enable DM for sata
> 
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> ---
> v3:
>     - rebase to latest code
> v2:
>     - no changes
> 

This set has been pplied to fsl-qoriq, awaiting upstream.
Thanks.

York