From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751329AbdEATAS (ORCPT ); Mon, 1 May 2017 15:00:18 -0400 Received: from mail-eopbgr10071.outbound.protection.outlook.com ([40.107.1.71]:51695 "EHLO EUR02-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750766AbdEATAR (ORCPT ); Mon, 1 May 2017 15:00:17 -0400 From: Roy Pledge To: Scott Wood , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "robin.murphy@arm.com" CC: Madalin-Cristian Bucur Subject: Re: [PATCH v2 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC Thread-Topic: [PATCH v2 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC Thread-Index: AQHSuU5jbcKJKchzHEG0XH9DV7bawg== Date: Mon, 1 May 2017 19:00:14 +0000 Message-ID: References: <1492634930-10765-1-git-send-email-roy.pledge@nxp.com> <1492634930-10765-8-git-send-email-roy.pledge@nxp.com> <1492998461.25397.16.camel@buserror.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: buserror.net; dkim=none (message not signed) header.d=none;buserror.net; dmarc=none action=none header.from=nxp.com; x-originating-ip: [192.88.168.1] x-microsoft-exchange-diagnostics: 1;AM5PR0402MB2689;7:cV7eWy8Xe43GDP1ScBhoSVOxdk4pd7Da2Rbv6iIP+pObXqpi5L2f/yoIoS6cpO1hfy7mBqPYZPy+3/ZkIvmMZoTPHHylHNYrZI91xvYJ85vT0zY4OrVkwI5RINiel1+oZu7vMpeGA7cp2ADV3XdZVOTZ0loJX2dIPInKDs3b9yoA9Hvk5uGrg4ywRbhv1upCEAX6ZheytQfipf0UgU4DLvLJReFk2Po5a8YhPDolwAiNhuq6fHkp0k0+gJpafE/B2OpJxYf4vLd/m3BczMSimJtljMxfNvq38QdjrFh6iuAyhZJowMiPGv3Z5xyWpv4BK0KV1qzDLzm3iLldYxMI3Q== x-forefront-antispam-report: SFV:SKI;SCL:-1SFV:NSPM;SFS:(10009020)(6009001)(39860400002)(39450400003)(39850400002)(39840400002)(39410400002)(39400400002)(24454002)(377424004)(377454003)(6436002)(2201001)(122556002)(8676002)(77096006)(55016002)(189998001)(6246003)(7696004)(6116002)(3660700001)(3846002)(8936002)(4326008)(86362001)(2906002)(53936002)(102836003)(38730400002)(6506006)(81166006)(33656002)(66066001)(74316002)(3280700002)(229853002)(25786009)(53546009)(76176999)(7736002)(305945005)(54356999)(2501003)(99286003)(9686003)(50986999)(478600001)(5660300001)(2900100001);DIR:OUT;SFP:1101;SCL:1;SRVR:AM5PR0402MB2689;H:VI1PR04MB3216.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; x-ms-office365-filtering-correlation-id: deadfde4-19bf-4a00-4188-08d490c44cb5 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081);SRVR:AM5PR0402MB2689; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(185117386973197)(275809806118684); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040450)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(93006095)(93001095)(6055026)(6041248)(20161123555025)(20161123560025)(20161123558100)(20161123562025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123564025)(6072148);SRVR:AM5PR0402MB2689;BCL:0;PCL:0;RULEID:;SRVR:AM5PR0402MB2689; x-forefront-prvs: 02945962BD spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 01 May 2017 19:00:14.0238 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0402MB2689 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v41J1Tj2032479 On 4/23/2017 9:47 PM, Scott Wood wrote: > On Wed, 2017-04-19 at 16:48 -0400, Roy Pledge wrote: >> Rework ioremap() for PPC and ARM. The PPC devices require a >> non-coherent mapping while ARM will work with a non-cachable/write >> combine mapping. >> >> Signed-off-by: Roy Pledge >> --- >> drivers/soc/fsl/qbman/bman_portal.c | 16 +++++++++++++--- >> drivers/soc/fsl/qbman/qman_portal.c | 16 +++++++++++++--- >> 2 files changed, 26 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/soc/fsl/qbman/bman_portal.c >> b/drivers/soc/fsl/qbman/bman_portal.c >> index 8354d4d..a661f30 100644 >> --- a/drivers/soc/fsl/qbman/bman_portal.c >> +++ b/drivers/soc/fsl/qbman/bman_portal.c >> @@ -125,7 +125,18 @@ static int bman_portal_probe(struct platform_device >> *pdev) >> } >> pcfg->irq = irq; >> >> - va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), >> 0); >> +#ifdef CONFIG_PPC >> + /* PPC requires a cacheable/non-coherent mapping of the portal */ >> + va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), >> + (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT)); >> +#else >> + /* >> + * For ARM we can use write combine mapping. A cacheable/non >> shareable >> + * mapping will perform better but equires additional platform >> + * support which is not currently available >> + */ > s/equires/requires/ > > Would be nice to describe the platform support that is required. Thanks for your feedback Scott, going to try to get a v3 of this set ASAP. I think I will remove the above statement for now. We did send patches for do non-shareable support on DPAA2 and there was significant feedback so I'm in the process of discussing the issue with SOC architects here. We will follow up with ARM folks on this eventually but I'd like to get the basic DPAA1 support in before adding the more advanced features. Roy > > -Scott > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on0043.outbound.protection.outlook.com [104.47.1.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wGtz92vLGzDq5W for ; Tue, 2 May 2017 05:00:20 +1000 (AEST) From: Roy Pledge To: Scott Wood , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "robin.murphy@arm.com" CC: Madalin-Cristian Bucur Subject: Re: [PATCH v2 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC Date: Mon, 1 May 2017 19:00:14 +0000 Message-ID: References: <1492634930-10765-1-git-send-email-roy.pledge@nxp.com> <1492634930-10765-8-git-send-email-roy.pledge@nxp.com> <1492998461.25397.16.camel@buserror.net> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 4/23/2017 9:47 PM, Scott Wood wrote:=0A= > On Wed, 2017-04-19 at 16:48 -0400, Roy Pledge wrote:=0A= >> Rework ioremap() for PPC and ARM. The PPC devices require a=0A= >> non-coherent mapping while ARM will work with a non-cachable/write=0A= >> combine mapping.=0A= >>=0A= >> Signed-off-by: Roy Pledge =0A= >> ---=0A= >> drivers/soc/fsl/qbman/bman_portal.c | 16 +++++++++++++---=0A= >> drivers/soc/fsl/qbman/qman_portal.c | 16 +++++++++++++---=0A= >> 2 files changed, 26 insertions(+), 6 deletions(-)=0A= >>=0A= >> diff --git a/drivers/soc/fsl/qbman/bman_portal.c=0A= >> b/drivers/soc/fsl/qbman/bman_portal.c=0A= >> index 8354d4d..a661f30 100644=0A= >> --- a/drivers/soc/fsl/qbman/bman_portal.c=0A= >> +++ b/drivers/soc/fsl/qbman/bman_portal.c=0A= >> @@ -125,7 +125,18 @@ static int bman_portal_probe(struct platform_device= =0A= >> *pdev)=0A= >> }=0A= >> pcfg->irq =3D irq;=0A= >> =0A= >> - va =3D ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),= =0A= >> 0);=0A= >> +#ifdef CONFIG_PPC=0A= >> + /* PPC requires a cacheable/non-coherent mapping of the portal */=0A= >> + va =3D ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),= =0A= >> + (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));=0A= >> +#else=0A= >> + /*=0A= >> + * For ARM we can use write combine mapping. A cacheable/non=0A= >> shareable=0A= >> + * mapping will perform better but equires additional platform=0A= >> + * support which is not currently available=0A= >> + */=0A= > s/equires/requires/=0A= >=0A= > Would be nice to describe the platform support that is required.=0A= Thanks for your feedback Scott, going to try to get a v3 of this set=0A= ASAP. I think I will remove the=0A= above statement for now. We did send patches for do non-shareable=0A= support on DPAA2 and there was significant feedback so I'm in the=0A= process of discussing the issue with SOC architects here. We will=0A= follow up with ARM folks on this eventually but I'd like to get the=0A= basic DPAA1 support in before adding the more advanced features.=0A= =0A= Roy=0A= >=0A= > -Scott=0A= >=0A= >=0A= =0A= From mboxrd@z Thu Jan 1 00:00:00 1970 From: roy.pledge@nxp.com (Roy Pledge) Date: Mon, 1 May 2017 19:00:14 +0000 Subject: [PATCH v2 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC References: <1492634930-10765-1-git-send-email-roy.pledge@nxp.com> <1492634930-10765-8-git-send-email-roy.pledge@nxp.com> <1492998461.25397.16.camel@buserror.net> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 4/23/2017 9:47 PM, Scott Wood wrote: > On Wed, 2017-04-19 at 16:48 -0400, Roy Pledge wrote: >> Rework ioremap() for PPC and ARM. The PPC devices require a >> non-coherent mapping while ARM will work with a non-cachable/write >> combine mapping. >> >> Signed-off-by: Roy Pledge >> --- >> drivers/soc/fsl/qbman/bman_portal.c | 16 +++++++++++++--- >> drivers/soc/fsl/qbman/qman_portal.c | 16 +++++++++++++--- >> 2 files changed, 26 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/soc/fsl/qbman/bman_portal.c >> b/drivers/soc/fsl/qbman/bman_portal.c >> index 8354d4d..a661f30 100644 >> --- a/drivers/soc/fsl/qbman/bman_portal.c >> +++ b/drivers/soc/fsl/qbman/bman_portal.c >> @@ -125,7 +125,18 @@ static int bman_portal_probe(struct platform_device >> *pdev) >> } >> pcfg->irq = irq; >> >> - va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), >> 0); >> +#ifdef CONFIG_PPC >> + /* PPC requires a cacheable/non-coherent mapping of the portal */ >> + va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), >> + (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT)); >> +#else >> + /* >> + * For ARM we can use write combine mapping. A cacheable/non >> shareable >> + * mapping will perform better but equires additional platform >> + * support which is not currently available >> + */ > s/equires/requires/ > > Would be nice to describe the platform support that is required. Thanks for your feedback Scott, going to try to get a v3 of this set ASAP. I think I will remove the above statement for now. We did send patches for do non-shareable support on DPAA2 and there was significant feedback so I'm in the process of discussing the issue with SOC architects here. We will follow up with ARM folks on this eventually but I'd like to get the basic DPAA1 support in before adding the more advanced features. Roy > > -Scott > >