[U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode

From: Xiaowei Bao <xiaowei.bao@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode
Date: Wed, 22 May 2019 10:19:18 +0000	[thread overview]
Message-ID: <VI1PR04MB3310C0B85CA46D78CE6D520FF5000@VI1PR04MB3310.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <CAEUhbmVW_36vbmG3j3bLRmE_tz8UVtHZMC8EUwsRJRz-ZXHnOA@mail.gmail.com>

Hi Bin,

-----Original Message-----
From: Bin Meng <bmeng.cn@gmail.com> 
Sent: 2019年5月17日 10:31
To: Xiaowei Bao <xiaowei.bao@nxp.com>; Ramon Fried <ramon.fried@gmail.com>; Simon Glass <sjg@chromium.org>
Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; u-boot at lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
Subject: Re: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode

Caution: EXT Email

Hi Xiaowei,

On Fri, May 17, 2019 at 10:23 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
>
>
> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: 2019年5月16日 19:58
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou 
> <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Hongbo Wang 
> <hongbo.wang@nxp.com>; York Sun <york.sun@nxp.com>; 
> u-boot at lists.denx.de; Jiafei Pan <jiafei.pan@nxp.com>
> Subject: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support 
> for ls2088 PCIe EP mode
>
> Caution: EXT Email
>
> Hi,
>
> On Thu, May 16, 2019 at 7:02 PM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> >
> > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> >
> > Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > ---
> > v2:
> >  - Add the NXP copyright and make the function readability.
> >
> >  drivers/pci/pcie_layerscape.c |  117 +++++++++++++++++++++++++++--------------
> >  drivers/pci/pcie_layerscape.h |   19 +++++--
> >  2 files changed, 91 insertions(+), 45 deletions(-)
> >
>
> Could you please support the PCIe EP mode using driver model?
> [Xiaowei Bao] do you mean that add a EP driver model to separate the RC and EP with their respective drivers?

That's correct.

> The purpose of adding EP support under u-boot is to configure the size of the BAR when the PCIE controller is used as an EP device, and to ensure that the configuration space of the EP can be accessed, so that when the RC scans the bus, the EP device can be scanned, and we also can do simple MEM read and write verification through the md command in u-boot shell.
> When entering the kernel, the kernel has its own PCIE EP framework, which will reinitialize the EP device, contain of the inbound and outbound window configure, MSI configuration and so no.
>

It's not kernel PCIe EP framework. Ramon Fried recently added PCIe EP uclass support to U-Boot and you should add NXP layerscape PCIe EP driver using the new EP uclass.
[Xiaowei Bao] OK, thanks, I will add NXP layerscape PCIe EP driver using the new EP uclass.

See https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D104952&amp;data=02%7C01%7Cxiaowei.bao%40nxp.com%7Ca1e3da7d57a54520bd3008d6da6fbc4d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C636936570769296107&amp;sdata=5CnEujEtYGbeiBEyv4iY5dXAapdQ65wCh1vs0quSVTY%3D&amp;reserved=0

Regards,
Bin