[U-Boot] [PATCH v2] fsl-lsch3: Add FlexSPI address space in immap_lsch3

[U-Boot] [PATCH v2] fsl-lsch3: Add FlexSPI address space in immap_lsch3

[Ashish Kumar]

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
v2:
 1. Rename SYS_FSL_FSPI_ADDR SYS_NXP_FSPI_ADDR
 2. Add mcaro for lutkey base addr and LUTa base addr

 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index b0cec74db0..a2aea18838 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,7 +19,13 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#ifndef CONFIG_NXP_LSCH3_2
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x010c0000)
+#else
+#define SYS_NXP_FSPI_ADDR			(CONFIG_SYS_IMMR + 0x010c0000)
+#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR		0x18
+#define SYS_NXP_FSPI_LUT_BASE_ADDR		0x200
+#endif
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
-- 
2.17.1

[U-Boot] [PATCH v2] fsl-lsch3: soc: Enable AHB read support for Flexspi controller

[Ashish Kumar]

Enable AHB support for Flexspi controller interface meaning
memory can be accessed via md command using absolute addresses

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
v2:
 1. Rename FSPI to FlexSPI in description and comments
 2. s/cmd/command
 3. Add macro and comments to improve readablity of code in soc.c
 4. Add declaration in soc.h for fspi_ahb_init()

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig     | 10 +++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c       | 44 +++++++++++++++++++
 .../arm/include/asm/arch-fsl-layerscape/soc.h |  7 +++
 3 files changed, 61 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5280d33ec8..70f26973e9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -327,6 +327,16 @@ config SYS_FSPI_AHB_INIT
 	  performed. Default LUT programmed in AHB mode is Fast Read command
 	  with 4-byte addressing enabled.
 
+config FSPI_AHB_EN_4BYTE
+	bool "Enable 4-byte Fast Read command for AHB mode"
+	depends on NXP_FSPI
+	default n
+	help
+	  The default setting for FlexSPI AHB bus just supports 3-byte addressing.
+	  But some FlexSPI flash sizes are up to 64MBytes.
+	  This flag enables fast read command for AHB mode and modifies required
+	  LUT to support full FlexSPI flash.
+
 config SYS_CCI400_OFFSET
 	hex "Offset for CCI400 base"
 	depends on SYS_FSL_HAS_CCI400
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3f15cb08ff..0a0e112a88 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -640,6 +640,47 @@ void fsl_lsch2_early_init_f(void)
 }
 #endif
 
+#ifdef CONFIG_FSPI_AHB_EN_4BYTE
+int fspi_ahb_init(void)
+{
+	/* Enable 4bytes address support and fast read */
+	u32 *fspi_lut, lut_key, *fspi_key;
+
+	fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
+	fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
+
+	lut_key = in_be32(fspi_key);
+
+	if (lut_key == SYS_NXP_FSPI_LUTKEY) {
+		/* That means the register is BE */
+		out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
+		/* Unlock the lut table */
+		out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
+		/* Create READ LUT */
+		out_be32(fspi_lut, 0x0820040c);
+		out_be32(fspi_lut + 1, 0x24003008);
+		out_be32(fspi_lut + 2, 0x00000000);
+		/* Lock the lut table */
+		out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
+		out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
+	} else {
+		/* That means the register is LE */
+		out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
+		/* Unlock the lut table */
+		out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
+		/* Create READ LUT */
+		out_le32(fspi_lut, 0x0820040c);
+		out_le32(fspi_lut + 1, 0x24003008);
+		out_le32(fspi_lut + 2, 0x00000000);
+		/* Lock the lut table */
+		out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
+		out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
+	}
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_QSPI_AHB_INIT
 /* Enable 4bytes address support and fast read */
 int qspi_ahb_init(void)
@@ -688,6 +729,9 @@ int board_late_init(void)
 #ifdef CONFIG_QSPI_AHB_INIT
 	qspi_ahb_init();
 #endif
+#ifdef CONFIG_FSPI_AHB_EN_4BYTE
+	fspi_ahb_init();
+#endif
 
 	return 0;
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 61b6e4bf07..84450c76ed 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -102,6 +102,13 @@ void init_pfe_scfg_dcfg_regs(void);
 int qspi_ahb_init(void);
 #endif
 
+#ifdef CONFIG_FSPI_AHB_EN_4BYTE
+#define SYS_NXP_FSPI_LUTCR_LOCK			0x00000001
+#define SYS_NXP_FSPI_LUTCR_UNLOCK		0x00000002
+#define SYS_NXP_FSPI_LUTKEY			0x5AF05AF0
+int fspi_ahb_init(void);
+#endif
+
 void cpu_name(char *name);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 void erratum_a009635(void);
-- 
2.17.1

[U-Boot] [PATCH v2] fsl-lsch3: soc: Enable AHB read support for Flexspi controller

[York Sun]

On 9/26/18 4:10 AM, Ashish Kumar wrote:
> Enable AHB support for Flexspi controller interface meaning
> memory can be accessed via md command using absolute addresses
> 
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
> ---
> v2:
>  1. Rename FSPI to FlexSPI in description and comments
>  2. s/cmd/command
>  3. Add macro and comments to improve readablity of code in soc.c
>  4. Add declaration in soc.h for fspi_ahb_init()
> 
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig     | 10 +++++
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c       | 44 +++++++++++++++++++
>  .../arm/include/asm/arch-fsl-layerscape/soc.h |  7 +++
>  3 files changed, 61 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 5280d33ec8..70f26973e9 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -327,6 +327,16 @@ config SYS_FSPI_AHB_INIT
>  	  performed. Default LUT programmed in AHB mode is Fast Read command
>  	  with 4-byte addressing enabled.

SYS_FSPI_AHB_INIT doesn't exist yet.

>  
> +config FSPI_AHB_EN_4BYTE
> +	bool "Enable 4-byte Fast Read command for AHB mode"
> +	depends on NXP_FSPI
> +	default n
> +	help
> +	  The default setting for FlexSPI AHB bus just supports 3-byte addressing.
> +	  But some FlexSPI flash sizes are up to 64MBytes.
> +	  This flag enables fast read command for AHB mode and modifies required
> +	  LUT to support full FlexSPI flash.
> +

NXP_FSPI doesn't exist yet.

Do you have dependency I missed?

York

[U-Boot] [PATCH v2] fsl-lsch3: soc: Enable AHB read support for Flexspi controller

[York Sun]

On 11/2/18 8:59 AM, York Sun wrote:
> On 9/26/18 4:10 AM, Ashish Kumar wrote:
>> Enable AHB support for Flexspi controller interface meaning
>> memory can be accessed via md command using absolute addresses
>>
>> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
>> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
>> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
>> ---
>> v2:
>>  1. Rename FSPI to FlexSPI in description and comments
>>  2. s/cmd/command
>>  3. Add macro and comments to improve readablity of code in soc.c
>>  4. Add declaration in soc.h for fspi_ahb_init()
>>
>>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig     | 10 +++++
>>  arch/arm/cpu/armv8/fsl-layerscape/soc.c       | 44 +++++++++++++++++++
>>  .../arm/include/asm/arch-fsl-layerscape/soc.h |  7 +++
>>  3 files changed, 61 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> index 5280d33ec8..70f26973e9 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> @@ -327,6 +327,16 @@ config SYS_FSPI_AHB_INIT
>>  	  performed. Default LUT programmed in AHB mode is Fast Read command
>>  	  with 4-byte addressing enabled.
> 
> SYS_FSPI_AHB_INIT doesn't exist yet.
> 
>>  
>> +config FSPI_AHB_EN_4BYTE
>> +	bool "Enable 4-byte Fast Read command for AHB mode"
>> +	depends on NXP_FSPI
>> +	default n
>> +	help
>> +	  The default setting for FlexSPI AHB bus just supports 3-byte addressing.
>> +	  But some FlexSPI flash sizes are up to 64MBytes.
>> +	  This flag enables fast read command for AHB mode and modifies required
>> +	  LUT to support full FlexSPI flash.
>> +
> 
> NXP_FSPI doesn't exist yet.
> 
> Do you have dependency I missed?
> 

Please fix your patch asap.

York

[U-Boot] [PATCH v2] fsl-lsch3: soc: Enable AHB read support for Flexspi controller

[Ashish Kumar]

> -----Original Message-----
> From: York Sun
> Sent: Tuesday, November 13, 2018 3:34 AM
> To: Ashish Kumar <ashish.kumar@nxp.com>
> Cc: u-boot at lists.denx.de; Rajat Srivastava <rajat.srivastava@nxp.com>; Yogesh
> Narayan Gaur <yogeshnarayan.gaur@nxp.com>
> Subject: Re: [PATCH v2] fsl-lsch3: soc: Enable AHB read support for Flexspi
> controller
> 
> On 11/2/18 8:59 AM, York Sun wrote:
> > On 9/26/18 4:10 AM, Ashish Kumar wrote:
> >> Enable AHB support for Flexspi controller interface meaning memory
> >> can be accessed via md command using absolute addresses
> >>
> >> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> >> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
> >> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
> >> ---
> >> v2:
> >>  1. Rename FSPI to FlexSPI in description and comments  2.
> >> s/cmd/command  3. Add macro and comments to improve readablity of
> >> code in soc.c  4. Add declaration in soc.h for fspi_ahb_init()
> >>
> >>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig     | 10 +++++
> >>  arch/arm/cpu/armv8/fsl-layerscape/soc.c       | 44 +++++++++++++++++++
> >>  .../arm/include/asm/arch-fsl-layerscape/soc.h |  7 +++
> >>  3 files changed, 61 insertions(+)
> >>
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> >> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> >> index 5280d33ec8..70f26973e9 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> >> @@ -327,6 +327,16 @@ config SYS_FSPI_AHB_INIT
> >>  	  performed. Default LUT programmed in AHB mode is Fast Read
> command
> >>  	  with 4-byte addressing enabled.
> >
> > SYS_FSPI_AHB_INIT doesn't exist yet.
> >
> >>
> >> +config FSPI_AHB_EN_4BYTE
> >> +	bool "Enable 4-byte Fast Read command for AHB mode"
> >> +	depends on NXP_FSPI
> >> +	default n
> >> +	help
> >> +	  The default setting for FlexSPI AHB bus just supports 3-byte
> addressing.
> >> +	  But some FlexSPI flash sizes are up to 64MBytes.
> >> +	  This flag enables fast read command for AHB mode and modifies
> required
> >> +	  LUT to support full FlexSPI flash.
> >> +
> >
> > NXP_FSPI doesn't exist yet.
> >
> > Do you have dependency I missed?
> >
> 
> Please fix your patch asap.
I have created v3[http://patchwork.ozlabs.org/patch/996846/] adding dependency patch information.

Regards
Ashish
> 
> York