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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: MiriHFKvWkG7tOXwJjaHfbvliqsSwcpVpjyucP4F2n0dGrUYKINUXzrsyJ/Ovnm+hVOjj592zb1U1OBiUXcPYjYyKbihpbPuIv8PnxsZ+ynJ4VX4Vc2UPNkxCaTkBM04umZwtXQqiym3j5FbMrEO97IsbwEPCEv5/ewo3I0VwrguDTWN+ZP/QjSK/IMhMgaqsu0wrXqxkPisS7xESbELWeuVU5qZ5IHaW+oIl7iEoBQxrHw1L2rELiVBWOu9PyjwDvclVVL06EntKKNzFvgmYFM2f94j074PI6QcUzwQIZyfxqftrvWYB8YWkxINddRhgtWZbQfLkZ+0yGk76AB2RLavr1GC8iZ5cMMFi4G+xl9VTe5JV6iUmQ/b2srl20G416oTzFJu4HbLYvGcyb/8ps+XZgEQMwuTjMcT5Jb3aws= Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 79d59e76-800c-4e34-c306-08d75248b540 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Oct 2019 14:54:12.5758 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cPufE3yRPtCnMTDsyci4jhsK6CBBBiEXmjDvdwyboysPbgb1WEdRrjJrdNtPMy6PY64HN88/hZSTE4hWniKIhg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4109 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On 16.10.2019 17:09, Angus Ainslie wrote:=0A= > On 2019-10-15 07:05, Leonard Crestez wrote:=0A= >> On 10.10.2019 17:43, Angus Ainslie wrote:=0A= >>>=0A= >>> I've integrated your u-boot and ATF on our board and I have a couple=0A= >>> of questions. Our board is running imx8mq B0 (Rev 2.0) silicon.=0A= >>>=0A= >>> It looks like this line limits the training frequencies to 800 MHz and= =0A= >>> 166 MHz=0A= >>=0A= >> Yes! This is due to a hardware errata which was solved in B1: DRAM pll= =0A= >> can't be disabled. This means that instead of 25/100/800 freqs are=0A= >> 166/800, and this requires code changes.=0A= >>=0A= >>> Does 100 MHz and 25 MHz not work on B0 ?=0A= >>=0A= >> No, lower rates require dram clk from a composite slice (dram_alt_root)= =0A= >>=0A= >>> I added the ddrc_and noc opp as well as the 166MHz opp=0A= >>>=0A= >>> I also added the interconnects ( do we need them on imx8mq ? )=0A= >>=0A= >> The interconnect stuff is not required to switch dram frequency, it's=0A= >> for device to make minimum bandwidth requests. It an additional feature= =0A= >> on top.=0A= >>=0A= >> As a hack I configured FEC to do so but a saner example would be to=0A= >> request bandwidth based on display resolution and color depth.=0A= >>=0A= >>> I had to add a hack as the PM QoS was limiting the bus speed to 399MHz,= =0A= >>> if you have any ideas why that would be appreciated.=0A= >>=0A= >> You probably need to set ethernet down (which is awkward) or better=0A= >> just drop the interconnect properties and test using the devfreq userspa= ce=0A= >> governor.=0A= >>=0A= >>> The driver is probing=0A= >>>=0A= >>> [ 12.136537] bus: 'platform': driver_probe_device: matched device=0A= >>> 3d400000.dram-controller with driver imx-ddrc-devfrq=0A= >>> [ 12.147259] bus: 'platform': really_probe: probing driver=0A= >>> imx-ddrc-devfreq with device 3d400000.dram-controller=0A= >>> [ 12.157382] imx-ddrc-devfreq 3d400000.dram-controller: no pinctrl=0A= >>> handle=0A= >>> [ 12.164197] arm_smcc rate 0 800000000=0A= >>> [ 12.167880] arm_smcc rate 1 166750000=0A= >>> [ 12.171778] of: _opp_add_static_v2: turbo:0 rate:25000000 uv:0=0A= >>> uvmin:0 uvmax:0 latency:0=0A= >>> [ 12.179994] of: _opp_add_static_v2: turbo:0 rate:100000000 uv:0=0A= >>> uvmin:0 uvmax:0 latency:0=0A= >>> [ 12.188311] of: _opp_add_static_v2: turbo:0 rate:166750000 uv:0=0A= >>> uvmin:0 uvmax:0 latency:0=0A= >>> [ 12.196606] of: _opp_add_static_v2: turbo:0 rate:800000000 uv:0=0A= >>> uvmin:0 uvmax:0 latency:0=0A= >>> [ 12.204930] imx-ddrc-devfreq 3d400000.dram-controller: events from= =0A= >>> pmu imx8_ddr0=0A= >>> [ 12.212403] Added freq 0 25000000=0A= >>> [ 12.215742] Added freq 1 100000000=0A= >>> [ 12.219177] Added freq 2 166750000=0A= >>> [ 12.222648] Added freq 3 800000000=0A= >>> [ 12.226105] device: 'devfreq0': device_add=0A= >>> [ 12.230287] PM: Adding info for No Bus:devfreq0=0A= >>> [ 12.234864] driver: 'imx-ddrc-devfreq': driver_bound: bound to=0A= >>> device=0A= >>> '3d400000.dram-controller'=0A= >>> [ 12.243699] bus: 'platform': really_probe: bound device=0A= >>> 3d400000.dram-controller to driver imx-ddrc-devfreq=0A= >>>=0A= >>> Add seems to run correctly until it tries to adjust the clock to=0A= >>> 166MHz=0A= >>>=0A= >>> [ 19.555482] ddrc checking rate 800000000 166750000=0A= >>> [ 19.555489] ddrc checking rate 166750000 166750000=0A= >>> [ 19.560442] bus: 'usb-serial': really_probe: bound device ttyUSB0=0A= >>> to=0A= >>> driver option1=0A= >>> [ 19.568751] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about=0A= >>> to=0A= >>> change freq 800000000 to 166750000=0A= >>>=0A= >>> And the board hangs there. Any ideas on how to get past this ?=0A= >>=0A= >> Please try this ATF patch:=0A= > =0A= > Ok applied this to the tree we're using=0A= > =0A= >> I tested switching on imx8mq-evk with B0 SoC but a few additional=0A= >> changes are required in kernel to support switching between rates which= =0A= >> are both backed by PLL:=0A= >>=0A= >> * Mark the PLL CLK_GET_RATE_NOCACHE=0A= > =0A= > Is this what you meant ?=0A= > =0A= > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c= =0A= > index 2813884f69c1..e5f50cf8a264 100644=0A= > --- a/drivers/clk/imx/clk-imx8mq.c=0A= > +++ b/drivers/clk/imx/clk-imx8mq.c=0A= > @@ -345,7 +345,7 @@ static int imx8mq_clocks_probe(struct=0A= > platform_device *pdev)=0A= > clks[IMX8MQ_SYS1_PLL_OUT] =3D imx_clk_sccg_pll("sys1_pll_out",= =0A= > sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30,= =0A= > CLK_IS_CRITICAL);=0A= > clks[IMX8MQ_SYS2_PLL_OUT] =3D imx_clk_sccg_pll("sys2_pll_out",= =0A= > sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c,= =0A= > CLK_IS_CRITICAL);=0A= > clks[IMX8MQ_SYS3_PLL_OUT] =3D imx_clk_sccg_pll("sys3_pll_out",= =0A= > sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48,= =0A= > CLK_IS_CRITICAL);=0A= > - clks[IMX8MQ_DRAM_PLL_OUT] =3D imx_clk_sccg_pll("dram_pll_out",=0A= > dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60,= =0A= > CLK_IS_CRITICAL);=0A= > + clks[IMX8MQ_DRAM_PLL_OUT] =3D imx_clk_sccg_pll("dram_pll_out",=0A= > dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60,= =0A= > CLK_IS_CRITICAL|CLK_GET_RATE_NOCACHE);=0A= =0A= Yes.=0A= =0A= >> * Set the rate to 166935483 exactly (to match clk_get_rate)=0A= > =0A= > Okay I hacked that in=0A= > =0A= > diff --git a/drivers/devfreq/imx-ddrc.c b/drivers/devfreq/imx-ddrc.c=0A= > index 4eed6f50bb8d..a832768a865f 100644=0A= > --- a/drivers/devfreq/imx-ddrc.c=0A= > +++ b/drivers/devfreq/imx-ddrc.c=0A= > @@ -436,6 +436,10 @@ static int imx_ddrc_init_freq_info(struct device=0A= > *dev)=0A= > return -ENODEV;=0A= > }=0A= > =0A= > + /* B0 hack */=0A= > + if ( freq->rate =3D=3D 166750000 )=0A= > + freq->rate =3D 166935483;=0A= > +inserting =0A= > pr_err( "arm_smcc rate %d %lu\n", index, freq->rate );= =0A= > }=0A= =0A= A nicer solution would be to keep imx_ddrc_freq.rate in MT/s as reported = =0A= by firmware and divide by 25000 in imx_ddrc_find_freq instead.=0A= =0A= > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi=0A= > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi=0A= > @@ -211,7 +211,7 @@=0A= > opp-hz =3D /bits/ 64 <100000000>;=0A= > };=0A= > opp-166M {=0A= > - opp-hz =3D /bits/ 64 <166750000>;=0A= > + opp-hz =3D /bits/ 64 <166935483>;=0A= > };=0A= > opp-800M {=0A= > opp-hz =3D /bits/ 64 <800000000>;=0A= =0A= Yes, this is the precise clock rate in Hz.=0A= =0A= >> * Make the rounding in imx-ddrc more generous.=0A= > =0A= > Sorry I don't understand what you mean by this=0A= =0A= I meant to make imx_ddrc_find_freq find 667 MT/s for an OPP of 166935483:= =0A= =0A= /*=0A= * Firmware reports values in MT/s, so we round-down from Hz=0A= * Rounding is extra generous to ensure a match.=0A= */=0A= rate =3D DIV_ROUND_CLOSEST(rate, 250000);=0A= for (i =3D 0; i < priv->freq_count; ++i) {=0A= struct imx_ddrc_freq *freq =3D &priv->freq_table[i];=0A= if (freq->rate =3D=3D rate ||=0A= freq->rate + 1 =3D=3D rate ||=0A= freq->rate - 1 =3D=3D rate)=0A= return freq;=0A= }=0A= =0A= But your B0 hack above should also work.=0A= =0A= > Adding the other changes the board no longer hangs when trying to change= =0A= > frequencies but it also doesn't seem to actually change the frequency.=0A= > =0A= > [ 3.076426] ddrc checking rate 800000000 166935483=0A= > [ 3.081290] ddrc checking rate 166935483 166935483=0A= > [ 3.086225] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about to= =0A= > change freq 800000000 to 166935483=0A= > [ 3.086891] imx-ddrc-devfreq 3d400000.dram-controller: ddrc changed=0A= > freq 800000000 to 166935483=0A= > =0A= > root@pureos:~# cat /sys/class/devfreq/devfreq0/cur_freq=0A= > 800000000=0A= > root@pureos:~# cat /sys/class/devfreq/devfreq0/target_freq=0A= > 166935483=0A= =0A= The target_freq value is from clk_get_rate(dram_core) but it is =0A= dram_core's parent which gets updated. It seems that a clk mux ignores =0A= CLK_GET_RATE_NOCACHE on the parent.=0A= =0A= An update can be forced by adding `clk_get_rate(new_dram_core_parent);` =0A= at the end of imx_ddrc_set_freq.=0A= =0A= You should also be able to check by looking at clk_summary or=0A= /sys/kernel/debug/clk/dram_core_clk/clk_rate=0A= /sys/kernel/debug/clk/dram_pll_out/clk_rate=0A= =0A= --=0A= Regards,=0A= Leonard=0A= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60D55FA3728 for ; Wed, 16 Oct 2019 14:54:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 28EE32168B for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 16.10.2019 17:09, Angus Ainslie wrote: > On 2019-10-15 07:05, Leonard Crestez wrote: >> On 10.10.2019 17:43, Angus Ainslie wrote: >>> >>> I've integrated your u-boot and ATF on our board and I have a couple >>> of questions. Our board is running imx8mq B0 (Rev 2.0) silicon. >>> >>> It looks like this line limits the training frequencies to 800 MHz and >>> 166 MHz >> >> Yes! This is due to a hardware errata which was solved in B1: DRAM pll >> can't be disabled. This means that instead of 25/100/800 freqs are >> 166/800, and this requires code changes. >> >>> Does 100 MHz and 25 MHz not work on B0 ? >> >> No, lower rates require dram clk from a composite slice (dram_alt_root) >> >>> I added the ddrc_and noc opp as well as the 166MHz opp >>> >>> I also added the interconnects ( do we need them on imx8mq ? ) >> >> The interconnect stuff is not required to switch dram frequency, it's >> for device to make minimum bandwidth requests. It an additional feature >> on top. >> >> As a hack I configured FEC to do so but a saner example would be to >> request bandwidth based on display resolution and color depth. >> >>> I had to add a hack as the PM QoS was limiting the bus speed to 399MHz, >>> if you have any ideas why that would be appreciated. >> >> You probably need to set ethernet down (which is awkward) or better >> just drop the interconnect properties and test using the devfreq userspace >> governor. >> >>> The driver is probing >>> >>> [ 12.136537] bus: 'platform': driver_probe_device: matched device >>> 3d400000.dram-controller with driver imx-ddrc-devfrq >>> [ 12.147259] bus: 'platform': really_probe: probing driver >>> imx-ddrc-devfreq with device 3d400000.dram-controller >>> [ 12.157382] imx-ddrc-devfreq 3d400000.dram-controller: no pinctrl >>> handle >>> [ 12.164197] arm_smcc rate 0 800000000 >>> [ 12.167880] arm_smcc rate 1 166750000 >>> [ 12.171778] of: _opp_add_static_v2: turbo:0 rate:25000000 uv:0 >>> uvmin:0 uvmax:0 latency:0 >>> [ 12.179994] of: _opp_add_static_v2: turbo:0 rate:100000000 uv:0 >>> uvmin:0 uvmax:0 latency:0 >>> [ 12.188311] of: _opp_add_static_v2: turbo:0 rate:166750000 uv:0 >>> uvmin:0 uvmax:0 latency:0 >>> [ 12.196606] of: _opp_add_static_v2: turbo:0 rate:800000000 uv:0 >>> uvmin:0 uvmax:0 latency:0 >>> [ 12.204930] imx-ddrc-devfreq 3d400000.dram-controller: events from >>> pmu imx8_ddr0 >>> [ 12.212403] Added freq 0 25000000 >>> [ 12.215742] Added freq 1 100000000 >>> [ 12.219177] Added freq 2 166750000 >>> [ 12.222648] Added freq 3 800000000 >>> [ 12.226105] device: 'devfreq0': device_add >>> [ 12.230287] PM: Adding info for No Bus:devfreq0 >>> [ 12.234864] driver: 'imx-ddrc-devfreq': driver_bound: bound to >>> device >>> '3d400000.dram-controller' >>> [ 12.243699] bus: 'platform': really_probe: bound device >>> 3d400000.dram-controller to driver imx-ddrc-devfreq >>> >>> Add seems to run correctly until it tries to adjust the clock to >>> 166MHz >>> >>> [ 19.555482] ddrc checking rate 800000000 166750000 >>> [ 19.555489] ddrc checking rate 166750000 166750000 >>> [ 19.560442] bus: 'usb-serial': really_probe: bound device ttyUSB0 >>> to >>> driver option1 >>> [ 19.568751] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about >>> to >>> change freq 800000000 to 166750000 >>> >>> And the board hangs there. Any ideas on how to get past this ? >> >> Please try this ATF patch: > > Ok applied this to the tree we're using > >> I tested switching on imx8mq-evk with B0 SoC but a few additional >> changes are required in kernel to support switching between rates which >> are both backed by PLL: >> >> * Mark the PLL CLK_GET_RATE_NOCACHE > > Is this what you meant ? > > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > index 2813884f69c1..e5f50cf8a264 100644 > --- a/drivers/clk/imx/clk-imx8mq.c > +++ b/drivers/clk/imx/clk-imx8mq.c > @@ -345,7 +345,7 @@ static int imx8mq_clocks_probe(struct > platform_device *pdev) > clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", > sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, > CLK_IS_CRITICAL); > clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", > sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, > CLK_IS_CRITICAL); > clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", > sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, > CLK_IS_CRITICAL); > - clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", > dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, > CLK_IS_CRITICAL); > + clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", > dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, > CLK_IS_CRITICAL|CLK_GET_RATE_NOCACHE); Yes. >> * Set the rate to 166935483 exactly (to match clk_get_rate) > > Okay I hacked that in > > diff --git a/drivers/devfreq/imx-ddrc.c b/drivers/devfreq/imx-ddrc.c > index 4eed6f50bb8d..a832768a865f 100644 > --- a/drivers/devfreq/imx-ddrc.c > +++ b/drivers/devfreq/imx-ddrc.c > @@ -436,6 +436,10 @@ static int imx_ddrc_init_freq_info(struct device > *dev) > return -ENODEV; > } > > + /* B0 hack */ > + if ( freq->rate == 166750000 ) > + freq->rate = 166935483; > +inserting > pr_err( "arm_smcc rate %d %lu\n", index, freq->rate ); > } A nicer solution would be to keep imx_ddrc_freq.rate in MT/s as reported by firmware and divide by 25000 in imx_ddrc_find_freq instead. > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -211,7 +211,7 @@ > opp-hz = /bits/ 64 <100000000>; > }; > opp-166M { > - opp-hz = /bits/ 64 <166750000>; > + opp-hz = /bits/ 64 <166935483>; > }; > opp-800M { > opp-hz = /bits/ 64 <800000000>; Yes, this is the precise clock rate in Hz. >> * Make the rounding in imx-ddrc more generous. > > Sorry I don't understand what you mean by this I meant to make imx_ddrc_find_freq find 667 MT/s for an OPP of 166935483: /* * Firmware reports values in MT/s, so we round-down from Hz * Rounding is extra generous to ensure a match. */ rate = DIV_ROUND_CLOSEST(rate, 250000); for (i = 0; i < priv->freq_count; ++i) { struct imx_ddrc_freq *freq = &priv->freq_table[i]; if (freq->rate == rate || freq->rate + 1 == rate || freq->rate - 1 == rate) return freq; } But your B0 hack above should also work. > Adding the other changes the board no longer hangs when trying to change > frequencies but it also doesn't seem to actually change the frequency. > > [ 3.076426] ddrc checking rate 800000000 166935483 > [ 3.081290] ddrc checking rate 166935483 166935483 > [ 3.086225] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about to > change freq 800000000 to 166935483 > [ 3.086891] imx-ddrc-devfreq 3d400000.dram-controller: ddrc changed > freq 800000000 to 166935483 > > root@pureos:~# cat /sys/class/devfreq/devfreq0/cur_freq > 800000000 > root@pureos:~# cat /sys/class/devfreq/devfreq0/target_freq > 166935483 The target_freq value is from clk_get_rate(dram_core) but it is dram_core's parent which gets updated. It seems that a clk mux ignores CLK_GET_RATE_NOCACHE on the parent. An update can be forced by adding `clk_get_rate(new_dram_core_parent);` at the end of imx_ddrc_set_freq. You should also be able to check by looking at clk_summary or /sys/kernel/debug/clk/dram_core_clk/clk_rate /sys/kernel/debug/clk/dram_pll_out/clk_rate -- Regards, Leonard _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel