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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?c2hzQKwt2iM6CABTAVkGQJ0QAglNYcEdRcM3LiDx33oGzk4xbuWLqheDeMeS?= =?us-ascii?Q?zw0ssMhI7wCxzwztWoE26Vw45za0qBe0Fr5w+tzbndhN+UCpEaW3eMQ5CtZG?= =?us-ascii?Q?arjTcEjiiPra2wFVKMn/XrQ28dupWFlDeP+7gMNGByrChCoynK0z0Nzm8KBx?= =?us-ascii?Q?u6OJZhK+yQkg1yCMRpEAuMJYADVEQ12o+BRs0vZi8kb2QCsKvR41WotrINwq?= =?us-ascii?Q?k7rnW+Z2OKR3k9JUeZXwrhojYKj2u8YWZ2ahgXm4+VQ1Z9VwKMB8ckJrIV7o?= =?us-ascii?Q?L4wBMSB4/Voqx2PUP3ktkxCmQFpKwrHeioRE8yNkFB3fNLfTcwFR31iAyGYp?= =?us-ascii?Q?aqEymt8tG/JKTGtIB2EQzWbvkZOTQ7jeob+1hfTGkvTPDAJRIcfvJGifjWcp?= =?us-ascii?Q?KtVjBsNl/LWQC1S8mxnZzkm/RR5t/V50rYhXJBs8ALMBJYjX0BCfU2EQzTVt?= =?us-ascii?Q?pxoTyur6MRcBBhzktrASqal7emJi2ri9J8oS4GX3iFk+r0mdOJs/i6plpW2b?= =?us-ascii?Q?6TkSjLcF7rkDRxsUxSauHKr3cXe8bvKkyu3JW7pgD5D7N4+PRy6o/PgTB1u+?= =?us-ascii?Q?DM6izrbt/p0Bu+le7CA1pivE60Gurw376AR+qhEMX7ONvMJRfMx2aYna8CHd?= =?us-ascii?Q?6G/ZbRDVW9hd6F4sONc293SAj7wGVboL18rmYymdkf4oBv9AFrRzNmgc7R3D?= =?us-ascii?Q?dQYFogX0+3HzB1YGsiFfEv9FFOzn0EqfGBx1fPeJoOkxIR4reTXrtufY0p9z?= =?us-ascii?Q?antO7GD9ImOX/KLznsbKs3FjDhyI6nmQLxYmN7iMheEl17eZwMl6kpIwCZdm?= =?us-ascii?Q?ybUMiVKDUBvIKoNVIe8z4lhgug0PNY40jmZ+WC52blEB3iOQ5JodyqCIJECm?= =?us-ascii?Q?Njyw6gGqVahrEYMGgLQN5KDtzh6nNjZcrAHErr0xUk8z4jkX8m5xd/8Eynv1?= =?us-ascii?Q?bsunSkLS9vxeUTj2ht0TGUv5Q/Shch/RZgCOM5DSTAnvDSVKkaAoRk0IsH+D?= =?us-ascii?Q?JrmIgxOeCPH4ZLShm9rUiPkk987E7p3UcLnIbNMAQ5RFjQ9t8I+NxMztU/q2?= =?us-ascii?Q?sK9zPmHeI8onU3F5wFgns4UMJQIb4vkSZk4yrWhVPdEzdk3B4d0uIalq9ois?= =?us-ascii?Q?lI93nsqdHbJFJAbxw7EQQNuBVOEC+Tqp2ULbevsNYbdTIbmrEKrz/i1As0/k?= =?us-ascii?Q?14MiTUMtrbLvhUQDWkfNgDgzPbVSwmoUssAOyQnL3VHhgU+7BSS21vow3ECO?= =?us-ascii?Q?psdA7SN6G+cvND42va24y3OioTQkGOrheCNq9jf2+g+BPB7PIEwyq/BIo1IR?= =?us-ascii?Q?8t8H953Zefumeoyg0wj84vnI+3k1HEcmLuKIM5siRkhCMd3dCZROFeKsD9EI?= =?us-ascii?Q?Lqv/zF6JnOBV+e+gKLC4McE6qQ+m68iIjLFjA7oj61kHimshjDsAtKfB5Wi9?= =?us-ascii?Q?mxwycNNNJJ9B5gYWcdr6kq4ao0DHIfTZuU9U7oEP8Z5GpMr2T6yn9XdzbuUo?= =?us-ascii?Q?+Yen7OhfSXqXxdHOBICMmRzk/2caMnPLgDyBcyhh0SKA0qYdfZJX/9BSNndE?= =?us-ascii?Q?1fFHd20ThdodbqrafGdsNehX0t3pa5neYxNGMd+x3fng2JXcJwSlAThpKFdn?= =?us-ascii?Q?DA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: fef3d896-4219-4009-822e-08db0ecd9545 X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 20:53:54.2855 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XJVhb63PxzxHGoYiYD+qCrvctFxSOBE8Bv8Z4RxC6j5gwyx6uQBKqTddiA6tlhF88zFuHHq7n4iz4T4x3kR6rw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB8207 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/hwmon: Enable PL1 limit when writing limit value to HW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Feb 14, 2023 at 12:47:23PM -0800, Dixit, Ashutosh wrote: > On Tue, 14 Feb 2023 06:51:37 -0800, Rodrigo Vivi wrote: > > > > Hi Rodrigo, > > > On Mon, Feb 13, 2023 at 01:00:48PM -0800, Ashutosh Dixit wrote: > > > Previous documentation suggested that the PL1 power limit is always enabled > > > in HW. However we now find this not to be the case on some platforms (such > > > as ATSM). Therefore enable the PL1 power limit (by setting the enable bit) > > > when writing the PL1 limit value to HW. > > > > > > Bspec: 51864 > > > > > > Signed-off-by: Ashutosh Dixit > > > --- > > > drivers/gpu/drm/i915/i915_hwmon.c | 5 +++-- > > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c > > > index 85195d61f89c7..7c20a6f47b92e 100644 > > > --- a/drivers/gpu/drm/i915/i915_hwmon.c > > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c > > > @@ -385,10 +385,11 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val) > > > > > > /* Computation in 64-bits to avoid overflow. Round to nearest. */ > > > nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER); > > > + nval = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, nval); > > > > > > hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit, > > > - PKG_PWR_LIM_1, > > > - REG_FIELD_PREP(PKG_PWR_LIM_1, nval)); > > > + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, > > > + nval); > > > > This patch looks right to me. But could you please open up on what exactly > > failed on that reverted patch? Why do we need to set the bits together? > > I had explained a bit here: > > https://gitlab.freedesktop.org/drm/intel/-/issues/8062#note_1761070 > > But will repeat. On ATSM, at power-up, PCODE sets the PL1 power limit to 0 > but disables the PL1 power limit. The earlier patch had enabled the the PL1 > power limit during module load itself but had left the PL1 power limit set > to 0 (since there is no easy way to find out what it should be set to, on > ATSM PCODE sets even the max power (which could have been used to set the > PL1 limit) to 0). You can see that patch here: > > https://patchwork.freedesktop.org/patch/521321/?series=113578&rev=4 > > Now the PL1 power limit being 0 (and enabled) implies that HW will work > with minimum power and therefore the lowest effective frequency. This means > all workloads will run slower and this was resulting in various IGT tests > timing out and GuC FW load (on resets) timing out on ATSM and that is why > we had to revert that patch. > > In this patch I have changed the strategy and instead of enabling the PL1 > power limit on module load we now enable it only when the limit is set by > userspace. So at least the default CI will not be affected in this case. We > can see that there no regressions on ATSM this time here: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113984v1/bat-all.html? > this makes total sense. Thank you! Reviewed-by: Rodrigo Vivi > Thanks. > -- > Ashutosh > > > > > > > > return 0; > > > } > > > > > > -- > > > 2.38.0 > > >