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From: Borislav Petkov <bp@alien8.de>
To: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Pavel Machek <pavel@ucw.cz>,
	Andrew Cooper <Andrew.Cooper3@citrix.com>,
	degoede@redhat.com, linux-kernel@vger.kernel.org,
	linux-pm@vger.kernel.org,
	Daniel Sneddon <daniel.sneddon@linux.intel.com>,
	antonio.gomez.iglesias@linux.intel.com
Subject: Re: [PATCH 2/3] x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG enumeration
Date: Tue, 8 Nov 2022 19:54:01 +0100	[thread overview]
Message-ID: <Y2qlyfRKgIc4KVcx@zn.tnic> (raw)
In-Reply-To: <034c7f5ac243ee7b40ba1a8cc3f9b10b1e380674.1663025154.git.pawan.kumar.gupta@linux.intel.com>

On Mon, Sep 12, 2022 at 04:40:47PM -0700, Pawan Gupta wrote:
> Currently there is no easy way to enumerate MSR_AMD64_LS_CFG. As this
> MSR is supported on AMD CPU families 10h to 18h, set a new feature bit
> on these CPU families. The new bit can be used to detect the MSR
> support.
> 
> Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  arch/x86/kernel/cpu/amd.c          | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index dd173733e40d..90bdb1d98531 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -305,6 +305,7 @@
>  #define X86_FEATURE_USE_IBPB_FW		(11*32+16) /* "" Use IBPB during runtime firmware calls */
>  #define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
>  #define X86_FEATURE_MSR_TSX_CTRL	(11*32+18) /* "" MSR IA32_TSX_CTRL */
> +#define X86_FEATURE_MSR_LS_CFG		(11*32+19) /* "" MSR AMD64_LS_CFG */

We already have that one:

#define X86_FEATURE_LS_CFG_SSBD         ( 7*32+24)  /* "" AMD SSBD implementation via LS_CFG MSR */

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

  reply	other threads:[~2022-11-08 18:54 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-12 23:38 [PATCH 0/3] Check enumeration before MSR save/restore Pawan Gupta
2022-09-12 23:39 ` [PATCH 1/3] x86/tsx: Add feature bit for TSX control MSR support Pawan Gupta
2022-11-08 18:27   ` Dave Hansen
2022-11-08 22:06     ` Pawan Gupta
2022-09-12 23:40 ` [PATCH 2/3] x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG enumeration Pawan Gupta
2022-11-08 18:54   ` Borislav Petkov [this message]
2022-11-08 22:51     ` Pawan Gupta
2022-11-08 23:10       ` Borislav Petkov
2022-11-09  0:45         ` Andrew Cooper
2022-11-09 17:37           ` Pawan Gupta
2022-11-09 18:34             ` Borislav Petkov
2022-11-09 21:41               ` Pawan Gupta
2022-11-10  0:00             ` Andrew Cooper
2022-11-10  6:09               ` Pawan Gupta
2022-11-09  2:18         ` Pawan Gupta
2022-09-12 23:41 ` [PATCH 3/3] x86/pm: Add enumeration check before spec MSRs save/restore setup Pawan Gupta
2022-11-08 18:40   ` Dave Hansen
2022-11-08 22:09     ` Pawan Gupta
2022-09-13  0:50 ` [PATCH 0/3] Check enumeration before MSR save/restore Pawan Gupta
2022-09-17 11:42   ` Hans de Goede
2022-09-19 16:56     ` Pawan Gupta
2022-11-08 18:16 ` Hans de Goede
2022-11-08 18:26   ` Borislav Petkov
2022-11-08 18:55     ` Borislav Petkov
2022-11-08 22:07       ` Pawan Gupta

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