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From: Oliver Upton To: Ben Gardon Cc: Marc Zyngier , James Morse , Alexandru Elisei , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Reiji Watanabe , Ricardo Koller , David Matlack , Quentin Perret , Gavin Shan , Peter Xu , Will Deacon , Sean Christopherson , kvmarm@lists.linux.dev Subject: Re: [PATCH v5 11/14] KVM: arm64: Make block->table PTE changes parallel-aware Message-ID: References: <20221107215644.1895162-1-oliver.upton@linux.dev> <20221107215855.1895367-1-oliver.upton@linux.dev> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, Nov 09, 2022 at 02:26:36PM -0800, Ben Gardon wrote: > On Mon, Nov 7, 2022 at 1:59 PM Oliver Upton wrote: > > > > In order to service stage-2 faults in parallel, stage-2 table walkers > > must take exclusive ownership of the PTE being worked on. An additional > > requirement of the architecture is that software must perform a > > 'break-before-make' operation when changing the block size used for > > mapping memory. > > > > Roll these two concepts together into helpers for performing a > > 'break-before-make' sequence. Use a special PTE value to indicate a PTE > > has been locked by a software walker. Additionally, use an atomic > > compare-exchange to 'break' the PTE when the stage-2 page tables are > > possibly shared with another software walker. Elide the DSB + TLBI if > > the evicted PTE was invalid (and thus not subject to break-before-make). > > > > All of the atomics do nothing for now, as the stage-2 walker isn't fully > > ready to perform parallel walks. > > > > Signed-off-by: Oliver Upton > > --- > > arch/arm64/kvm/hyp/pgtable.c | 80 +++++++++++++++++++++++++++++++++--- > > 1 file changed, 75 insertions(+), 5 deletions(-) > > > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > > index f4dd77c6c97d..b9f0d792b8d9 100644 > > --- a/arch/arm64/kvm/hyp/pgtable.c > > +++ b/arch/arm64/kvm/hyp/pgtable.c > > @@ -49,6 +49,12 @@ > > #define KVM_INVALID_PTE_OWNER_MASK GENMASK(9, 2) > > #define KVM_MAX_OWNER_ID 1 > > > > +/* > > + * Used to indicate a pte for which a 'break-before-make' sequence is in > > + * progress. > > + */ > > +#define KVM_INVALID_PTE_LOCKED BIT(10) > > + > > struct kvm_pgtable_walk_data { > > struct kvm_pgtable_walker *walker; > > > > @@ -674,6 +680,11 @@ static bool stage2_pte_is_counted(kvm_pte_t pte) > > return !!pte; > > } > > > > +static bool stage2_pte_is_locked(kvm_pte_t pte) > > +{ > > + return !kvm_pte_valid(pte) && (pte & KVM_INVALID_PTE_LOCKED); > > +} > > + > > static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t new) > > { > > if (!kvm_pgtable_walk_shared(ctx)) { > > @@ -684,6 +695,64 @@ static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_ > > return cmpxchg(ctx->ptep, ctx->old, new) == ctx->old; > > } > > > > +/** > > + * stage2_try_break_pte() - Invalidates a pte according to the > > + * 'break-before-make' requirements of the > > + * architecture. > > + * > > + * @ctx: context of the visited pte. > > + * @mmu: stage-2 mmu > > + * > > + * Returns: true if the pte was successfully broken. > > + * > > + * If the removed pte was valid, performs the necessary serialization and TLB > > + * invalidation for the old value. For counted ptes, drops the reference count > > + * on the containing table page. > > + */ > > +static bool stage2_try_break_pte(const struct kvm_pgtable_visit_ctx *ctx, > > + struct kvm_s2_mmu *mmu) > > +{ > > + struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops; > > + > > + if (stage2_pte_is_locked(ctx->old)) { > > + /* > > + * Should never occur if this walker has exclusive access to the > > + * page tables. > > + */ > > + WARN_ON(!kvm_pgtable_walk_shared(ctx)); > > + return false; > > + } > > + > > + if (!stage2_try_set_pte(ctx, KVM_INVALID_PTE_LOCKED)) > > + return false; > > + > > + /* > > + * Perform the appropriate TLB invalidation based on the evicted pte > > + * value (if any). > > + */ > > + if (kvm_pte_table(ctx->old, ctx->level)) > > + kvm_call_hyp(__kvm_tlb_flush_vmid, mmu); > > + else if (kvm_pte_valid(ctx->old)) > > + kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu, ctx->addr, ctx->level); > > + > > + if (stage2_pte_is_counted(ctx->old)) > > + mm_ops->put_page(ctx->ptep); > > + > > + return true; > > +} > > + > > +static void stage2_make_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t new) > > +{ > > + struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops; > > + > > + WARN_ON(!stage2_pte_is_locked(*ctx->ptep)); > > + > > + if (stage2_pte_is_counted(new)) > > + mm_ops->get_page(ctx->ptep); > > + > > + smp_store_release(ctx->ptep, new); > > +} > > + > > static void stage2_put_pte(const struct kvm_pgtable_visit_ctx *ctx, struct kvm_s2_mmu *mmu, > > struct kvm_pgtable_mm_ops *mm_ops) > > { > > @@ -812,17 +881,18 @@ static int stage2_map_walk_leaf(const struct kvm_pgtable_visit_ctx *ctx, > > if (!childp) > > return -ENOMEM; > > > > + if (!stage2_try_break_pte(ctx, data->mmu)) { > > + mm_ops->put_page(childp); > > + return -EAGAIN; > > + } > > + > > /* > > * If we've run into an existing block mapping then replace it with > > * a table. Accesses beyond 'end' that fall within the new table > > * will be mapped lazily. > > */ > > - if (stage2_pte_is_counted(ctx->old)) > > - stage2_put_pte(ctx, data->mmu, mm_ops); > > - > > new = kvm_init_table_pte(childp, mm_ops); > > Does it make any sense to move this before the "break" to minimize the > critical section in which the PTE is locked? I had rationalized this before as doing less work in the threads that would lose a race, but the critical section is very likely to be performance sensitive as we're unmapping memory after all. Thanks for the suggestion, I'll fold it in the next spin. -- Best, Oliver From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09C55C43217 for ; Wed, 9 Nov 2022 23:03:46 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6C3124B9AD; Wed, 9 Nov 2022 18:03:46 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@linux.dev Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yznnz+RWg7gC; Wed, 9 Nov 2022 18:03:45 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 0250E4BA01; Wed, 9 Nov 2022 18:03:45 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id C0E5A4B9F4 for ; Wed, 9 Nov 2022 18:03:43 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PcruKwgn596x for ; Wed, 9 Nov 2022 18:03:42 -0500 (EST) Received: from out0.migadu.com (out0.migadu.com [94.23.1.103]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id E35834B9AD for ; Wed, 9 Nov 2022 18:03:41 -0500 (EST) Date: Wed, 9 Nov 2022 23:03:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1668035016; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=cEYES5XxXZs+zunY6rrb9ofRyEyk1RW2nSk1EruIy3s=; b=jlZXDD9x+BAG+Jr7d0COcWMBnWDXvrMyjGdpxHyfb6MvSH6Dc6Ass51yOagLrPqR2unXvO 6h75qxzYity7jNp27ZKfrpuiFVnRJKQu6S52E0IoT9g39sKlLrzyNag13dftducsU3F8O6 hmlrdSayU6PLRAj1yDBw2tPv/+00okA= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Ben Gardon Subject: Re: [PATCH v5 11/14] KVM: arm64: Make block->table PTE changes parallel-aware Message-ID: References: <20221107215644.1895162-1-oliver.upton@linux.dev> <20221107215855.1895367-1-oliver.upton@linux.dev> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT Cc: kvm@vger.kernel.org, Marc Zyngier , Will Deacon , kvmarm@lists.linux.dev, David Matlack , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Wed, Nov 09, 2022 at 02:26:36PM -0800, Ben Gardon wrote: > On Mon, Nov 7, 2022 at 1:59 PM Oliver Upton wrote: > > > > In order to service stage-2 faults in parallel, stage-2 table walkers > > must take exclusive ownership of the PTE being worked on. An additional > > requirement of the architecture is that software must perform a > > 'break-before-make' operation when changing the block size used for > > mapping memory. > > > > Roll these two concepts together into helpers for performing a > > 'break-before-make' sequence. Use a special PTE value to indicate a PTE > > has been locked by a software walker. Additionally, use an atomic > > compare-exchange to 'break' the PTE when the stage-2 page tables are > > possibly shared with another software walker. Elide the DSB + TLBI if > > the evicted PTE was invalid (and thus not subject to break-before-make). > > > > All of the atomics do nothing for now, as the stage-2 walker isn't fully > > ready to perform parallel walks. > > > > Signed-off-by: Oliver Upton > > --- > > arch/arm64/kvm/hyp/pgtable.c | 80 +++++++++++++++++++++++++++++++++--- > > 1 file changed, 75 insertions(+), 5 deletions(-) > > > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > > index f4dd77c6c97d..b9f0d792b8d9 100644 > > --- a/arch/arm64/kvm/hyp/pgtable.c > > +++ b/arch/arm64/kvm/hyp/pgtable.c > > @@ -49,6 +49,12 @@ > > #define KVM_INVALID_PTE_OWNER_MASK GENMASK(9, 2) > > #define KVM_MAX_OWNER_ID 1 > > > > +/* > > + * Used to indicate a pte for which a 'break-before-make' sequence is in > > + * progress. > > + */ > > +#define KVM_INVALID_PTE_LOCKED BIT(10) > > + > > struct kvm_pgtable_walk_data { > > struct kvm_pgtable_walker *walker; > > > > @@ -674,6 +680,11 @@ static bool stage2_pte_is_counted(kvm_pte_t pte) > > return !!pte; > > } > > > > +static bool stage2_pte_is_locked(kvm_pte_t pte) > > +{ > > + return !kvm_pte_valid(pte) && (pte & KVM_INVALID_PTE_LOCKED); > > +} > > + > > static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t new) > > { > > if (!kvm_pgtable_walk_shared(ctx)) { > > @@ -684,6 +695,64 @@ static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_ > > return cmpxchg(ctx->ptep, ctx->old, new) == ctx->old; > > } > > > > +/** > > + * stage2_try_break_pte() - Invalidates a pte according to the > > + * 'break-before-make' requirements of the > > + * architecture. > > + * > > + * @ctx: context of the visited pte. > > + * @mmu: stage-2 mmu > > + * > > + * Returns: true if the pte was successfully broken. > > + * > > + * If the removed pte was valid, performs the necessary serialization and TLB > > + * invalidation for the old value. For counted ptes, drops the reference count > > + * on the containing table page. > > + */ > > +static bool stage2_try_break_pte(const struct kvm_pgtable_visit_ctx *ctx, > > + struct kvm_s2_mmu *mmu) > > +{ > > + struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops; > > + > > + if (stage2_pte_is_locked(ctx->old)) { > > + /* > > + * Should never occur if this walker has exclusive access to the > > + * page tables. > > + */ > > + WARN_ON(!kvm_pgtable_walk_shared(ctx)); > > + return false; > > + } > > + > > + if (!stage2_try_set_pte(ctx, KVM_INVALID_PTE_LOCKED)) > > + return false; > > + > > + /* > > + * Perform the appropriate TLB invalidation based on the evicted pte > > + * value (if any). > > + */ > > + if (kvm_pte_table(ctx->old, ctx->level)) > > + kvm_call_hyp(__kvm_tlb_flush_vmid, mmu); > > + else if (kvm_pte_valid(ctx->old)) > > + kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu, ctx->addr, ctx->level); > > + > > + if (stage2_pte_is_counted(ctx->old)) > > + mm_ops->put_page(ctx->ptep); > > + > > + return true; > > +} > > + > > +static void stage2_make_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t new) > > +{ > > + struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops; > > + > > + WARN_ON(!stage2_pte_is_locked(*ctx->ptep)); > > + > > + if (stage2_pte_is_counted(new)) > > + mm_ops->get_page(ctx->ptep); > > + > > + smp_store_release(ctx->ptep, new); > > +} > > + > > static void stage2_put_pte(const struct kvm_pgtable_visit_ctx *ctx, struct kvm_s2_mmu *mmu, > > struct kvm_pgtable_mm_ops *mm_ops) > > { > > @@ -812,17 +881,18 @@ static int stage2_map_walk_leaf(const struct kvm_pgtable_visit_ctx *ctx, > > if (!childp) > > return -ENOMEM; > > > > + if (!stage2_try_break_pte(ctx, data->mmu)) { > > + mm_ops->put_page(childp); > > + return -EAGAIN; > > + } > > + > > /* > > * If we've run into an existing block mapping then replace it with > > * a table. Accesses beyond 'end' that fall within the new table > > * will be mapped lazily. > > */ > > - if (stage2_pte_is_counted(ctx->old)) > > - stage2_put_pte(ctx, data->mmu, mm_ops); > > - > > new = kvm_init_table_pte(childp, mm_ops); > > Does it make any sense to move this before the "break" to minimize the > critical section in which the PTE is locked? I had rationalized this before as doing less work in the threads that would lose a race, but the critical section is very likely to be performance sensitive as we're unmapping memory after all. Thanks for the suggestion, I'll fold it in the next spin. -- Best, Oliver _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 085A8C433FE for ; Wed, 9 Nov 2022 23:04:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pTACW+7PhFsKATk3ODMd+6WJL8jwqmSzl0zVxt/I1Fk=; b=krm8HPVS+40AxG SwNydOzVGSo1yTToBor1BqHjjJwip0aZBK5sDc8FnhEaq36JfUqzFn7M0/um9Wu3j+06YRu4ZAvhX ZyH30EQ00Kmx+/yhKR1IYmKcrnDDLsSY5MIO4kALts3irrgrCqk0JNe2FIG4Yozinq/jYpnpakQ3J O38gMMp6xSRdUviR2rv+M3GYRF2k1MacWAuixHmkWyQxBWvewep6xmq+YWlsafguiCKEpHmQwOKDY asg+0cqBvYx6KzPQSc1V9l5b61fKtg/B+PLIxHkZAielwCjWCMd1fNyVB6g7Jf91MpW4ahjKlDjpc HmiZGHSv6fDGV9R374PA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1osu6l-000W80-Lg; Wed, 09 Nov 2022 23:03:48 +0000 Received: from out0.migadu.com ([94.23.1.103]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1osu6g-000W5L-Ib for linux-arm-kernel@lists.infradead.org; Wed, 09 Nov 2022 23:03:44 +0000 Date: Wed, 9 Nov 2022 23:03:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1668035016; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=cEYES5XxXZs+zunY6rrb9ofRyEyk1RW2nSk1EruIy3s=; b=jlZXDD9x+BAG+Jr7d0COcWMBnWDXvrMyjGdpxHyfb6MvSH6Dc6Ass51yOagLrPqR2unXvO 6h75qxzYity7jNp27ZKfrpuiFVnRJKQu6S52E0IoT9g39sKlLrzyNag13dftducsU3F8O6 hmlrdSayU6PLRAj1yDBw2tPv/+00okA= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Ben Gardon Cc: Marc Zyngier , James Morse , Alexandru Elisei , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Reiji Watanabe , Ricardo Koller , David Matlack , Quentin Perret , Gavin Shan , Peter Xu , Will Deacon , Sean Christopherson , kvmarm@lists.linux.dev Subject: Re: [PATCH v5 11/14] KVM: arm64: Make block->table PTE changes parallel-aware Message-ID: References: <20221107215644.1895162-1-oliver.upton@linux.dev> <20221107215855.1895367-1-oliver.upton@linux.dev> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221109_150343_169590_86B113FE X-CRM114-Status: GOOD ( 35.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Nov 09, 2022 at 02:26:36PM -0800, Ben Gardon wrote: > On Mon, Nov 7, 2022 at 1:59 PM Oliver Upton wrote: > > > > In order to service stage-2 faults in parallel, stage-2 table walkers > > must take exclusive ownership of the PTE being worked on. An additional > > requirement of the architecture is that software must perform a > > 'break-before-make' operation when changing the block size used for > > mapping memory. > > > > Roll these two concepts together into helpers for performing a > > 'break-before-make' sequence. Use a special PTE value to indicate a PTE > > has been locked by a software walker. Additionally, use an atomic > > compare-exchange to 'break' the PTE when the stage-2 page tables are > > possibly shared with another software walker. Elide the DSB + TLBI if > > the evicted PTE was invalid (and thus not subject to break-before-make). > > > > All of the atomics do nothing for now, as the stage-2 walker isn't fully > > ready to perform parallel walks. > > > > Signed-off-by: Oliver Upton > > --- > > arch/arm64/kvm/hyp/pgtable.c | 80 +++++++++++++++++++++++++++++++++--- > > 1 file changed, 75 insertions(+), 5 deletions(-) > > > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > > index f4dd77c6c97d..b9f0d792b8d9 100644 > > --- a/arch/arm64/kvm/hyp/pgtable.c > > +++ b/arch/arm64/kvm/hyp/pgtable.c > > @@ -49,6 +49,12 @@ > > #define KVM_INVALID_PTE_OWNER_MASK GENMASK(9, 2) > > #define KVM_MAX_OWNER_ID 1 > > > > +/* > > + * Used to indicate a pte for which a 'break-before-make' sequence is in > > + * progress. > > + */ > > +#define KVM_INVALID_PTE_LOCKED BIT(10) > > + > > struct kvm_pgtable_walk_data { > > struct kvm_pgtable_walker *walker; > > > > @@ -674,6 +680,11 @@ static bool stage2_pte_is_counted(kvm_pte_t pte) > > return !!pte; > > } > > > > +static bool stage2_pte_is_locked(kvm_pte_t pte) > > +{ > > + return !kvm_pte_valid(pte) && (pte & KVM_INVALID_PTE_LOCKED); > > +} > > + > > static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t new) > > { > > if (!kvm_pgtable_walk_shared(ctx)) { > > @@ -684,6 +695,64 @@ static bool stage2_try_set_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_ > > return cmpxchg(ctx->ptep, ctx->old, new) == ctx->old; > > } > > > > +/** > > + * stage2_try_break_pte() - Invalidates a pte according to the > > + * 'break-before-make' requirements of the > > + * architecture. > > + * > > + * @ctx: context of the visited pte. > > + * @mmu: stage-2 mmu > > + * > > + * Returns: true if the pte was successfully broken. > > + * > > + * If the removed pte was valid, performs the necessary serialization and TLB > > + * invalidation for the old value. For counted ptes, drops the reference count > > + * on the containing table page. > > + */ > > +static bool stage2_try_break_pte(const struct kvm_pgtable_visit_ctx *ctx, > > + struct kvm_s2_mmu *mmu) > > +{ > > + struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops; > > + > > + if (stage2_pte_is_locked(ctx->old)) { > > + /* > > + * Should never occur if this walker has exclusive access to the > > + * page tables. > > + */ > > + WARN_ON(!kvm_pgtable_walk_shared(ctx)); > > + return false; > > + } > > + > > + if (!stage2_try_set_pte(ctx, KVM_INVALID_PTE_LOCKED)) > > + return false; > > + > > + /* > > + * Perform the appropriate TLB invalidation based on the evicted pte > > + * value (if any). > > + */ > > + if (kvm_pte_table(ctx->old, ctx->level)) > > + kvm_call_hyp(__kvm_tlb_flush_vmid, mmu); > > + else if (kvm_pte_valid(ctx->old)) > > + kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu, ctx->addr, ctx->level); > > + > > + if (stage2_pte_is_counted(ctx->old)) > > + mm_ops->put_page(ctx->ptep); > > + > > + return true; > > +} > > + > > +static void stage2_make_pte(const struct kvm_pgtable_visit_ctx *ctx, kvm_pte_t new) > > +{ > > + struct kvm_pgtable_mm_ops *mm_ops = ctx->mm_ops; > > + > > + WARN_ON(!stage2_pte_is_locked(*ctx->ptep)); > > + > > + if (stage2_pte_is_counted(new)) > > + mm_ops->get_page(ctx->ptep); > > + > > + smp_store_release(ctx->ptep, new); > > +} > > + > > static void stage2_put_pte(const struct kvm_pgtable_visit_ctx *ctx, struct kvm_s2_mmu *mmu, > > struct kvm_pgtable_mm_ops *mm_ops) > > { > > @@ -812,17 +881,18 @@ static int stage2_map_walk_leaf(const struct kvm_pgtable_visit_ctx *ctx, > > if (!childp) > > return -ENOMEM; > > > > + if (!stage2_try_break_pte(ctx, data->mmu)) { > > + mm_ops->put_page(childp); > > + return -EAGAIN; > > + } > > + > > /* > > * If we've run into an existing block mapping then replace it with > > * a table. Accesses beyond 'end' that fall within the new table > > * will be mapped lazily. > > */ > > - if (stage2_pte_is_counted(ctx->old)) > > - stage2_put_pte(ctx, data->mmu, mm_ops); > > - > > new = kvm_init_table_pte(childp, mm_ops); > > Does it make any sense to move this before the "break" to minimize the > critical section in which the PTE is locked? I had rationalized this before as doing less work in the threads that would lose a race, but the critical section is very likely to be performance sensitive as we're unmapping memory after all. Thanks for the suggestion, I'll fold it in the next spin. -- Best, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel