On Wed, Nov 23, 2022 at 02:36:09PM +0100, Fabrice Gasnier wrote: > The ARR (auto reload register) and CMP (compare) registers are > successively written. The status bits to check the update of these > registers are polled together with regmap_read_poll_timeout(). > The condition to end the loop may become true, even if one of the register > isn't correctly updated. > So ensure both status bits are set before clearing them. > > Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer") > Signed-off-by: Fabrice Gasnier > --- > drivers/counter/stm32-lptimer-cnt.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c > index d6b80b6dfc28..8439755559b2 100644 > --- a/drivers/counter/stm32-lptimer-cnt.c > +++ b/drivers/counter/stm32-lptimer-cnt.c > @@ -69,7 +69,7 @@ static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv, > > /* ensure CMP & ARR registers are properly written */ > ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, > - (val & STM32_LPTIM_CMPOK_ARROK), > + (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK, This is a reasonable fix, but I don't like seeing so much happening in an argument list -- it's easy to misunderstand what's going on which can lead to further bugs the future. Pull out this condition to a dedicated bool variable with a comment explaining why we need the equivalence check (i.e. to ensure both status bits are set and not just one). William Breathitt Gray