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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id h9-20020a05620a284900b006f9ddaaf01esm12455343qkp.102.2022.11.23.07.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 07:08:16 -0800 (PST) Date: Tue, 22 Nov 2022 02:41:14 -0500 From: William Breathitt Gray To: Fabrice Gasnier Cc: jic23@kernel.org, alexandre.torgue@foss.st.com, olivier.moysan@foss.st.com, linux-iio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update Message-ID: References: <20221123133609.465614-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="MBQTBXmEy5ZnhVes" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --MBQTBXmEy5ZnhVes Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 23, 2022 at 03:56:31PM +0100, Fabrice Gasnier wrote: > On 11/22/22 08:33, William Breathitt Gray wrote: > > On Tue, Nov 22, 2022 at 02:27:50AM -0500, William Breathitt Gray wrote: > >> On Wed, Nov 23, 2022 at 02:36:09PM +0100, Fabrice Gasnier wrote: > >>> The ARR (auto reload register) and CMP (compare) registers are > >>> successively written. The status bits to check the update of these > >>> registers are polled together with regmap_read_poll_timeout(). > >>> The condition to end the loop may become true, even if one of the reg= ister > >>> isn't correctly updated. > >>> So ensure both status bits are set before clearing them. > >>> > >>> Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer") > >>> Signed-off-by: Fabrice Gasnier > >>> --- > >>> drivers/counter/stm32-lptimer-cnt.c | 2 +- > >>> 1 file changed, 1 insertion(+), 1 deletion(-) > >>> > >>> diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/st= m32-lptimer-cnt.c > >>> index d6b80b6dfc28..8439755559b2 100644 > >>> --- a/drivers/counter/stm32-lptimer-cnt.c > >>> +++ b/drivers/counter/stm32-lptimer-cnt.c > >>> @@ -69,7 +69,7 @@ static int stm32_lptim_set_enable_state(struct stm3= 2_lptim_cnt *priv, > >>> =20 > >>> /* ensure CMP & ARR registers are properly written */ > >>> ret =3D regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, > >>> - (val & STM32_LPTIM_CMPOK_ARROK), > >>> + (val & STM32_LPTIM_CMPOK_ARROK) =3D=3D STM32_LPTIM_CMPOK_= ARROK, > >> > >> This is a reasonable fix, but I don't like seeing so much happening in > >> an argument list -- it's easy to misunderstand what's going on which c= an > >> lead to further bugs the future. Pull out this condition to a dedicated > >> bool variable with a comment explaining why we need the equivalence > >> check (i.e. to ensure both status bits are set and not just one). > >> > >> William Breathitt Gray > >=20 > > Alternatively, you could pull out just (val & STM32_LPTIM_CMPOK_ARROK) > > to a separate variable and keep the equivalence condition inline if you > > think it'll be clearer that way. >=20 > Hi William, >=20 > I'm not sure to fully understand your proposal here. > Could you clarify ? >=20 > regmap_read_poll_timeout() macro requires: >=20 > * @val: Unsigned integer variable to read the value into > * @cond: Break condition (usually involving @val) >=20 > So do you wish I introduce a macro that abstracts the condition check ? > (val & STM32_LPTIM_CMPOK_ARROK) =3D=3D STM32_LPTIM_CMPOK_ARROK >=20 >=20 > Best regards, > Fabrice My apologies Fabrice, I realize now that regmap_read_poll_timeout() is a macro. Abstracting out the conditional would probably be more confusing than having it inline, so the way it is right now is probably fine after all. William Breathitt Gray --MBQTBXmEy5ZnhVes Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEARYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCY3x9GgAKCRC1SFbKvhIj Kz+lAQDMbIxU7BPDmxYGeA4ARRXDfefK7ZVmk8dutqzuUI9PMwD8CRczxb5A9kTp ZqBOIIef6M/iAzY6hZV01bnuvoOxhAo= =Crky -----END PGP SIGNATURE----- --MBQTBXmEy5ZnhVes-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3ECCCC4332F for ; Wed, 23 Nov 2022 15:10:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: In-Reply-To:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date: Reply-To:Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date :Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ViznvZVUKe0ULquqOYdJvlbU7qwxp3vCTV6Ppqj8sa8=; b=SWzX/AZCt8shAquKLpXFZGOfzQ l4FrJapgM/wpXUp+xJUaCdFN0oxMeQKmXWCg/qag+YTR+w03hD19Yl0TSjWTP6K/3bRUD3C+HhinG OyMTVSRkDqb1dLglN+OT4Hi73Q/EkF2wnC5rQY32ku1506LhJlRHNUyY42i1SnoYv1tpzlzIiG5LK 7pWF9I0M6HvP8VROyiL/DfWkwjph6mQK6HyQWQ/2beXFLEmbujTJeFmSIFMC54CgS16M3YM7p2qgi B0BWD+R64Cq9L/FNVtzkZr16YcxSHFry7IxkjSMv1LBdYHZP0de0WltN/pEy1037JBwEN0Ztp4bAO lTBvKpjA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oxrMN-000IXM-Gy; Wed, 23 Nov 2022 15:08:23 +0000 Received: from mail-qt1-x829.google.com ([2607:f8b0:4864:20::829]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oxrMK-000IUS-5R for linux-arm-kernel@lists.infradead.org; Wed, 23 Nov 2022 15:08:21 +0000 Received: by mail-qt1-x829.google.com with SMTP id cg5so11351899qtb.12 for ; Wed, 23 Nov 2022 07:08:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=+S7mFwOjPwIOTHt6SuUNUfln0CNGkBMEDjngY+UgUuw=; b=rzZ+y6MWMosxPSSLwzCaISThrED4G5+KW6v323GlLLMD+syvy4SFu0r6eNrMbH57sd uMZXQ1S2+vrMF8Wq25KawQXHdvH68RxHeGEk484kuMYOA+QApc5NgjNr/e6EWPs6nyDX kCengAM3vFGiyuzEP+bZWGM6bkmBOTL1D07J/t94+2HuS/Ic/dVLYnOyLsMp06vGPwc/ VXk87fMZ9jDpHO3oDrGCPbIeetmZTquIiluoxMRHf+GKyz/nRElElgM7Z0rdir/tly0U kPv29RU8QOzUFa72Uxd3+3//mcjj2fG77rzINTQWO8nhD7vHUr4IOvppHgMLOdwsntSC HfHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=+S7mFwOjPwIOTHt6SuUNUfln0CNGkBMEDjngY+UgUuw=; b=dBgrZhDhJyyODP+OAP8tjk8SASJwkmMzG8xCCE9MUQ6l5fUD+xs73cRDz9EJMO4/aA WJLHGWct+FfK8w+EI0w6BZjoFw4cw/gY/f8S77NSJDKbaRs00ood53rTXJNDV3HbqZeF 2OfGGJCjfIsjPDoSBhzU/9JX/QNQGQ2Al5RaR85H2laGEu1PW3Lr0K6zfRxI7sTCqRhA Bal4Xq5QtTEcf0J0jTFZyoYbJbl9inds8KktgoKaG+6aa+1LfQm7SAH+DVmx+m+YmJf2 i8AVQTnhUQRLpuYa0ZbuJHeOTAHmtv5EELw+F4Kdy/vB4i3XS4jvNOSAZWGzGRefUiNS Xe/g== X-Gm-Message-State: ANoB5plS8e2sQ81mOk5dmUw+bm7EYgsZDiFdgNXjtR+tNx6akb6iavab r/oJFCJt3lVWc/jh/RpGVrzXVw== X-Google-Smtp-Source: AA0mqf6lbGcYJ1up0v8P7VKqnSrzjDshqpztg9z1N3SWYybjjY8vuJvLTB0jH62UATdfYKb42oe7/w== X-Received: by 2002:a05:622a:4a11:b0:3a5:1cc6:ae12 with SMTP id fv17-20020a05622a4a1100b003a51cc6ae12mr26699265qtb.103.1669216096994; Wed, 23 Nov 2022 07:08:16 -0800 (PST) Received: from fedora (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id h9-20020a05620a284900b006f9ddaaf01esm12455343qkp.102.2022.11.23.07.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 07:08:16 -0800 (PST) Date: Tue, 22 Nov 2022 02:41:14 -0500 From: William Breathitt Gray To: Fabrice Gasnier Cc: jic23@kernel.org, alexandre.torgue@foss.st.com, olivier.moysan@foss.st.com, linux-iio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update Message-ID: References: <20221123133609.465614-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221123_070820_227838_E24BEF9F X-CRM114-Status: GOOD ( 29.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============0701599024156985859==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============0701599024156985859== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="MBQTBXmEy5ZnhVes" Content-Disposition: inline --MBQTBXmEy5ZnhVes Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 23, 2022 at 03:56:31PM +0100, Fabrice Gasnier wrote: > On 11/22/22 08:33, William Breathitt Gray wrote: > > On Tue, Nov 22, 2022 at 02:27:50AM -0500, William Breathitt Gray wrote: > >> On Wed, Nov 23, 2022 at 02:36:09PM +0100, Fabrice Gasnier wrote: > >>> The ARR (auto reload register) and CMP (compare) registers are > >>> successively written. The status bits to check the update of these > >>> registers are polled together with regmap_read_poll_timeout(). > >>> The condition to end the loop may become true, even if one of the reg= ister > >>> isn't correctly updated. > >>> So ensure both status bits are set before clearing them. > >>> > >>> Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer") > >>> Signed-off-by: Fabrice Gasnier > >>> --- > >>> drivers/counter/stm32-lptimer-cnt.c | 2 +- > >>> 1 file changed, 1 insertion(+), 1 deletion(-) > >>> > >>> diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/st= m32-lptimer-cnt.c > >>> index d6b80b6dfc28..8439755559b2 100644 > >>> --- a/drivers/counter/stm32-lptimer-cnt.c > >>> +++ b/drivers/counter/stm32-lptimer-cnt.c > >>> @@ -69,7 +69,7 @@ static int stm32_lptim_set_enable_state(struct stm3= 2_lptim_cnt *priv, > >>> =20 > >>> /* ensure CMP & ARR registers are properly written */ > >>> ret =3D regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, > >>> - (val & STM32_LPTIM_CMPOK_ARROK), > >>> + (val & STM32_LPTIM_CMPOK_ARROK) =3D=3D STM32_LPTIM_CMPOK_= ARROK, > >> > >> This is a reasonable fix, but I don't like seeing so much happening in > >> an argument list -- it's easy to misunderstand what's going on which c= an > >> lead to further bugs the future. Pull out this condition to a dedicated > >> bool variable with a comment explaining why we need the equivalence > >> check (i.e. to ensure both status bits are set and not just one). > >> > >> William Breathitt Gray > >=20 > > Alternatively, you could pull out just (val & STM32_LPTIM_CMPOK_ARROK) > > to a separate variable and keep the equivalence condition inline if you > > think it'll be clearer that way. >=20 > Hi William, >=20 > I'm not sure to fully understand your proposal here. > Could you clarify ? >=20 > regmap_read_poll_timeout() macro requires: >=20 > * @val: Unsigned integer variable to read the value into > * @cond: Break condition (usually involving @val) >=20 > So do you wish I introduce a macro that abstracts the condition check ? > (val & STM32_LPTIM_CMPOK_ARROK) =3D=3D STM32_LPTIM_CMPOK_ARROK >=20 >=20 > Best regards, > Fabrice My apologies Fabrice, I realize now that regmap_read_poll_timeout() is a macro. Abstracting out the conditional would probably be more confusing than having it inline, so the way it is right now is probably fine after all. William Breathitt Gray --MBQTBXmEy5ZnhVes Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEARYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCY3x9GgAKCRC1SFbKvhIj Kz+lAQDMbIxU7BPDmxYGeA4ARRXDfefK7ZVmk8dutqzuUI9PMwD8CRczxb5A9kTp ZqBOIIef6M/iAzY6hZV01bnuvoOxhAo= =Crky -----END PGP SIGNATURE----- --MBQTBXmEy5ZnhVes-- --===============0701599024156985859== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============0701599024156985859==--