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From: Jisheng Zhang <jszhang@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: "Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Jiri Slaby" <jirislaby@kernel.org>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org
Subject: Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC
Date: Mon, 28 Nov 2022 22:34:38 +0800	[thread overview]
Message-ID: <Y4TG/iM0ibf65Iua@xhacker> (raw)
In-Reply-To: <Y4TF8FzX19puws37@xhacker>

On Mon, Nov 28, 2022 at 10:30:15PM +0800, Jisheng Zhang wrote:
> On Sun, Nov 27, 2022 at 05:36:53PM +0000, Conor Dooley wrote:
> > On Sun, Nov 27, 2022 at 05:35:48PM +0000, Conor Dooley wrote:
> > > Hey Jisheng,
> > > 
> > > On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote:
> > > > Add Jisheng Zhang as Bouffalolab SoC maintainer.
> > > > 
> > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > ---
> > > >  MAINTAINERS | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > > 
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index 00ff4a2949b8..a6b04249853c 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -17729,6 +17729,15 @@ F:	arch/riscv/
> > > >  N:	riscv
> > > >  K:	riscv
> > > >  
> > > > +RISC-V BOUFFALOLAB SOC SUPPORT
> > > > +M:	Jisheng Zhang <jszhang@kernel.org>
> > > > +L:	linux-riscv@lists.infradead.org
> > > > +S:	Maintained
> > > > +F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> > > > +F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> > > > +F:	arch/riscv/boot/dts/bouffalolab/
> > > > +F:	drivers/tty/serial/bflb_uart.c
> > > 
> > > I think I asked last time but I didn't see an answer on lore or my
> > > mailbox - if you intend sending Arnd PRs for this stuff, please add a
> 
> Per my past experience of synaptics/mrvl arm SoCs, I usually sent PRs to Arnd
> if there are two or more commits/patches; If there's only one patch, I
> asked Arnd for picking it up directly. So in bouffalolab SoC case, I
> want to do similar, but with one difference -- if there's only one
> patch, may I ask you for picking it up directly?

That's to say: If there are two or more commits/patches, I will send
Arnd PRs; If there's only one commit/patch, I will ask your help to
picking it up directly.

> 
> > > git tree here. Otherwise, LMK and I'll bundle it with the other "misc
> 
> Hmm, is "git tree" necessary?
> 
> > > riscv devicetree" stuff.
> > 
> > I forgot:
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > 
> > > >  RISC-V MICROCHIP FPGA SUPPORT
> > > >  M:	Conor Dooley <conor.dooley@microchip.com>
> > > >  M:	Daire McNamara <daire.mcnamara@microchip.com>
> > > > -- 
> > > > 2.38.1
> > > > 
> > > > 
> > > > _______________________________________________
> > > > linux-riscv mailing list
> > > > linux-riscv@lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: "Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Jiri Slaby" <jirislaby@kernel.org>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org
Subject: Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC
Date: Mon, 28 Nov 2022 22:34:38 +0800	[thread overview]
Message-ID: <Y4TG/iM0ibf65Iua@xhacker> (raw)
In-Reply-To: <Y4TF8FzX19puws37@xhacker>

On Mon, Nov 28, 2022 at 10:30:15PM +0800, Jisheng Zhang wrote:
> On Sun, Nov 27, 2022 at 05:36:53PM +0000, Conor Dooley wrote:
> > On Sun, Nov 27, 2022 at 05:35:48PM +0000, Conor Dooley wrote:
> > > Hey Jisheng,
> > > 
> > > On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote:
> > > > Add Jisheng Zhang as Bouffalolab SoC maintainer.
> > > > 
> > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > ---
> > > >  MAINTAINERS | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > > 
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index 00ff4a2949b8..a6b04249853c 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -17729,6 +17729,15 @@ F:	arch/riscv/
> > > >  N:	riscv
> > > >  K:	riscv
> > > >  
> > > > +RISC-V BOUFFALOLAB SOC SUPPORT
> > > > +M:	Jisheng Zhang <jszhang@kernel.org>
> > > > +L:	linux-riscv@lists.infradead.org
> > > > +S:	Maintained
> > > > +F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> > > > +F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> > > > +F:	arch/riscv/boot/dts/bouffalolab/
> > > > +F:	drivers/tty/serial/bflb_uart.c
> > > 
> > > I think I asked last time but I didn't see an answer on lore or my
> > > mailbox - if you intend sending Arnd PRs for this stuff, please add a
> 
> Per my past experience of synaptics/mrvl arm SoCs, I usually sent PRs to Arnd
> if there are two or more commits/patches; If there's only one patch, I
> asked Arnd for picking it up directly. So in bouffalolab SoC case, I
> want to do similar, but with one difference -- if there's only one
> patch, may I ask you for picking it up directly?

That's to say: If there are two or more commits/patches, I will send
Arnd PRs; If there's only one commit/patch, I will ask your help to
picking it up directly.

> 
> > > git tree here. Otherwise, LMK and I'll bundle it with the other "misc
> 
> Hmm, is "git tree" necessary?
> 
> > > riscv devicetree" stuff.
> > 
> > I forgot:
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > 
> > > >  RISC-V MICROCHIP FPGA SUPPORT
> > > >  M:	Conor Dooley <conor.dooley@microchip.com>
> > > >  M:	Daire McNamara <daire.mcnamara@microchip.com>
> > > > -- 
> > > > 2.38.1
> > > > 
> > > > 
> > > > _______________________________________________
> > > > linux-riscv mailing list
> > > > linux-riscv@lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-11-28 14:44 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-27 13:24 [PATCH v2 0/9] riscv: add Bouffalolab bl808 support Jisheng Zhang
2022-11-27 13:24 ` Jisheng Zhang
2022-11-27 13:24 ` [PATCH v2 1/9] dt-bindings: serial: add documentation for Bouffalolab UART Driver Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-30  5:45   ` Samuel Holland
2022-11-30  5:45     ` Samuel Holland
2022-12-01 11:02   ` Krzysztof Kozlowski
2022-12-01 11:02     ` Krzysztof Kozlowski
2022-11-27 13:24 ` [PATCH v2 2/9] serial: bflb_uart: add " Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-28  6:10   ` Jiri Slaby
2022-11-28  6:10     ` Jiri Slaby
2022-11-28 14:21     ` Jisheng Zhang
2022-11-28 14:21       ` Jisheng Zhang
2022-11-28 16:01       ` Ilpo Järvinen
2022-11-28 16:01         ` Ilpo Järvinen
2022-11-28 23:20         ` Jisheng Zhang
2022-11-28 23:20           ` Jisheng Zhang
2022-11-29  6:32           ` Jiri Slaby
2022-11-29  6:32             ` Jiri Slaby
2022-12-05 20:03   ` kernel test robot
2022-12-05 20:03     ` kernel test robot
2022-11-27 13:24 ` [PATCH v2 3/9] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-30  6:48   ` Samuel Holland
2022-11-30  6:48     ` Samuel Holland
2022-11-27 13:24 ` [PATCH v2 4/9] dt-bindings: vendor-prefixes: add bouffalolab Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:23   ` Conor Dooley
2022-11-27 17:23     ` Conor Dooley
2022-12-01 11:03   ` Krzysztof Kozlowski
2022-12-01 11:03     ` Krzysztof Kozlowski
2022-11-27 13:24 ` [PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 16:25   ` Rob Herring
2022-11-27 16:25     ` Rob Herring
2022-11-27 17:29   ` Conor Dooley
2022-11-27 17:29     ` Conor Dooley
2022-12-01 11:05   ` Krzysztof Kozlowski
2022-12-01 11:05     ` Krzysztof Kozlowski
2022-12-01 11:14     ` Conor Dooley
2022-12-01 11:14       ` Conor Dooley
2022-12-01 11:41       ` Krzysztof Kozlowski
2022-12-01 11:41         ` Krzysztof Kozlowski
2022-11-27 13:24 ` [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:21   ` Conor Dooley
2022-11-27 17:21     ` Conor Dooley
2022-11-28  9:52     ` Icenowy Zheng
2022-11-28  9:52       ` Icenowy Zheng
2022-11-28 14:52       ` Conor Dooley
2022-11-28 14:52         ` Conor Dooley
2022-11-30  7:21   ` Samuel Holland
2022-11-30  7:21     ` Samuel Holland
2022-12-05  8:17     ` Icenowy Zheng
2022-12-05  8:17       ` Icenowy Zheng
2022-12-05 10:29       ` Conor Dooley
2022-12-05 10:29         ` Conor Dooley
2023-01-04  8:32   ` Michael Walle
2023-01-04  8:32     ` Michael Walle
2022-11-27 13:24 ` [PATCH v2 7/9] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:32   ` Conor Dooley
2022-11-27 17:32     ` Conor Dooley
2022-11-30  7:25   ` Samuel Holland
2022-11-30  7:25     ` Samuel Holland
2022-12-05  8:15     ` Icenowy Zheng
2022-12-05  8:15       ` Icenowy Zheng
2022-11-27 13:24 ` [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:35   ` Conor Dooley
2022-11-27 17:35     ` Conor Dooley
2022-11-27 17:36     ` Conor Dooley
2022-11-27 17:36       ` Conor Dooley
2022-11-28 14:30       ` Jisheng Zhang
2022-11-28 14:30         ` Jisheng Zhang
2022-11-28 14:34         ` Jisheng Zhang [this message]
2022-11-28 14:34           ` Jisheng Zhang
2022-11-28 14:50         ` Conor Dooley
2022-11-28 14:50           ` Conor Dooley
2022-11-30  7:27   ` Samuel Holland
2022-11-30  7:27     ` Samuel Holland
2022-11-27 13:24 ` [PATCH v2 9/9] riscv: defconfig: enable BOUFFALOLAB SoC Jisheng Zhang
2022-11-27 13:24   ` Jisheng Zhang
2022-11-27 17:36   ` Conor Dooley
2022-11-27 17:36     ` Conor Dooley
2022-12-02 17:54 ` [PATCH v2 0/9] riscv: add Bouffalolab bl808 support Palmer Dabbelt
2022-12-02 17:54   ` Palmer Dabbelt

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