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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozfN6-002J3Y-Dg; Mon, 28 Nov 2022 14:44:36 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozfN3-002J10-LQ for linux-riscv@lists.infradead.org; Mon, 28 Nov 2022 14:44:35 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DCFFD611C8; Mon, 28 Nov 2022 14:44:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5A4A1C433C1; Mon, 28 Nov 2022 14:44:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669646672; bh=CbaAnBCuYu+p+UM9W360R4cey3oGnj8pLzKqxqy8XvU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=RodtObudbG8bTHmKvie0yVRlfVrZptmw9XXByMIPO5LtqwEW/5b4M3XhWuX+ZSz40 9B6oL+NFt90t5KBYwWkerqJcOqX9S7OCT/ceDeQB0q0NR6tqStRlvdrJNkfqlcKOyA k+vKWq0Yblo1L0WOFNVxm7gqFVNeFXXola86g9FJTuXrY1PZXA/szlQHMl+RpbGpWA h8SG7ikczPJ+7su5TsPuRV0Yde1KLjs6vpkOT3/qlQl4qEoRUbXh+BT+wPXSGDSLpt f1SQdZkiHVpqVTUe/MKmHTagtKXs/2uuTDU7CsSywrOAXrO7HtwJJoQoVe9M/Gv9xh ixJgqkKQP8IVA== Date: Mon, 28 Nov 2022 22:34:38 +0800 From: Jisheng Zhang To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Greg Kroah-Hartman , Jiri Slaby , Ilpo =?utf-8?B?SsOkcnZpbmVu?= , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC Message-ID: References: <20221127132448.4034-1-jszhang@kernel.org> <20221127132448.4034-9-jszhang@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221128_064433_811498_7A529415 X-CRM114-Status: GOOD ( 25.30 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Nov 28, 2022 at 10:30:15PM +0800, Jisheng Zhang wrote: > On Sun, Nov 27, 2022 at 05:36:53PM +0000, Conor Dooley wrote: > > On Sun, Nov 27, 2022 at 05:35:48PM +0000, Conor Dooley wrote: > > > Hey Jisheng, > > > > > > On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote: > > > > Add Jisheng Zhang as Bouffalolab SoC maintainer. > > > > > > > > Signed-off-by: Jisheng Zhang > > > > --- > > > > MAINTAINERS | 9 +++++++++ > > > > 1 file changed, 9 insertions(+) > > > > > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > > > index 00ff4a2949b8..a6b04249853c 100644 > > > > --- a/MAINTAINERS > > > > +++ b/MAINTAINERS > > > > @@ -17729,6 +17729,15 @@ F: arch/riscv/ > > > > N: riscv > > > > K: riscv > > > > > > > > +RISC-V BOUFFALOLAB SOC SUPPORT > > > > +M: Jisheng Zhang > > > > +L: linux-riscv@lists.infradead.org > > > > +S: Maintained > > > > +F: Documentation/devicetree/bindings/riscv/bouffalolab.yaml > > > > +F: Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml > > > > +F: arch/riscv/boot/dts/bouffalolab/ > > > > +F: drivers/tty/serial/bflb_uart.c > > > > > > I think I asked last time but I didn't see an answer on lore or my > > > mailbox - if you intend sending Arnd PRs for this stuff, please add a > > Per my past experience of synaptics/mrvl arm SoCs, I usually sent PRs to Arnd > if there are two or more commits/patches; If there's only one patch, I > asked Arnd for picking it up directly. So in bouffalolab SoC case, I > want to do similar, but with one difference -- if there's only one > patch, may I ask you for picking it up directly? That's to say: If there are two or more commits/patches, I will send Arnd PRs; If there's only one commit/patch, I will ask your help to picking it up directly. > > > > git tree here. Otherwise, LMK and I'll bundle it with the other "misc > > Hmm, is "git tree" necessary? > > > > riscv devicetree" stuff. > > > > I forgot: > > Reviewed-by: Conor Dooley > > > > > > RISC-V MICROCHIP FPGA SUPPORT > > > > M: Conor Dooley > > > > M: Daire McNamara > > > > -- > > > > 2.38.1 > > > > > > > > > > > > _______________________________________________ > > > > linux-riscv mailing list > > > > linux-riscv@lists.infradead.org > > > > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E3E6C433FE for ; Mon, 28 Nov 2022 14:45:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231587AbiK1Opb (ORCPT ); Mon, 28 Nov 2022 09:45:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232673AbiK1OpE (ORCPT ); Mon, 28 Nov 2022 09:45:04 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6807823BF6; Mon, 28 Nov 2022 06:44:33 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EB607611E1; Mon, 28 Nov 2022 14:44:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5A4A1C433C1; Mon, 28 Nov 2022 14:44:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669646672; bh=CbaAnBCuYu+p+UM9W360R4cey3oGnj8pLzKqxqy8XvU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=RodtObudbG8bTHmKvie0yVRlfVrZptmw9XXByMIPO5LtqwEW/5b4M3XhWuX+ZSz40 9B6oL+NFt90t5KBYwWkerqJcOqX9S7OCT/ceDeQB0q0NR6tqStRlvdrJNkfqlcKOyA k+vKWq0Yblo1L0WOFNVxm7gqFVNeFXXola86g9FJTuXrY1PZXA/szlQHMl+RpbGpWA h8SG7ikczPJ+7su5TsPuRV0Yde1KLjs6vpkOT3/qlQl4qEoRUbXh+BT+wPXSGDSLpt f1SQdZkiHVpqVTUe/MKmHTagtKXs/2uuTDU7CsSywrOAXrO7HtwJJoQoVe9M/Gv9xh ixJgqkKQP8IVA== Date: Mon, 28 Nov 2022 22:34:38 +0800 From: Jisheng Zhang To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Greg Kroah-Hartman , Jiri Slaby , Ilpo =?utf-8?B?SsOkcnZpbmVu?= , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC Message-ID: References: <20221127132448.4034-1-jszhang@kernel.org> <20221127132448.4034-9-jszhang@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 28, 2022 at 10:30:15PM +0800, Jisheng Zhang wrote: > On Sun, Nov 27, 2022 at 05:36:53PM +0000, Conor Dooley wrote: > > On Sun, Nov 27, 2022 at 05:35:48PM +0000, Conor Dooley wrote: > > > Hey Jisheng, > > > > > > On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote: > > > > Add Jisheng Zhang as Bouffalolab SoC maintainer. > > > > > > > > Signed-off-by: Jisheng Zhang > > > > --- > > > > MAINTAINERS | 9 +++++++++ > > > > 1 file changed, 9 insertions(+) > > > > > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > > > index 00ff4a2949b8..a6b04249853c 100644 > > > > --- a/MAINTAINERS > > > > +++ b/MAINTAINERS > > > > @@ -17729,6 +17729,15 @@ F: arch/riscv/ > > > > N: riscv > > > > K: riscv > > > > > > > > +RISC-V BOUFFALOLAB SOC SUPPORT > > > > +M: Jisheng Zhang > > > > +L: linux-riscv@lists.infradead.org > > > > +S: Maintained > > > > +F: Documentation/devicetree/bindings/riscv/bouffalolab.yaml > > > > +F: Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml > > > > +F: arch/riscv/boot/dts/bouffalolab/ > > > > +F: drivers/tty/serial/bflb_uart.c > > > > > > I think I asked last time but I didn't see an answer on lore or my > > > mailbox - if you intend sending Arnd PRs for this stuff, please add a > > Per my past experience of synaptics/mrvl arm SoCs, I usually sent PRs to Arnd > if there are two or more commits/patches; If there's only one patch, I > asked Arnd for picking it up directly. So in bouffalolab SoC case, I > want to do similar, but with one difference -- if there's only one > patch, may I ask you for picking it up directly? That's to say: If there are two or more commits/patches, I will send Arnd PRs; If there's only one commit/patch, I will ask your help to picking it up directly. > > > > git tree here. Otherwise, LMK and I'll bundle it with the other "misc > > Hmm, is "git tree" necessary? > > > > riscv devicetree" stuff. > > > > I forgot: > > Reviewed-by: Conor Dooley > > > > > > RISC-V MICROCHIP FPGA SUPPORT > > > > M: Conor Dooley > > > > M: Daire McNamara > > > > -- > > > > 2.38.1 > > > > > > > > > > > > _______________________________________________ > > > > linux-riscv mailing list > > > > linux-riscv@lists.infradead.org > > > > http://lists.infradead.org/mailman/listinfo/linux-riscv