On Thu, Dec 15, 2022 at 05:17:30PM +0000, Andrew Cooper wrote:
> On 15/12/2022 8:49 am, Jan Beulich wrote:
> > On 15.12.2022 00:11, Demi Marie Obenour wrote:
> >> --- a/xen/arch/x86/include/asm/x86-defns.h
> >> +++ b/xen/arch/x86/include/asm/x86-defns.h
> >> @@ -153,4 +153,15 @@
> >>       (1u << X86_EXC_AC) | (1u << X86_EXC_CP) |                      \
> >>       (1u << X86_EXC_VC) | (1u << X86_EXC_SX))
> >>  
> >> +/* Memory types */
> >> +#define X86_MT_UC         0x00 /* uncachable */
> >> +#define X86_MT_WC         0x01 /* write-combined */
> >> +#define X86_MT_RESERVED_1 0x02 /* reserved */
> >> +#define X86_MT_RESERVED_2 0x03 /* reserved */
> > As said, unless there's a good reason to use 1 and 2 (and not e.g.
> > 0 and 1), I'd prefer these to be numbered 2 and 3 to match the
> > values they expand to (and the numbering then not being as arbitrary).
> 
> TBH, I'd prefer not having them in the first place (I'll see if there's
> a way to simplify the build assertions which are the only users I can
> spot), but if we are going to have them then do use 2 and 3, and its
> fine to abbreviate to RSVD.

They will be needed when the NPT code starts to use these constants, as
EPT_EMT_RSV0 and EPT_EMT_RSV1 are used.
-- 
Sincerely,
Demi Marie Obenour (she/her/hers)
Invisible Things Lab