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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id v7-20020a1709028d8700b00186bc66d2cbsm9582949plo.73.2023.01.11.00.19.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 00:19:37 -0800 (PST) Date: Wed, 11 Jan 2023 09:19:34 +0100 From: Jiri Pirko To: Jakub Kicinski Cc: "Kubalewski, Arkadiusz" , Maciek Machnikowski , 'Vadim Fedorenko' , 'Jonathan Lemon' , 'Paolo Abeni' , "netdev@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" Subject: Re: [RFC PATCH v4 0/4] Create common DPLL/clock configuration API Message-ID: References: <20221206184740.28cb7627@kernel.org> <10bb01d90a45$77189060$6549b120$@gmail.com> <20221207152157.6185b52b@kernel.org> <6e252f6d-283e-7138-164f-092709bc1292@machnikowski.net> <20221209083104.2469ebd6@kernel.org> <20230110120549.4d764609@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230110120549.4d764609@kernel.org> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Tue, Jan 10, 2023 at 09:05:49PM CET, kuba@kernel.org wrote: >On Mon, 9 Jan 2023 14:43:01 +0000 Kubalewski, Arkadiusz wrote: >> This is a simplified network switch board example. >> It has 2 synchronization channels, where each channel: >> - provides clk to 8 PHYs driven by separated MAC chips, >> - controls 2 DPLLs. >> >> Basically only given FW has control over its PHYs, so also a control over it's >> MUX inputs. >> All external sources are shared between the channels. >> >> This is why we believe it is not best idea to enclose multiple DPLLs with one >> object: >> - sources are shared even if DPLLs are not a single synchronizer chip, >> - control over specific MUX type input shall be controllable from different >> driver/firmware instances. >> >> As we know the proposal of having multiple DPLLs in one object was a try to >> simplify currently implemented shared pins. We fully support idea of having >> interfaces as simple as possible, but at the same time they shall be flexible >> enough to serve many use cases. > >I must be missing context from other discussions but what is this >proposal trying to solve? Well implemented shared pins is all we need. There is an entity containing the pins. The synchronizer chip. One synchronizer chip contains 1-n DPLLs. The source pins are connected to each DPLL (usually). What we missed in the original model was the synchronizer entity. If we have it, we don't need any notion of somehow floating pins as independent entities being attached to one or many DPLL refcounted, etc. The synchronizer device holds them in straightforward way. Example of a synchronizer chip: https://www.renesas.com/us/en/products/clocks-timing/jitter-attenuators-frequency-translation/8a34044-multichannel-dpll-dco-four-eight-channels#overview From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73531C5479D for ; Wed, 11 Jan 2023 08:20:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ymt60Nm+NhJtCg+L8IkjJCZG3zKjTCyzfRMKS6xH0qE=; b=Er6XPxqRrR/alS pN98D8T3TIFSU0mgzTxCIYKdsXLzEcmPCf+wh5oX3SrAUPXnnbUvSzKTkNpcvRGnvNUtotTv5GYC1 WUa65lTej/JMo/UyLMCcv/8aAKA6EfPR6dTwXmst40O8aDHd/maqJYucrawcLX2k40fl4jCMCojSt HXkVTO+eFBg4YPluzIxtGWYUbMhLfm35CSzby0nGNDRfhvTST1VGajPPoEzL7SOMLst/WNO3ZvkGr 5kdtQGNIDFEygTel+SFnTg9ZnMK5hooLsPdVELJf4nU2GEZZP+cqVodveFxc5o3xl8pno3JXeBIT2 iMe7MxbTFQfZQ1tIl7uA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pFWKp-00AK5s-4Q; Wed, 11 Jan 2023 08:19:47 +0000 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pFWKj-00AK3x-PH for linux-arm-kernel@lists.infradead.org; Wed, 11 Jan 2023 08:19:45 +0000 Received: by mail-pl1-x641.google.com with SMTP id y1so16020486plb.2 for ; Wed, 11 Jan 2023 00:19:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=resnulli-us.20210112.gappssmtp.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=XGrxh5RU1Q9X5xnd06++hlbzr5xDY2Wv8eguXMCmuQ8=; b=BorcWx8o+oTOqTKzgqgjnCr6QxuUNH80ocGTwKkMrgzdxxsO85cZLtVLDfq0KAUquO UpyT7BK9pVj+RFGaTAX7QIGZbUfFEC9rTG0ABk1Cp0pSYehAYz6hFTApsJcaTlZr5mFF QOMUtg+dGAVne2avL1kqxz1seqMMnui7rp12UrA/c9WPjRcUxGuy2Bht8+jNjofhTi7J EoX9LYnN2Uc4WBGBs4XqztUZ+UcjYNKGmrFHBJko7PfUJD5QHv9oxF+fshFqBV5etVVK jj7pNtYybJAbT+mNHSK/hX3pYvpU+clq1Gi5/DLnOi+RJbgwWBWFIeBhRv5dr3uzMR/5 2t8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=XGrxh5RU1Q9X5xnd06++hlbzr5xDY2Wv8eguXMCmuQ8=; b=pwHArqLZHYUg9wdXLw0jc6xXQsnOmgeo9fAO/X6tWX22NxV/tIewQnxva0XOYTfuv/ 5tlCMzLJn9zrrNBDHeklmVoW14dN1CePEswDVy/qLdmZTvhBYyCrljmAnHWkTLMblRGP R89FEcK6Qt4Ob9Rg7Yv41iK/7iEceGC4GFfcmHbPyU1ZHVhh76ruCSU9W2vdqIrB2gTh Ldc+c8sIKCD6927cQ2hxGwGc9DVgKfhTzp3IKsjkVmCAyl1B0WVQ4mLuRKkQN8aEZUHZ Qfy6CMRlyuFQPbeySPrbATCdAD5QyVJ73H0SPMye1h16GeXtSZe/CXKLpcEefF5qVig7 R0fQ== X-Gm-Message-State: AFqh2kry6dMlFRgOndQq7hVEz3jt4h3NDZ9fW2luuVF60yXdRkqfqfHS dG9Xs4TZkcoBtY1NLJ8+zYRp5g== X-Google-Smtp-Source: AMrXdXv8HEGTtHE38l6uIqkffBd2HJNr7lYLCc9XR2w8PzGrwGHjx8fKXytQGmrKPSCOQLMTsj6lrA== X-Received: by 2002:a17:902:c94b:b0:189:76ef:e112 with SMTP id i11-20020a170902c94b00b0018976efe112mr95588728pla.41.1673425177760; Wed, 11 Jan 2023 00:19:37 -0800 (PST) Received: from localhost (thunderhill.nvidia.com. [216.228.112.22]) by smtp.gmail.com with ESMTPSA id v7-20020a1709028d8700b00186bc66d2cbsm9582949plo.73.2023.01.11.00.19.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 00:19:37 -0800 (PST) Date: Wed, 11 Jan 2023 09:19:34 +0100 From: Jiri Pirko To: Jakub Kicinski Cc: "Kubalewski, Arkadiusz" , Maciek Machnikowski , 'Vadim Fedorenko' , 'Jonathan Lemon' , 'Paolo Abeni' , "netdev@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" Subject: Re: [RFC PATCH v4 0/4] Create common DPLL/clock configuration API Message-ID: References: <20221206184740.28cb7627@kernel.org> <10bb01d90a45$77189060$6549b120$@gmail.com> <20221207152157.6185b52b@kernel.org> <6e252f6d-283e-7138-164f-092709bc1292@machnikowski.net> <20221209083104.2469ebd6@kernel.org> <20230110120549.4d764609@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230110120549.4d764609@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230111_001942_029230_B1BB6C4E X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Tue, Jan 10, 2023 at 09:05:49PM CET, kuba@kernel.org wrote: >On Mon, 9 Jan 2023 14:43:01 +0000 Kubalewski, Arkadiusz wrote: >> This is a simplified network switch board example. >> It has 2 synchronization channels, where each channel: >> - provides clk to 8 PHYs driven by separated MAC chips, >> - controls 2 DPLLs. >> >> Basically only given FW has control over its PHYs, so also a control over it's >> MUX inputs. >> All external sources are shared between the channels. >> >> This is why we believe it is not best idea to enclose multiple DPLLs with one >> object: >> - sources are shared even if DPLLs are not a single synchronizer chip, >> - control over specific MUX type input shall be controllable from different >> driver/firmware instances. >> >> As we know the proposal of having multiple DPLLs in one object was a try to >> simplify currently implemented shared pins. We fully support idea of having >> interfaces as simple as possible, but at the same time they shall be flexible >> enough to serve many use cases. > >I must be missing context from other discussions but what is this >proposal trying to solve? Well implemented shared pins is all we need. There is an entity containing the pins. The synchronizer chip. One synchronizer chip contains 1-n DPLLs. The source pins are connected to each DPLL (usually). What we missed in the original model was the synchronizer entity. If we have it, we don't need any notion of somehow floating pins as independent entities being attached to one or many DPLL refcounted, etc. The synchronizer device holds them in straightforward way. Example of a synchronizer chip: https://www.renesas.com/us/en/products/clocks-timing/jitter-attenuators-frequency-translation/8a34044-multichannel-dpll-dco-four-eight-channels#overview _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel