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From: Johan Hovold <johan@kernel.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: "Andy Gross" <agross@kernel.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konrad.dybcio@linaro.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"vkoul@kernel.org" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 11/12] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes
Date: Mon, 23 Jan 2023 15:24:28 +0100	[thread overview]
Message-ID: <Y86YnAxmTcQTmqwH@hovoldconsulting.com> (raw)
In-Reply-To: <Y86WqGW6pj5re3FU@hovoldconsulting.com>

On Mon, Jan 23, 2023 at 03:16:09PM +0100, Johan Hovold wrote:
> On Mon, Jan 23, 2023 at 02:39:55PM +0200, Abel Vesa wrote:
> > On 23-01-23 09:51:20, Johan Hovold wrote:
 
> > > > +		pcie1_phy: phy@1c0e000 {
> > > > +			compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
> > > > +			reg = <0x0 0x01c0e000 0x0 0x2000>;
> > > > +
> > > > +			clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
> > > > +				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> > > > +				 <&tcsr TCSR_PCIE_1_CLKREF_EN>,
> > > > +				 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
> > > > +				 <&gcc GCC_PCIE_1_PIPE_CLK>;
> > > > +			clock-names = "aux", "cfg_ahb", "ref", "rchng",
> > > > +				      "pipe";
> > > > +
> > > > +			resets = <&gcc GCC_PCIE_1_PHY_BCR>,
> > > > +				 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
> > > > +			reset-names = "phy", "nocsr";
> > > 
> > > Do you know why only the second PHY uses two resets here? Did you intend
> > > to add it also for the first PHY?
> > 
> > Please notice that this is a g4x2 phy. The documentation specifically
> > says that both the pciephy_reset and pciephy_nocsr_reset should be
> > asserted on power-up. Now, even the g3x2 has the nocsr reset (at least
> > in GCC) but its documentation doesn't seem to say anything about
> > nocsr needed to be asserted (ever).
> 
> Ok. Thanks for confirming. I did not notice the difference in generation
> at first.
> 
> > > Both of these resets exists also on sc8280xp, and I believe downstream
> > > used the NOCSR_COM variant, which does not reset all registers in the
> > > PHY so you could unknowingly be relying on firmware to setup things up
> > > for you.
> > 
> > That is also the case for the g3x2 phy on sm8550.

One more thing: Shouldn't the second reset be named 'nocsr_com' or
similar?

Johan

WARNING: multiple messages have this Message-ID (diff)
From: Johan Hovold <johan@kernel.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: "Andy Gross" <agross@kernel.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konrad.dybcio@linaro.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"vkoul@kernel.org" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 11/12] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes
Date: Mon, 23 Jan 2023 15:24:28 +0100	[thread overview]
Message-ID: <Y86YnAxmTcQTmqwH@hovoldconsulting.com> (raw)
In-Reply-To: <Y86WqGW6pj5re3FU@hovoldconsulting.com>

On Mon, Jan 23, 2023 at 03:16:09PM +0100, Johan Hovold wrote:
> On Mon, Jan 23, 2023 at 02:39:55PM +0200, Abel Vesa wrote:
> > On 23-01-23 09:51:20, Johan Hovold wrote:
 
> > > > +		pcie1_phy: phy@1c0e000 {
> > > > +			compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
> > > > +			reg = <0x0 0x01c0e000 0x0 0x2000>;
> > > > +
> > > > +			clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
> > > > +				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> > > > +				 <&tcsr TCSR_PCIE_1_CLKREF_EN>,
> > > > +				 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
> > > > +				 <&gcc GCC_PCIE_1_PIPE_CLK>;
> > > > +			clock-names = "aux", "cfg_ahb", "ref", "rchng",
> > > > +				      "pipe";
> > > > +
> > > > +			resets = <&gcc GCC_PCIE_1_PHY_BCR>,
> > > > +				 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
> > > > +			reset-names = "phy", "nocsr";
> > > 
> > > Do you know why only the second PHY uses two resets here? Did you intend
> > > to add it also for the first PHY?
> > 
> > Please notice that this is a g4x2 phy. The documentation specifically
> > says that both the pciephy_reset and pciephy_nocsr_reset should be
> > asserted on power-up. Now, even the g3x2 has the nocsr reset (at least
> > in GCC) but its documentation doesn't seem to say anything about
> > nocsr needed to be asserted (ever).
> 
> Ok. Thanks for confirming. I did not notice the difference in generation
> at first.
> 
> > > Both of these resets exists also on sc8280xp, and I believe downstream
> > > used the NOCSR_COM variant, which does not reset all registers in the
> > > PHY so you could unknowingly be relying on firmware to setup things up
> > > for you.
> > 
> > That is also the case for the g3x2 phy on sm8550.

One more thing: Shouldn't the second reset be named 'nocsr_com' or
similar?

Johan

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2023-01-23 14:24 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-19 14:04 [PATCH v4 00/12] sm8550: Add PCIe HC and PHY support Abel Vesa
2023-01-19 14:04 ` Abel Vesa
2023-01-19 14:04 ` [PATCH v4 01/12] dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-22 14:09   ` Krzysztof Kozlowski
2023-01-22 14:09     ` Krzysztof Kozlowski
2023-01-19 14:04 ` [PATCH v4 02/12] phy: qcom-qmp: pcs: Add v6 register offsets Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-19 14:04 ` [PATCH v4 03/12] phy: qcom-qmp: pcs: Add v6.20 " Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-19 14:04 ` [PATCH v4 04/12] phy: qcom-qmp: pcs-pcie: Add v6 " Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-19 14:04 ` [PATCH v4 05/12] phy: qcom-qmp: pcs-pcie: Add v6.20 " Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-19 14:04 ` [PATCH v4 06/12] phy: qcom-qmp: qserdes-txrx: " Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-19 14:04 ` [PATCH v4 07/12] phy: qcom-qmp: qserdes-lane-shared: Add v6 " Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-19 14:04 ` [PATCH v4 08/12] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-23 15:03   ` Johan Hovold
2023-01-23 15:03     ` Johan Hovold
2023-01-23 19:42     ` Abel Vesa
2023-01-23 19:42       ` Abel Vesa
2023-01-19 14:04 ` [PATCH v4 09/12] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-22 14:10   ` Krzysztof Kozlowski
2023-01-22 14:10     ` Krzysztof Kozlowski
2023-01-23 10:44     ` Abel Vesa
2023-01-23 10:44       ` Abel Vesa
2023-01-23 11:03       ` Krzysztof Kozlowski
2023-01-23 11:03         ` Krzysztof Kozlowski
2023-01-19 14:04 ` [PATCH v4 10/12] PCI: qcom: Add SM8550 PCIe support Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-19 14:21   ` Manivannan Sadhasivam
2023-01-19 14:21     ` Manivannan Sadhasivam
2023-01-19 15:35     ` Abel Vesa
2023-01-19 15:35       ` Abel Vesa
2023-01-23  8:27       ` Johan Hovold
2023-01-23  8:27         ` Johan Hovold
2023-01-19 14:04 ` [PATCH v4 11/12] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes Abel Vesa
2023-01-19 14:04   ` Abel Vesa
2023-01-23  8:51   ` Johan Hovold
2023-01-23  8:51     ` Johan Hovold
2023-01-23 12:39     ` Abel Vesa
2023-01-23 12:39       ` Abel Vesa
2023-01-23 13:11       ` Abel Vesa
2023-01-23 13:11         ` Abel Vesa
2023-01-23 14:17         ` Johan Hovold
2023-01-23 14:17           ` Johan Hovold
2023-01-23 14:16       ` Johan Hovold
2023-01-23 14:16         ` Johan Hovold
2023-01-23 14:24         ` Johan Hovold [this message]
2023-01-23 14:24           ` Johan Hovold
2023-01-19 14:04 ` [PATCH v4 12/12] arm64: dts: qcom: sm8550-mtp: " Abel Vesa
2023-01-19 14:04   ` Abel Vesa

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