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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id z2-20020aa79f82000000b00593c679d405sm2210624pfr.78.2023.01.30.09.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 09:30:07 -0800 (PST) Date: Mon, 30 Jan 2023 17:30:04 +0000 From: Sean Christopherson To: "Yang, Weijiang" Cc: pbonzini@redhat.com, jmattson@google.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, like.xu.linux@gmail.com, kan.liang@linux.intel.com, wei.w.wang@intel.com Subject: Re: [PATCH v2 14/15] KVM: x86: Add Arch LBR data MSR access interface Message-ID: References: <20221125040604.5051-1-weijiang.yang@intel.com> <20221125040604.5051-15-weijiang.yang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 30, 2023, Yang, Weijiang wrote: > > On 1/28/2023 6:13 AM, Sean Christopherson wrote: > > On Thu, Nov 24, 2022, Yang Weijiang wrote: > > > Arch LBR MSRs are xsave-supported, but they're operated as "independent" > > > xsave feature by PMU code, i.e., during thread/process context switch, > > > the MSRs are saved/restored with perf_event_task_sched_{in|out} instead > > > of generic kernel fpu switch code, i.e.,save_fpregs_to_fpstate() and > > > restore_fpregs_from_fpstate(). When vcpu guest/host fpu state swap happens, > > > Arch LBR MSRs are retained so they can be accessed directly. > > > > > > Signed-off-by: Yang Weijiang > > > Reviewed-by: Kan Liang > > > --- > > > arch/x86/kvm/vmx/pmu_intel.c | 10 ++++++++++ > > > 1 file changed, 10 insertions(+) > > > > > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > > > index b57944d5e7d8..241128972776 100644 > > > --- a/arch/x86/kvm/vmx/pmu_intel.c > > > +++ b/arch/x86/kvm/vmx/pmu_intel.c > > > @@ -410,6 +410,11 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > > > msr_info->data = vmcs_read64(GUEST_IA32_LBR_CTL); > > > } > > > return 0; > > > + case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31: > > > + case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31: > > > + case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31: > > > + rdmsrl(msr_info->index, msr_info->data); > > I don't see how this is correct. As called out in patch 5: > > > > : If for some magical reason it's safe to access arch LBR MSRs without disabling > > : IRQs and confirming perf event ownership, I want to see a very detailed changelog > > : explaining exactly how that magic works. > > The MSR lists here are just for live migration. When arch-lbr is active, > these MSRs are passed through to guest. None of that explains how the guest's MSR values are guaranteed to be resident in hardware.