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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?iso-8859-1?Q?ycGjDYu39uyaEY5MSnaWOmRWOY8CTaKdVIh5Zwke5dmjeSUoxY3b/YfU62?= =?iso-8859-1?Q?K+O0/RRj/XG+JXUDY3+D+os9d5k2s27lHc6RWbFGeJPeV2L5SE1VjzZM8C?= =?iso-8859-1?Q?Pqu1L6RyopEbGxdz78NQPICOwn5lNCFpHDKt9N0kKRVoAeD7r2cuzqV6eT?= =?iso-8859-1?Q?dQMLTzhxxt3YFQzMU+cgKIt7JKSrzKiXv9bwf/jotqzZ9g3fuDMFU9WMO+?= =?iso-8859-1?Q?0F7zhOG1AD1Z6UX3aCZA/mlSyS+cxAioTrrCyOhppLZd4DZtmXEwpaeuSq?= =?iso-8859-1?Q?26ptrc6X4mpWYISRJG/xKNZv+fHHVbomxybYfcpyum2BPbimFp9Fuv8f8J?= =?iso-8859-1?Q?jlhUo91QC3MCN2SjEFn4qTsrvHO+tq43aPy53EM6nwcCbeRisQpCG5W988?= =?iso-8859-1?Q?iL5YRA11x32lpjblatMGKBLYkgikM92dwNSph5f9nZ80xLQmS83SjPucmh?= =?iso-8859-1?Q?1MmY+nhrv3VNTmKsdBLNWRcea+SM5cQgAekZPTGw26V9sQY9281IKxTR7I?= =?iso-8859-1?Q?ix/+CLRuY3s4cNDCquuNo88vH1+LDD6SUGTMnelcQit7pGXrToB5sLuLmL?= =?iso-8859-1?Q?dEd7trL0aRQTsFFafJSqb0mMD32xCGtR5C55SkeQcolXikDYBRxemvYr/1?= =?iso-8859-1?Q?V1f3JJFKdKls2MGWo4F0+Q9oozZAdpSp8+YxceJlDHLNM2+IeHDZotHIxD?= =?iso-8859-1?Q?fCXHFgQVJ45jj12bkdllzxgctLXNUmH/6GCBji+CnjuGUgtV5JkLQNUiwi?= =?iso-8859-1?Q?AUciQZmxSSfLcUF8ns6m+bs/iG+kOKVi76jckdUV5G4kEn7YFUMJAVsj83?= =?iso-8859-1?Q?6wnM2/gh0to8pTzvIX3y6e7FkGuXpkQTPwPXpvPPwXXGr0Gvg5on9ycSEF?= =?iso-8859-1?Q?Haxbwkosfsh6Yn+rutJYSbx2JfpuS4Shwc3ErL6D1F7ewsq62zMgoczbZu?= =?iso-8859-1?Q?u6aiyh74/R7+VT5YYwatMSRVUcpV1TQ1FcL5O6Dp2Invwt7jFclDEnmIuh?= =?iso-8859-1?Q?sb8Wux+KF1x30I+IvpYiInzO+9w6+HdQqD6MVZmQ+cvI9bwwtVDoe9CXlc?= =?iso-8859-1?Q?2QnBuBdNvFZMc7IQ2t9wEAmOwik0OP+3zJQFoz4MlpvySWlbic5b6u86Ha?= =?iso-8859-1?Q?V7y5c8LH1r9lQtMLNPYASxI9rgUzROgcIUvyR6p5VTdw91C1061y1lQa/R?= =?iso-8859-1?Q?ULiBtt8rp8jyed5pOR4hmkoVTYLa/RfZue+Eva2GGgxKO6xhqEXT50MPPu?= =?iso-8859-1?Q?xeigdtYdXkee6+WfJmi5PNkufzX6m9NYkyWhusOvZJkp6q+y+OalUIE7rw?= =?iso-8859-1?Q?vspyMMJHD4KqDUCMZa2x32Nt7Yy6ONNqXru+eqJAC65i9V1+F7QajIdoAD?= =?iso-8859-1?Q?ydz1emdFYkV79NCqHcaim+tvdXUSlE/vOMX3ac0Ns0ZI+opkInyEFvPEVU?= =?iso-8859-1?Q?vbEG8jpe3a7NgbsgGcK+O6TXaz/t0kjETmUpg5wGBo4ls07Ed02CX47fcV?= =?iso-8859-1?Q?2Gl8PETZd7/+899omMO3zkdz2P8dIytbDa7hLSbpHNBbIUgI6W23kc+HqR?= =?iso-8859-1?Q?JQD96P8YYmLME9nd0AHKVx9WsEIDE5wDngwpmFU21FxmCleIhBcQPbYCZ9?= =?iso-8859-1?Q?d4IgKpQ9eFn9I4eKi1n8spcrQw4XVpU7KBgDkjalga58UPZqXYBJJq+g?= =?iso-8859-1?Q?=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 61a5dead-9a90-44cb-41a3-08db02e59da3 X-MS-Exchange-CrossTenant-AuthSource: DS7PR11MB7859.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2023 17:15:42.0264 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Rd76ALkD1tpectOzYt1ZonR4MBfIXbVMneiJJ8IhdhASSq084PkJmMKcJMfWdzIFd/sWsIZo0qErct8zVxDRpMWBLdPP4t4cmD2ArCc8Dak= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR11MB8009 X-OriginatorOrg: intel.com Subject: Re: [Intel-xe] [PATCH v2] drm/xe: Add fake workaround to maintain backward compatible in MI_BATCH_BUFFER_START X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , intel-xe@lists.freedesktop.org Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Mon, Jan 30, 2023 at 08:17:23AM -0800, José Roberto de Souza wrote: > i915 has the same fake workaround to return MI_BATCH_BUFFER_START > nested batch buffer behavior in DG2 and newer platforms to the same > behavior as older platforms. > > So here cleaning up TGL_NESTED_BB_EN in MI_MODE to disable third level > chained batch buffer level. I was kind of assuming we'd just drop this setting for the Xe driver. I believe hardware will be removing the option to turn off nested batchbuffers in an upcoming platform, so userspace is going to have to adapt to the new behavior soon anyway; doing it while moving to a new KMD seems like the easiest time to make that happen since the UMDs are already updating their programming models. Matt > > v2: > - replace IP_VERSION_FOREVER by XE_RTP_END_VERSION_UNDEFINED > - move fake workaround to lrc_additional_programming table > > Bspec: 45974, 45718 > Cc: Lucas De Marchi > Cc: Matt Roper > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/xe/xe_gt.c | 1 + > drivers/gpu/drm/xe/xe_wa.c | 28 ++++++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_wa.h | 1 + > 3 files changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c > index 84a73eeccd297..5d07e1e7bd506 100644 > --- a/drivers/gpu/drm/xe/xe_gt.c > +++ b/drivers/gpu/drm/xe/xe_gt.c > @@ -311,6 +311,7 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) > > xe_reg_sr_init(&hwe->reg_lrc, "LRC", xe); > xe_wa_process_lrc(hwe); > + xe_wa_process_lrc_additional_programming(hwe); > > default_lrc = drmm_kzalloc(&xe->drm, > xe_lrc_size(xe, hwe->class), > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c > index 3325de3edf691..744b7d0982683 100644 > --- a/drivers/gpu/drm/xe/xe_wa.c > +++ b/drivers/gpu/drm/xe/xe_wa.c > @@ -288,6 +288,21 @@ static const struct xe_rtp_entry lrc_was[] = { > {} > }; > > +static const struct xe_rtp_entry lrc_additional_programming[] = { > + { XE_RTP_NAME("FakeWaDisableNestedBBMode"), > + /* > + * This is a "fake" workaround defined by software to ensure we > + * maintain reliable, backward-compatible behavior for userspace with > + * regards to how nested MI_BATCH_BUFFER_START commands are handled. > + */ > + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED)), > + XE_RTP_CLR(RING_MI_MODE(0), > + TGL_NESTED_BB_EN, > + XE_RTP_FLAG(MASKED_REG, ENGINE_BASE)) > + }, > + {} > +}; > + > static const struct xe_rtp_entry register_whitelist[] = { > { XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"), > XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), > @@ -362,6 +377,19 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe) > xe_rtp_process(lrc_was, &hwe->reg_lrc, hwe->gt, hwe); > } > > +/** > + * xe_wa_process_lrc_additional_programming - process additional LRC programming > + * table > + * @hwe: engine instance to process workarounds for > + * > + * Process additional context programming table for this platform, saving in > + * @hwe all the registers changes that need to be applied on context restore. > + */ > +void xe_wa_process_lrc_additional_programming(struct xe_hw_engine *hwe) > +{ > + xe_rtp_process(lrc_additional_programming, &hwe->reg_lrc, hwe->gt, hwe); > +} > + > /** > * xe_reg_whitelist_process_engine - process table of registers to whitelist > * @hwe: engine instance to process whitelist for > diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h > index 1a0659690a320..872f3e4ddc73c 100644 > --- a/drivers/gpu/drm/xe/xe_wa.h > +++ b/drivers/gpu/drm/xe/xe_wa.h > @@ -12,6 +12,7 @@ struct xe_hw_engine; > void xe_wa_process_gt(struct xe_gt *gt); > void xe_wa_process_engine(struct xe_hw_engine *hwe); > void xe_wa_process_lrc(struct xe_hw_engine *hwe); > +void xe_wa_process_lrc_additional_programming(struct xe_hw_engine *hwe); > > void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe); > void xe_reg_whitelist_apply(struct xe_hw_engine *hwe); > -- > 2.39.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation